| Age | Commit message (Collapse) | Author |
|---|
|
Update generic id to generate the SSDT1 acpi table successfully
BUG=b:196866470
BRANCH=firmware-zork-13434.B
TEST=generate SSDT1 acpi table by command "iasl -d SSDT1"
Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Change-Id: I09c9adc2db08e8e3905d9ba800948252230e4d54
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57286
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
|
|
It turns out that putting a device ref in an overridetree at a different
point in the tree will generate a duplicate device definition, such that
the change introducing this support was ignoring the device presence
specified by overridetree.cb and only using the baseboard configuration.
I believe testing of that change was not redone after the baseboard was
changed to disable the MST, so that conflicting behavior was not
noticed.
The incorrect behavior generated a disabled device for the MST at the
location specified by the baseboard, and one with the probe as a child
of the soc. At runtime this did a fw_config probe of the "I2C 00:4a"
device, and later probed a different "I2C 00:4a" which was already
disabled. As the disabled one came later, it seems to have completely
disabled the MST, discarding the results of the variant-specific probe.
BUG=b:185862297
TEST=10EC2141 device is now present on a Dali berknip
BRANCH=zork
Change-Id: I2a8feb544f3fc198fe6313b226ad8995aad31c3e
Signed-off-by: Peter Marheine <pmarheine@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57298
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Now that the SPI configuration has been moved into Kconfig, it is no
longer needed in devicetree.
BUG=b:194919326
TEST=Build & boot guybrush
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: Ifdcd3f33173194c4a25794137756b143751edd70
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56962
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
|
|
This takes the devicetree SPI settings and moves them into Kconfig.
BUG=b:195943311
TEST=boot guybrush & majolica and verify spi settings.
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: Icce1d57761465ae8255e5d9ce8679f3fdcb0ceed
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56885
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
|
|
An MST hub is only present on some devices that are configured with a
particular daughterboard indicated by EC fw_config, so add a fw_config
probe that matches the USB daughterboard ID from CBI to only enable it
on devices where present, using variant-specific daughterboard IDs.
BUG=b:185862297
TEST=RTD2141 remains in ACPI tables on a berknip with Dali DB, and is
not present on the same system if probe is changed to enable it
for picasso DB.
BRANCH=zork
Change-Id: I4ada9b492ab221fa98350bf2faf27a23342f3a55
Signed-off-by: Peter Marheine <pmarheine@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56990
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sam McNally <sammc@google.com>
|
|
Specify the type of the `VARIANT_DIR` Kconfig symbol once instead of
doing so on each and every mainboard.
Change-Id: Iea2f992a59e41e00fec3cdc9d6a13b5f3ab0a437
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56558
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Specify the type of the `FMDFILE` Kconfig symbol once instead of doing
so on each and every mainboard.
Change-Id: I810bd3fe8d42102586db6c2c58b7037a60189257
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56557
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Specify the type of the `OVERRIDE_DEVICETREE` Kconfig symbol once
instead of doing so on each and every mainboard.
Change-Id: I4cbf4e318a30f0cf75aa8690e7454b9caa115c9d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56556
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Specify the type of the `DEVICETREE` Kconfig symbol once instead of
doing so on each and every mainboard.
Change-Id: If68f11a5ceaa67a3e8218f89e1138c247ebb9a25
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56555
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Specify the type of the `MAINBOARD_PART_NUMBER` Kconfig symbol once
instead of doing so on each and every mainboard.
Change-Id: I3692f9e82fe90af4d0da1d037018a20aa1b45793
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56554
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Specify the type of the `MAINBOARD_DIR` Kconfig symbol once instead of
doing so on each and every mainboard.
Change-Id: If1cc538b0c4938dac193699897b690e402b3c1e8
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56553
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
It appears the pspp_policy enum is not the same as the FSP definition
currently being used. This means that the incorrect PSPP value setting
would get read by FSP. For Zork programs this meant we actually were
setting links as DXIO_PSPP_BALANCED instead of DXIO_PSPP_POWERSAVE.
This change adds DXIO_PSPP_DISABLED as the first enum value to properly
match the FSP definition and adjusts non AMD Customer Reference Boards
that reference the enum to still send the same value even though it has
now change definitions. If we actually want DXIO_PSPP_POWERSAVE for
those boards that can be adjusted in a future change.
BUG=b:193495634
TEST=Boot to OS with Majolica and Guybrush and run 10G iperf on wifi
with other server on local network.
Change-Id: I287b6d3168697793a2ae8d8e68b4ec824f2ca5ef
Signed-off-by: Matt Papageorge <matthewpapa07@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56463
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
|
|
Add new ram_id:1000 for memory part MT40A1G16RC-062E:B.
BUG=b:193732051
TEST=Generate new spd file and build coreboot.
Then boot from the DUT with new memory MT40A1G16RC-062E:B
Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Change-Id: I07c69f628da7871b990c91af4a8244430b4d96a0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56328
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
According to stardust test tracking report to adjust
telemetry setting.
VDD Slope : 30595 -> 30400
VDD Offset: 77 -> 317
SOC Slope : 24063 -> 23789
SOC Offset: 105 -> 94
BUG=b:190338440
BRANCH=zork
TEST=emerge-zork coreboot
Signed-off-by: Kane Chen <kane_chen@pegatron.corp-partner.google.com>
Change-Id: Id997f9cd220d704c5b0882c257a596fb3d2485ef
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56077
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Sam McNally <sammc@google.com>
Reviewed-by: Daniel Kurtz <djkurtz@google.com>
|
|
Since the default state of the MMIO UART devices in the chipset
devicetree is off, the mainboard devicetree entries that disable MMIO
UART devices are removed.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I913a587802020ce4e182b48632cdde1104c2a6e6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55545
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This a mainly a preparation for adding the MMIO UART devices to the
chipset devicetree.
TEST=none
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I533e4a909fdeb1614dbc5df015440b9df5d83233
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55544
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
|
|
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I06102f4fcc3bf9de332c71a52c632241b95cde19
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55543
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
GSC is connected with AP via i2c bus so we need to enable i2c in
psp_verstage.
Signed-off-by: Kangheui Won <khwon@chromium.org>
Change-Id: I5f7b73be67a692ea7de31ae53bd111d0e4b6998c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55136
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Id2bdce5871f57e9edb17f89cba61b5c5ae018566
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55104
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
|
|
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ia6199c70163d32467abe5ba5da55c73ff62ba10f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55103
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
|
|
The chipset devicetree only has the essential PCIe devices enabled that
are needed for the SoC code to work. It also defines aliases for all
PCIe devices that can be used to reference the devices in the mainboard-
specific devicetrees and devicetree overrides. To make the change easier
to review that part will be done in a follow-up patch.
Despite missing in the PPR, device pci 18.7 exists on Picasso.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I6b7c3fd32579a23539594672593a243172c161c7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50626
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
|
|
Since the default for the corresponding UPD of the Picasso FSP is
DXIO_PSPP_POWERSAVE and the devicetree default is DXIO_PSPP_PERFORMANCE,
add a deviectree setting for each board that's using the Picasso SoC
code to not change the setting for the existing boards.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I0008ebb0c0f339ed3bdf24ab95a20aa83d5be2c9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54934
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
|
|
Add Samsung DDR4 memory part K4AAG165WB-BCWE 16Gb
index was generated by gen_part_id
BUG=b:180986354
TEST=none
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Change-Id: I94b950b51b41767676ab3ddf89e88860c42f5f1d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54250
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
|
|
modify USB OC pin setting for Shuboz/Jelboz/Jelboz360
Shuboz/Jelboz:
usb_port_overcurrent_pin[0] = "USB_OC_PIN_0" # USB C0
usb_port_overcurrent_pin[1] = "USB_OC_PIN_0" # USB A0
usb_port_overcurrent_pin[2] = "USB_OC_PIN_1" # USB A1
usb_port_overcurrent_pin[3] = "USB_OC_PIN_1" # USB C1
Jelboz360:
usb_port_overcurrent_pin[0] = "USB_OC_PIN_0" # USB C0
usb_port_overcurrent_pin[1] = "USB_OC_PIN_0" # USB A0
usb_port_overcurrent_pin[2] = "USB_OC_NONE" # NONE
usb_port_overcurrent_pin[3] = "USB_OC_PIN_1" # USB C1
BUG=b:182879559
BRANCH=zork
TEST=emerge-zork coreboot, validate the OC mapping.
Signed-off-by: Kane Chen <kane_chen@pegatron.corp-partner.google.com>
Change-Id: Icc1fa090109e6be54e2a5f49e364f5502f53aca2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51523
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
|
|
Some designs might wish to use an open drain eSPI ALERT#. This change
adds an enum that allows setting the eSPI alert mode.
BUG=b:187122344, b:186135022
TEST=Boot guybrush using all 3 alert modes
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ia35fc59a699cf9444b53aad5c9bb71aa27ce9251
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52954
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
Disable HDMI 2.0 for Vilboz and then support display resolution 4K 30Hz
BUG=b:179170193
BRANCH=firmware-zork-13434.B
TEST=verified that the resolution of the display is 4K 30Hz
Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Change-Id: Ib0dc0d584f0e87bc9c3da85a583cb8c8bed76440
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52724
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Huang <patrick.huang@amd.corp-partner.google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
|
|
The usage of external oscillator has got nothing to do with Audio
Co-processor (ACP). Hence move it out of common config and put it into
the SoC config where it is being used.
BUG=None
TEST=Build Dalboz and Vilboz mainboards.
Change-Id: I8c5d98addfba750f9ddb87a846599541b4a8340a
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52771
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
|
|
zork doesn't configure any GPIO as PAD_SMI. Since mainboard_smi_gpi will
only get called for a GEVENT that will cause a non-SCI SMI, this isn't
expected to be called. For the unexpected and very unlikely case that it
still does get called, put a printk into mainboard_smi_gpi to see what
is happening there.
TEST=none
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I14c67b21a83b334558cdd54ebf700924aa9d0808
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52359
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Audio Co-processor driver is similar for both Picasso and Cezanne SoCs.
Hence move it to the common location.
BUG=None.
TEST=Builds Dalboz, Trembyle, Vilboz, Mandolin and Bilby mainboards.
Change-Id: I91470ff68d1c183df9a2927d71b03371b535186a
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52643
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
|
|
Both touchpads supported by zork use level-triggered wakeup signal.
BRANCH=zork
BUG=b:172846122,b:182911201
TEST=1. cros build-ap -b zork
2. both Synaptics and ELAN touchpads work fine on Vilboz
3. Wakeup source is correctly reported on Vilboz
Signed-off-by: Victor Ding <victording@google.com>
Change-Id: Icc2b5ad3bd434c9759a0fdfc121aa3c94f46630e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52367
Reviewed-by: Sam McNally <sammc@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Based on the datasheet provided by ELAN, the /INT pin is "low active"
and "indicates touchpad likes to send data to system(host) when low".
The signal is level-triggered.
BRANCH=zork
BUG=b:172846122
TEST=cros build-ap -b zork
Signed-off-by: Victor Ding <victording@google.com>
Change-Id: I1f2182aaf483932304591ab14592f35214ea6efd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52366
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
platform_descriptors.h is unrelated to the contents of baseboard/gpio.h
where it was included, so move the includes to the files where it is
actually needed.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I94e59b5aac2df834d956106ac953eebfc5cf6921
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52357
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
amdblocks/gpio_defs.h provides the definitions of GEVENT_x.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I65d398667e6777de6f1fa4e027cf1c75a3e235c3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52356
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
The new discovery from Google & AMD, the value currently used
STAPM Time Constant of 1640 is reducing real PPT TSP from the
target 4.8W to 4.68W.
Furthermore, when using the "default" STAPM Time Constant of 1400,
the actual real PPT TSP becomes 4.89W.
Operating at this default settings therefore uses a higher real PPT TSP,
which results in a significant performance improvement.
BUG=b:175364713,b:184902568
BRANCH=zork
TEST=1. emerge-zork coreboot
2. run balance performance and skin temperature test => pass
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Change-Id: I9cf4d51f42fe250340bcb642db07796c9a480c34
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52312
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Sam McNally <sammc@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
The new discovery from Google & AMD, the value currently used
STAPM Time Constant of 1640 is reducing real PPT TSP from the
target 4.8W to 4.68W.
Furthermore, when using the "default" STAPM Time Constant of 1400,
the actual real PPT TSP becomes 4.89W.
Operating at this default settings therefore uses a higher real PPT TSP,
which results in a significant performance improvement.
BUG=b:184902568
BRANCH=zork
TEST=1. emerge-zork coreboot
2. run balance performance and skin temperature test => pass
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Change-Id: I102c1c5f8215a6c5f7a4451f5731167c32e27c90
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52313
Reviewed-by: Sam McNally <sammc@google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
To update the sx9324 registers after RF team fine-tuned the parameters.
BUG=b:172397658
BRANCH=firmware-zork-13434.B
TEST=build coreboot and verify the sx9324 function
Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Change-Id: Ief85bc61952144a1d7a151100d89938517078ab4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51936
Reviewed-by: Kangheui Won <khwon@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
When GPIO_2 was configured as PAD_NF with the WAKE_L function selected
the GPIO_2 override in soc_gpio_hook called soc_route_sci that wrote the
corresponding SCI mapping register, but didn't set up the SCI level and
trigger type, so that couldn't have worked on most of the boards. The
only boards where I think this was actually tested are the google/zork
ones and they configured GPIO_2 as PAD_SCI where the GPIO mux setting is
GPIO mode instead of the WAKE_L mode, but at least the SCI was
configured correctly. The new PAD_NF_SCI macro can configure both the
right GPIO mux setting and set up the SCI configuration correctly, so
use this new macro for the GPIO_2 pin. For test purposes I also added
the corresponding GPIO_2 configuration to amd/mandolin to see if the
affected registers end up having the expected value using the HDT
debugger to look at the registers, but didn't test the wake-up
functionality, since S3 resume isn't working on amd/mandolin yet.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Suggested-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Change-Id: Ic069e46b759fb6746645faccd254263c49a892d4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51756
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Update the ACPI name from AMDP1015 to 1002105 based on b/177971830#180.
AMDI1015 -> AMD platform with RT1015
10021015 -> AMD platform with RT1015p
Reference:
https://www.spinics.net/lists/alsa-devel/msg124694.html
BUG=b:177971830
BRANCH=firmware-zork-13434.B
TEST=emerge-zork coreboot chromeos-bootimage, then verify with ALC1015 AMP
Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Change-Id: Id8f378ad6f3328d7db949ecdb609a2f16acd3884
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52127
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Add Micron DDR4 memory part MT40A1G16RC-062E-B 16Gb
index was generated by gen_part_id
BUG=b:184024142
BRANCH=zork
TEST=emerge-zork coreboot
Change-Id: I890a2da38c8cd1963e9ee7c5df9410b2b2538e9f
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51947
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
|
|
Loading wifi_sar-vilboz-2.hex for vilboz LTE sku.
Loading wifi_sar-vilboz-3.hex for vilboz360 LTE sku.
BUG=b:183902165, b:176211194, b:183913210
BRANCH=firmware-zork-13434.B
TEST=Build coreboot and load the wifi sar table by fw_config
Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Change-Id: I37a40456970e3f1dc8b2eed26aa23e3d75748222
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51935
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
|
|
Use board id to switch acp_i2s_use_external_48mhz_osc enable.
BUG=b:181720406
BRANCH=firmware-zork-13434.B
TEST=emerge-zork coreboot chromeos-bootimage
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Change-Id: I085c39accd82bf72e4ebbc0394382ed4a7d4e901
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51792
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
|
|
Move the eDP phy overridden to variant for WWAN SKU.
BUG=b:171269338
BRANCH=firmware-zork-13434.B
TEST=emerge-zork coreboot chromeos-bootimage
Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Change-Id: I0400e8f78b152f260c632fba3cfa43aeca2f6776
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51938
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
Move the parts of romstage.c that populate the UPD-M data structure to
the newly created fsp_m_params.c file. Since
platform_fsp_memory_init_params_cb gets called from the FSP driver and
not directly from car_stage_entry the two code parts in romstage.c
weren't directly interacting. Since soc/romstage.h only contains the
mainboard_updm_update function prototype, rename it to soc/fsp.h. This
patch also removes a few unused includes.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I52c21f13520dbdfab37587d17b3a8a3b1a780f36
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51834
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
|
|
Original Stamp_boost parameter will cause boost time over 2500sec(3960sec)
To pass balance performance and skin temperature test, decrease stamp_boost:
2500 -> 1640
BUG=b:182753072
TEST=1. emerge-zork coreboot
2. run balance performance and skin temperature test
Change-Id: I43c104ef912aafecadf9497f9ea20c8478c0e920
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51738
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
|
|
update telemetry to improve the performance.
BUG=b:182753072
BRANCH=zork
TEST=1. emerge-zork coreboot
2. run AMD SDLE stardust test => pass
Change-Id: I6e4d0c6fcd740d82edf073fb307aa6a6b09ec78a
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51790
Reviewed-by: Sam McNally <sammc@google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Enable ALC1015 driver for audio support in vilboz
BUG=b:177971830
BRANCH=firmware-zork-13434.B
TEST=emerge-zork coreboot chromeos-bootimage, then verify with ALC1015 AMP
Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Change-Id: If0abfd6570579fe637a7bef31de2f01d58f3bdf6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51053
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
|
|
Set default USB2 HS disconnect threshold to maximum to avoid false
disconnects that eventually lock up the xHCI controller
BUG=b:174538960
TEST=suspend_stress_test -c 50 on vilboz and morphius.
Sample set of USB2 HS devices connect and disconnect
successfully
Signed-off-by: Julian Schroeder <julianmarcusschroeder@gmail.com>
Change-Id: Ic921d850a0bdd717a2a7e50e9e6f65e39e0607bf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51265
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
To append SSFC to top 32 bits of fw_config.
BUG=b:177971830
BRANCH=firmware-zork-13434.B
TEST=Build coreboot and get the value of SSFC.
Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Change-Id: Iab1596f1cc8fbbf45e6a9269351bf422a43f3583
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51655
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Not all of dalboz variants support the this amp. Thus, move out of baseboard.
BUG=b:182815488
TEST=builds
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: If708574f5fb18dd3b4f2ef978529a16a40d5dc0c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51511
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-hsuan Hsu <yuhsuan@google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
|
|
The logic behind I2C bus initialization, I2C MMIO base address getter
and setter, I2C bus ACPI name resolution are identical for all the AMD
SoCs. Hence moving all the SoC agnotic parts of the driver into the
common driver and just configure the SoC specific parts into individual
I2C drivers.
BUG=None
TEST=Build Dalboz and Grunt. Boot to OS in Dalboz. Ensure that the I2C
peripherals are detected as earlier in Dalboz. Verify some I2C
peripheral functionality like trackpad and touchscreen.
Change-Id: Ic9c99ec769d7d8ad7e1e566fdf42a5206657183d
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Suggested-by: Kyosti Malkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51509
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
According to stardust test tracking report to adjust
telemetry setting.
VDD Slope : 30518 -> 30595
VDD Offset: 435 -> 77
SOC Slope : 22965 -> 24063
SOC Offset: 165 -> 105
BUG=b:182399760
BRANCH=zork
TEST=emerge-zork coreboot
Signed-off-by: Kane Chen <kane_chen@pegatron.corp-partner.google.com>
Change-Id: Ie7e6af77bdaad6cc964ac206a69ccb854aae869f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51517
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
|
|
Currently, if `get_wifi_sar_cbfs_filename()` returns NULL, then
`get_wifi_sar_limits()` assumes that the default filename is used for
CBFS SAR file. This prevents a board from supporting different models
using the same firmware -- some which require SAR support and some
which don't.
This change updates the logic in `get_wifi_sar_limits()` to return
early if filename is not provided by the mainboard. In order to
maintain the same logic as before, current mainboards are updated to
return WIFI_SAR_CBFS_DEFAULT_FILENAME instead of NULL in default
case.
Change-Id: I68b5bdd213767a3cd81fe41ace66540acd68e26a
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51485
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This reverts commit 87a1bd696d47f80101e46132efae8cad8cfe5c7e.
Reason for revert: skin temperature is overheating due to boost time is too long
BUG=b:175364713
TEST=1. emerge-zork coreboot
2. run balance performance and skin temperature test => pass
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Change-Id: I31db06f4bcb986398e7bd2ac2858ffbedb257e2b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51391
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Daniel Kurtz <djkurtz@google.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
|
|
Define the 26th bit of the fw_config for the regular touchpad
and numpad touchpad selection.
REGULAR_TOUCHPAD: 1
NUMPAD_TOUCHPAD: 0
BUG=b:174964012
BRANCH=zork
TEST=build pass
Signed-off-by: Kane Chen <kane_chen@pegatron.corp-partner.google.com>
Change-Id: Ie2055d6bb45a64bc0e59209cecc0f8a31c0f3718
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51278
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
|
|
The VGA BIOS for AMD Padmelon and Google Zork are stored in `amd_blobs`.
Do not force inclusion of VGA BIOS when `USE_AMD_BLOBS` is not enabled.
Change-Id: I206e8fadc14ec0d9b162dc4d72813fdd3d43958b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51341
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
|
|
Add ".data_hold_time_ns" to follow I2C specification.
The adjusted result aobut 0.315us(more than 0.3us)
BUG=b:181091107
BRANCH=zork
TEST=emerge-zork coreboot chromeos-bootimage
Signed-off-by: Kane Chen <kane_chen@pegatron.corp-partner.google.com>
Change-Id: Id92fadcb54b9722709e32ced1f0be001b8c97975
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51361
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
BUG=b:182269526
TEST=builds
Signed-off-by: Mathew King <mathewk@chromium.org>
Change-Id: I351fb4fc493bb92b31e2c8bc946dfb048045335c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51384
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
|
|
To define Mainboard Type config, use the fw_config bit[26].
Check MB Type to modify SDLE settings for different VCORE IC.
BUG=b:177193131
BRANCH=zork
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Change-Id: If153c0a3e641ae32ef89737925bd9f62dfb71f3d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49683
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
|
|
Add the UPD updating hook in early stage for customization.
BUG=b:117719313
BRANCH=zork
TEST=build,check the hook function been executed.
Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Change-Id: I4954a438a51b29b086015624127e651fd06f971b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51181
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This file is common for all the AMD platforms.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I10ee600b4bcd7aaff39bfab075eb4dbc9096b435
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51299
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Update telemetry settings for vilboz.
VDD Slope : 26939 -> 27225
VDD Offset: 125 -> 187
SOC Slope : 20001 -> 26559
SOC Offset: 168 -> 89
BUG=b:177162553
BRANCH=zork
TEST=emerge-zork coreboot
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Change-Id: Iaf7c5083c4c5affec5ae0b5583efb5237e10d0ec
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51165
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: chris wang <Chris.Wang@amd.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
|
|
Loading wifi_sar-vilboz-1.hex for vilboz360 LTE sku for the present.
BUG=b:177684735, b:176168400
BRANCH=zork
TEST=emerge-zork coreboot chromeos-bootimage, then verify that tables are
in CBFS and loaded by iwlwifi driver.
Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Change-Id: I477b55d64fd9d33d753b10b2de443041a12d13e2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51171
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kangheui Won <khwon@chromium.org>
|
|
Modify I2C3 setting to follow I2C specification (lower than 400kHz).
Original setting:
.rise_time_ns = 184
.fall_time_ns = 42
Change to:
.rise_time_ns = 110
.fall_time_ns = 34
BUG=b:181091107
BRANCH=zork
TEST=emerge-zork coreboot chromeos-bootimage
Signed-off-by: Kane Chen <kane_chen@pegatron.corp-partner.google.com>
Change-Id: Ibdbb9a7dde524bdbde4789ee7ea005646080d97a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51052
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
Change-Id: Ie3870bc666acaea316f00b205de512cf790e720c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50718
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
Stamp_boost 1640 parameter is too short to keep APU performance.
Restore parameter to 2500 then APU could have longer boost time (~3xxx sec)
BUG=b:175364713
TEST=1. emerge-zork coreboot
2. run balance performance and skin temperature test => pass
Change-Id: Ie08394d0b1a693f71336cb4cb6ce9528dfdce14b
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51050
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
|
|
Let's not have 7 boards of all use a different name for
the .enable_dev function in mainboard chip_operations.
Change-Id: I07f3569e6af85f4f1635595125fe2881ab9ddd43
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50999
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
|
|
The semantics of pirq_setup() from previous platforms was to
only setup the global pointers for PIC and APIC tables, not
to create or modify the tables themselves.
Change-Id: Iaa7c31eed21432dc2b3fe6b32803bd2658fd5e2d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50717
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
|
|
Recommendation from SOC to config IQ=8 for U3 port0,
vboost for all U3 ports for passing ESD pin test.
BUG=b:173476380
BRANCH=zork
TEST=1. emerge-zork coreboot
2. run U3 SI/ESD pin test => pass
Change-Id: I0e6414f686a995536a0fd8aa0f6f70e5a36718a3
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50992
Reviewed-by: Kangheui Won <khwon@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Adjust H1 I2C CLK:
404kHz -> 391 kHz
BUG=b:179753353
BRANCH=zork
TEST=1. emerge-zork coreboot chromeos-bootimage
2. power on proto board successfully
3. measure i2c freq by scope is close to 400kHz
Change-Id: Iedd47dd6fc4f7ac7f0aac480d63ddbdf85a84ec2
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50994
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
|
|
1. GPIO_4 to NC
BUG=b:179333669
BRANCH=zork
TEST=emerge-zork coreboot
Signed-off-by: Kane Chen <kane_chen@pegatron.corp-partner.google.com>
Change-Id: I4342b2beb7fc755bee47ee4fad0023d7a6592c4b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50277
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Sometimes the USB device will be lost after DUT resume.
Adjust USB phy settings for all USB ports to fix the failed symptom.
BUG=b:174538960
BRANCH=zork
TEST=USB devices stay connected after running suspend test
Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Change-Id: I25bca968bb4a740161b36e2082d1e500ae648712
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50020
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Peichao Wang <pwang12@lenovo.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Found using:
diff <(git grep -l '#include <string.h>' -- src/) <(git grep -l 'STRINGIFY\|memcpy\|memmove\|memset\|memcmp\|memchr\|strdup\|strconcat\|strnlen\|strlen\|strchr\|strncpy\|strcpy\|strcmp\|strncmp\|strspn\|strcspn\|strstr\|strtok_r\|strtok\|atol\|strrchr\|skip_atoi\|snprintf' -- src/)|grep '<'
Change-Id: I3ba39077014c50c2dfb9fddf78813f1058c45cc1
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50685
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
|
|
Change-Id: I6e0f33172fbcecebddfccdf64c22685636a23936
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50524
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This is ACPI specific config that applies to all the AMD SoCs. Stoney
doesn't currently use this, but we can add that functionality later.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I0be7d917d7c5ba71347aa646822a883e2cf55743
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50557
Reviewed-by: Mathew King <mathewk@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
configure IRQs as level triggered to prevent TP lost.
BUG=None
BRANCH=zork
TEST=1. emerge-zork coreboot chromeos-bootimage
2. power on, suspend DUT to check TP is functional
Change-Id: I81ffa889fbdfb01bf3057a8258fb4dd4ad7e88d5
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50420
Reviewed-by: Sam McNally <sammc@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
EDGE IRQ from TS might be invalid to HOST, configure IRQs
as level triggered to prevent TS lost.
BUG=b:179594439
BRANCH=zork
TEST=1. emerge-zork coreboot chromeos-bootimage
2. power on, suspend DUT to check TS is functional
Change-Id: Ibbbc73b37932ba1359ffe6f572a15564bb341025
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50416
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Sam McNally <sammc@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Modify GPIO_140 delay time and add "disable_gpio_export_in_crs"
to meet touchscreen controller power on sequence.
BUG=b:174442484
BRANCH=master
TEST=emerge-zork coreboot chromeos-bootimage
Signed-off-by: Kane Chen <kane_chen@pegatron.corp-partner.google.com>
Change-Id: I36a7055b7be0963479f8a0f4dc49c92bc8fbdc9d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50228
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Since Jelboz support number pad,
due to one single coreboot for both Jelboz and Shuboz,
modify "overridetree.cb" setting to number pad support for Jelboz.
BUG=b:174964012
BRANCH=master
TEST=emerge-zork coreboot chromeos-bootimage
Signed-off-by: Kane Chen <kane_chen@pegatron.corp-partner.google.com>
Change-Id: Ie0219419834b34b6eac589f28d3604f5f1b65679
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49742
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
|
|
Fixes: b3c41329fd (mb/google/zork: Add Picasso based Zork mainboard and variants)
Change-Id: I68cd5ffc3117e714919bbce56e9af4c9982b3d54
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50385
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
|
|
Recommendation from SOC to config IQ=8 for U3 port0,
vboost for all U3 ports for passing ESD pin test.
BUG=b:175192931
BRANCH=zork
TEST=1. emerge-zork coreboot
2. run U3 SI/ESD pin test => pass
Change-Id: I42a94e03fb6f8230d4356d16b8e0d2164bc61e3f
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50282
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
|
|
update telemetry to improve the performance.
BUG=b:168585079
BRANCH=zork
TEST=1. emerge-zork coreboot
2. run AMD stardust test => pass
Change-Id: Ie0c941815d062d9af01858faf2121bc69f23ab44
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50283
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
|
|
Change-Id: Icb3108a281dfb3f21248a7065821b8237143be1a
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50301
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
Adjust H1 I2C CLK:
404kHz -> 391 kHz
BUG=b:178656936
BRANCH=master
TEST=1. emerge-zork coreboot chromeos-bootimage
2. power on proto board successfully
3. measure i2c freq by scope is close to 400kHz
Change-Id: I9067db9fc7a4d6aa2ce33b86ba6a611dfd5d7838
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50284
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
|
|
add UPD for RV2 USB3 phy setting adjust.
Note: it only for RV2 silicon and not available for RV/PCO.
Usb 3.1 PHY Parameters:
1. RX_EQ_DELTA_IQ_OVRD_VAL
-Override value for rx_eq_delta_iq. Range 0-0xF
2. RX_EQ_DELTA_IQ_OVRD_EN
-Enable override value for rx_eq_delta_iq. Range 0-0x1
3. Override value for rx_vref_ctrl. Range 0 - 0x1F
4. Enable override value for rx_vref_ctrl. Range 0 - 0x1
5. Override value for tx_vboost_lvl: 0 - 0x7.
6. Enable override value for tx_vboost_lvl. Range: 0 - 0x1
7. Override value for rx_vref_ctrl. Range 0 - 0x1F
8. Enable override value for rx_vref_ctrl. Range 0 - 0x1
9. Override value for tx_vboost_lvl: 0 - 0x7.
10. Enable override value for tx_vboost_lvl. Range: 0 - 0x1
BUG=b:175192931
TEST=Build/verify the valule will been apply on dirinboz
Change-Id: I1d5f69e840952cc5171af1ce8597628d1bede5cb
Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50240
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Improve performance and meet stardust test requirement.
PcdSet32(PcdTelemetry_VddcrVddfull_Scale_Current,102586)
PcdSet32(PcdTelemetry_VddcrVddOffset, 0)
PcdSet32(PcdTelemetry_VddcrSocfull_Scale_Current,24674)
PcdSet32(PcdTelemetry_VddcrSocOffset, 0)
BUG=b:176156237
BRANCH=zork
TEST=emerge-zork coreboot
Signed-off-by: Kane Chen <kane_chen@pegatron.corp-partner.google.com>
Change-Id: I81dbfafffe7625c3d0d80419466240508f9b041b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50256
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Enable this driver along with power saving.
BUG=b:177955523
BRANCH=zork
TEST=boot and see this message:
BayHub LV2: Power-saving enabled 110102
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Change-Id: Icd87ea585dfaa2185abf1f7bf803e9c9a6e63972
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49822
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
Change-Id: I0d2ab4144970184f46e1d0e7a2464e94fa38aa63
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50203
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Johnny Lin <Johnny_Lin@wiwynn.com>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
|
|
Change-Id: Idc11f1e131df2e01864fedac864bda5e11f2d17b
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50166
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
|
|
Clean up the unused UPD and re-sort the table, and also update
the new phy parameter in the soc code and overridetree.
remove:
EDpPhySel
EDpVersion
rename:
DpPhyOverride -> edp_phy_override
EDpPhySel -> edp_physel
DpVsPemphLevel -> edp_dp_vs_pemph_level
MarginDeemPh -> edp_margin_deemph
Deemph6db4 -> edp_deemph_6db_4
BoostAdj -> edp_boost_adj
eDP phy setting:
DP_VS_LEVEL0_PREEMPH_LEVEL0 = 0x00(0.4v 0db swing 0,pre-emphasis 0)
COMMON_MAR_DEEMPH_NOM = 0x004b
COMMON_SELDEEMPH60 = 0x0
CMD_BUS_GLOBAL_FOR_TX_LANE0 = 0x80
BUG=b:171269338
BRANCH=zork
TEST=Build, verify the parameter pass to picasso-fsp
Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Change-Id: I655af08e2f86398d088e30d330f49e71cf7e1275
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50212
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
Change-Id: I960870fabde1dacfe52a8a35c253b0bd097d3e10
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50183
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
|
|
Added device hid info to the MST RTD2141b device on
trembyle.
BRANCH=zork
BUG=b:147402710
TEST=Build and flash BIOS image, see 10EC2141 appears
under /sys/bus/i2c/devices
Signed-off-by: Shiyu Sun <sshiyu@chromium.org>
Change-Id: I97a67f9dbc31cd788d579252d7d355b24d97ca30
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48229
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sam McNally <sammc@google.com>
|
|
Change-Id: I4356a8bda71e84afe8c348d366479c5006bf2459
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49796
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Objects that are created with acpigen need to be declared
with External () for the generation of dsdt.asl to pass
iasl without errors.
There are some objects that are common to all platforms,
and some that should be declared only conditionally.
Having a top-level ASL helps to achieve this.
Change-Id: Ibaf1ab9941b82f99e5fa857c0c7e4b6192c74330
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49794
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: If0bc153cd3a3391b1607848436f0ab5fcd54ce7d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49907
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
set pwron_varybl_to_blon to 0x5, which means fw will delay 20ms between backlight
on and vary backlight.
BUG=b:171269338
BRANCH=zork
TEST=Build; Verify the UPD was passed to system integrated table; measure
the power on sequence on dalboz
Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Change-Id: I8af35eee7777a8e71b42f0c128795290b8c2c93e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48865
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
|
|
needs to adjust the eDP phy setting to fix the eDP noise for WWAN.
DP_VS_LEVEL0_PREEMPH_LEVEL0, = 0x00 (0.4v 0db) swing 0, pre-emphasis 0)
COMMON_MAR_DEEMPH_NOM = 0x004B
COMMON_SELDEEMPH60 = 0x0
CMD_BUS_GLOBAL_FOR_TX_LANE0 = 0x80
BUG=b:171269338
BRANCH=none
TEST=Build; Verify the UPD was passed to system integrated table
Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Change-Id: Ibe720e26d2257e05a989eaa1fd85d542005cf6a6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48734
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This conflicts with the MSTH i2c_tunnel.
BUG=b:175146875
BRANCH=zork
TEST=Boot trembyle and inspect ACPI tables.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Iac04c7dc361d427f5ebb99644aa70bd0c7dbb918
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49812
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
|
|
From AMD USB phy specialist recommended that for DB port2 (type-A), port3 (type-C C1)
the most effective corrections for the depressed eye are
tx_rise_tune=0x0
tx_pre_emp_amp_tune=0x3
tx_fsls_tune = 0x3
BUG=b:173476380
BRANCH=zork
TEST=1. emerge-zork coreboot
2. pass USB 2.0 SI eye diagram verification
Change-Id: Ib31c5d55e30b958d3e552e8d0b4a160947444636
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49826
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
From AMD USB phy specialist recommended that for DB port2 (type-A), port3 (type-C C1)
the most effective corrections for the depressed eye are:
tx_rise_tune=0x0
tx_pre_emp_amp_tune=0x3
tx_fsls_tune = 0x3
BUG=b:165209698
BRANCH=zork
TEST=1. emerge-zork coreboot
2. pass USB 2.0 SI eye diagram verification
Change-Id: I80afd6bf1257b9a72d0d7651b48d243ebaf5de2f
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49824
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Rob Barnes <robbarnes@google.com>
|
|
Change-Id: I306f8cd74af62c0cd30f445d20c47f774f122481
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49247
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
