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The PICASSO_UART Kconfig option is about using the internal MMIO UART
controllers in Picasso for console, so rename it to PICASSO_CONSOLE_UART
Change-Id: I38ac9ee96af826fe49307b4d0e055a43fcbd4334
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42429
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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Zork family does not use OEM binary and so this change drops the
configs required for adding this binary.
Change-Id: Id38c67030e4055ab16934d1a900ee1cea5843b54
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42336
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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This change enables following ELOG options for zork family:
ELOG
ELOG_BOOT_COUNT
ELOG_GSMI
ELOG_BOOT_COUNT_CMOS_OFFSET
BUG=b:158875638
TEST=Verified that kernel reports GSMI loading correctly:
[ 5.308982] gsmi version 1.0 loaded
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I4f34a814e744e863f1fbfc19e37209cb7febbdcc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42332
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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This change defines a Kconfig variable MEMLAYOUT_LD_FILE which allows
SoC/mainboard to provide a linker file for the platform. x86 already
provides a default memlayout.ld under src/arch/x86. With this new
Kconfig variable, it is possible for the SoC/mainboard code for x86 to
provide a custom linker file as well.
Makefile.inc is updated for all architectures to use this new Kconfig
variable instead of assuming memlayout.ld files under a certain
path. All non-x86 boards used memlayout.ld under mainboard
directory. However, a lot of these boards were simply including the
memlayout from SoC. So, this change also updates these mainboards and
SoCs to define the Kconfig as required.
BUG=b:155322763
TEST=Verified that abuild with --timeless option results in the same
coreboot.rom image for all boards.
Change-Id: I6a7f96643ed0519c93967ea2c3bcd881a5d6a4d6
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42292
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add DRAM support for vilboz:
Hynix H5AN8G6NCJR-VKC # 0b0000
Hynix H5ANAG6NCMR-VKC # 0b0001
Samsung K4A8G165WC-BCWE # 0b0010
Hynix H5AN8G6NDJR-XNC # 0b0011
Micron MT40A512M16TB-062E-J # 0b0100
Samsung K4AAG165WA-BCWE # 0b0101
Micron MT40A1G16KD-062E-E # 0b0110
BUG=b:157523051
BRANCH=none
TEST=build
Change-Id: I251fd9cc7bc51bfdeaa577f7034da750e684dc99
Signed-off-by: Paul Ma <magf@bitland.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42244
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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The picasso_ prefix on the fsp_pcie_descriptor and fsp_ddi_descriptor
structs isn't needed, since this code is picasso-specific, so drop it.
Change-Id: Ia6a0ddb411aa64becc3c23a876f2ea43cb68e028
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42252
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This change sets FMDFILE for zork family so that coreboot builds pick
up the right flash layout.
BUG=b:155990176
Change-Id: Ia1673622ccd14a2ff7bde555ed33d5b51cf4272a
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42106
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This reverts commit fddd101904188193197be10c8eae04e76386299b.
Reason for revert: With FSP compression and non serial FSP we now have enough space in RO.
Original change's description:
> mb/google/zork: Increase RO section to 5MB
>
> The current size is too small to fit all the depthcharge assets.
> Increasing it to 5MB gives us 648k of free space.
>
> $ cbfstool /build/zork/firmware/image-trembyle.serial.bin print -r COREBOOT
> FMAP REGION: COREBOOT
> Name Offset Type Size Comp
> cbfs master header 0x0 cbfs header 32 none
> fallback/romstage 0x80 stage 524316 none
> fallback/ramstage 0x80100 stage 96592 none
> config 0x97ac0 raw 843 none
> revision 0x97e80 raw 680 none
> spd.bin 0x98180 spd 8192 none
> etc/sdcard0 0x9a1c0 raw 8 none
> locales 0x9a200 raw 141 LZMA (166 decompressed)
> (empty) 0x9a300 null 3224 none
> fspm.bin 0x9afc0 fsp 720896 none
> (empty) 0x14b000 null 3992 none
> fsps.bin 0x14bfc0 fsp 327680 none
> pci1002,15d8,c1.rom 0x19c000 optionrom 54272 none
> pci1002,15d8,c4.rom 0x1a9480 optionrom 54272 none
> fallback/dsdt.aml 0x1b6900 raw 12727 none
> locale_hi.bin 0x1b9b00 raw 10441 LZMA (239928 decompressed)
> ...
> locale_ko.bin 0x254f80 raw 11282 LZMA (231168 decompressed)
> fallback/payload 0x257c00 simple elf 95169 none
> (empty) 0x26f000 null 245656 none
> apu/amdfw 0x2aafc0 raw 1277440 none
> (empty) 0x3e2e00 null 688472 none
> bootblock 0x48af80 bootblock 64 none
>
> BUG=b:130028876
> BRANCH=none
> TEST=Built image with depthcharge and booted.
>
> Change-Id: I9cd2902404ef68cdbd4a9484d5cb1ee9cba3efd1
> Signed-off-by: Raul E Rangel <rrangel@chromium.org>
> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2042850
> Reviewed-by: Martin Roth <martinroth@google.com>
BUG=b:130028876, b:150746858
BRANCH=none
TEST=emerge-zork coreboot-zork chromeos-bootimage and boot trembyle
localhost ~ # flashrom -p host -r /tmp/main.bin
flashrom v0.9.9 : 1e0291b4 : Apr 16 2020 06:13:41 UTC on Linux 5.4.39 (x86_64)
flashrom v0.9.9 : 1e0291b4 : Apr 16 2020 06:13:41 UTC on Linux 5.4.39 (x86_64)
Calibrating delay loop... OK.
coreboot table found at 0xcbe54000.
Reading flash... SUCCESS
localhost ~ # futility dump_fmap /tmp/main.bin | grep WP_RO -B 3
area: 22
area_offset: 0x00c00000
area_size: 0x00400000 (4194304)
area_name: WP_RO
localhost ~ # flashrom -p host --wp-range 0xc00000 0x400000 --wp-enable
flashrom v0.9.9 : 1e0291b4 : Apr 16 2020 06:13:41 UTC on Linux 5.4.39 (x86_64)
flashrom v0.9.9 : 1e0291b4 : Apr 16 2020 06:13:41 UTC on Linux 5.4.39 (x86_64)
coreboot table found at 0xcbe54000.
SUCCESS
localhost ~ # flashrom -p host --wp-status
flashrom v0.9.9 : 1e0291b4 : Apr 16 2020 06:13:41 UTC on Linux 5.4.39 (x86_64)
flashrom v0.9.9 : 1e0291b4 : Apr 16 2020 06:13:41 UTC on Linux 5.4.39 (x86_64)
coreboot table found at 0xcbe54000.
WP: status: 0x0094
WP: status.srp0: 1
WP: status.srp1: 0
WP: write protect is enabled.
WP: write protect range: start=0x00c00000, len=0x00400000
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I5df10ee8e855adfaaf4b2fac4c2c47037ec093b4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42049
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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BUG=b:157499341
BRANCH=NONE
TEST=FW_NAME="vilboz" emerge-zork coreboot
Signed-off-by: peichao.wang <peichao.wang@bitland.corp-partner.google.com>
Change-Id: I28ab3edb130fc7bf8b786141bc088166052d4868
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41801
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The default HID was removed by a1c82c5ebee. We need to explicitly
specify it.
BUG=b:154756391
TEST=No longer see ERROR: _HID required message in console
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I0083f98aea55ba262ac44b0018c9c1d2e12d9f8e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42015
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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This file is not used.
BUG=b:154756391
TEST=Build trembyle and check that peripherals still work
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I721e295546aa75c9745a4836425b6e3e0067afaf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41837
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Change-Id: I858f870db0babcb51c594570e8136436ecbb0d1d
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41823
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This is a copy of the mb/google/zork directory from the chromiumos
coreboot-zork branch. This was from commit 29308ac8606.
See https://chromium.googlesource.com/chromiumos/third_party/coreboot/+/29308ac8606/src/mainboard/google/zork
Changes:
* Minor changes to make the board build.
* Add bootblock.c.
* Modify romstage.c
* Removed the FSP_X configs from zork/Kconfig since they should be
set in picasso/Kconfig. picasso/Kconfig doesn't currently define the
binaries since they haven't been published. To get a working build
a custom config that sets FSP_X_FILE is required.
BUG=b:157140753
TEST=Build trembyle and boot to OS
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I3933fa54e3f603985a0818852a1c77d8e248484f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41581
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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