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from AMD USB phy specialist recommended that TXVREFTUNE0 shouldn't over 0xD (the maximum)
in order to have enough room to accomdate a safe disconnect threshhold in COMPDISTUNE0.
TXVREFTUNE0: 0xf -> 0xd
BUG=b:172687208
BRANCH=zork
TEST=emerge-zork coreboot
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Change-Id: Ia104454d95e5e8d6a212c97fb09d61125945eeea
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48653
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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From spec, [31:28] "HS DC Voltage Level Adjustment" is "TXVREFTUNE0".
correct rx_vref_tune -> tx_vref_tune
BUG=None
BRANCH=zork
TEST=emerge-zork coreboot
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Change-Id: I27003a952d8f8bdd8fe52af8a37010e23ee9cdfd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47735
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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As per HID over I2C Protocol Specification[1] Version 1.00 Section 7.4,
the interrupt line used by the device is required to be level triggered.
Hence, this change updates the configuration of the HID over I2C devices
to be level triggered.
References:
[1] http://download.microsoft.com/download/7/d/d/7dd44bb7-2a7a-4505-ac1c-7227d3d96d5b/hid-over-i2c-protocol-spec-v1-0.docx
BUG=b:172846122
TEST=./util/abuild/abuild
Change-Id: I75a92616f11054993ff5a5bfefce5c3f4638c07c
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47420
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Use command below to change the variable globally.
sed -i "s/\<variable\>/variable_u/g" `grep variable -rl ./ \
--exclude-dir=build --exclude-dir=crossgcc`
BUG=b:171334623
TEST=Build
Change-Id: I056a76663e84ebc940343d64178c18cb20df01a3
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46840
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Update the two load line slope settings for the SVID3 telemetry.
AGESA sends these values to the SMU, which accepts them as units
of current. Proper calibration is determined by the AMD SDLE tool
and the Stardust test.
VDD Slope: 62852 -> 62641
SOC Slope: 28022 -> 28333
BUG=b:170531252
BRANCH=zork
TEST=1. emerge-zork coreboot
2. pass AMD SDLE/Stardust test
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Change-Id: Id831907aa47be27fef2e33bb884a1118ffec14a0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46655
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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Enhance USB 2.0 SI by increasing the level of "HS DC Voltage Level"
and "Disconnect Threshold Adjustment".
COMPDISTUNE0: 0x3->0x7
TXVREFTUNE0: 0x6->0xf
BUG=b:162614573
BRANCH=zork
TEST=1. emerge-zork coreboot
2. check U2 registers are set correctly
3. test with servo v4 type-c, it's working expectedly.
4. U2 SI pass
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Change-Id: I278cc0aaddbc9fce595bf57ca69ee8abfc9f5659
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46537
Reviewed-by: Rob Barnes <robbarnes@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Correct the two load line slope settings for the SVID3 telemetry.
AGESA sends these values to the SMU, which accepts them as units
of current. Proper calibration is determined by the AMD SDLE tool
and the Stardust test.
BUG=b:168265881
BRANCH=zork
TEST=emerge-zork coreboot
Change-Id: Id6c4f1a92d7f2ad293df7b63694e9665b85f8018
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46472
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This will reduce boot time by 7ms. Some of the initial designs
don't have a pull-up resistor on the CMD line. These designs still boot
at 400 kHz despite not having the pull-up.
BUG=b:158766134
TEST=Boot on morphius with and without patch, confirm ~7ms improvement
BRANCH=zork
Signed-off-by: Rob Barnes <robbarnes@google.com>
Change-Id: I7f6efd3d5839f154f2487a07654be8e35634bbbc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45932
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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In morphius, the USB3 typeA port needs to set to gen1, and for ezkinil
all the USB3 ports should force to gen1. So set the corresponding
setting to usb3_port_force_gen1 to force USB3 to Gen1.
BUG=b:167651308
BRANCH=zork
TEST=Build, verify the USB3 speed in gen1
Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Change-Id: I10419b91fe86fe3e06de36ddfe0d1769c1031f8e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45334
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Sam McNally <sammc@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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clamshell/tablet:
Slow_ppt_limit(W) 20
Fast_ppt_limit(W) 24
Slow_ppt_time_constant 5
Stapm_time_constant 200
Sustained_power_limit(W) 12
clamshell:
Temperature limit(C') 100
tablet:
Temperature limit(C') 70
BUG=b:157943445
BRANCH=zork
TEST=1. emerge-zork coreboot
2. change mode and check "thermctl_limit" will change
Change-Id: I1eda1411766e446b673046236f7cc4015696521f
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45520
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add dptc interface in devicetree for morphius.
Set the STAPM parameters for tablet mode:
dptc_enable = 1
dptc_fast_ppt_limit = 24000
dptc_slow_ppt_limit = 20000
dptc_sustained_power_limit = 6000
BUG=b:157943445
BRANCH=zork
TEST=Build. check the setting changed.
Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Change-Id: I4dac4b7e5157ad7ad407f42a6fc6b06eefbf3291
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45153
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Fingerprint interrupt (FPMCU_INT_L) is level triggered and not edge
triggered. Also, we are using GEVENT for wake from fingerprint and
not the GPIO IRQ wake. Thus, the irq property exposed in ACPI tables
does not need to be set to indicate wake for the IRQ.
This change updates GPIO table to configure the pad as level triggered
and drops the wake attribute for irq_gpio in overridetree.
BUG=b:165612778
BRANCH=zork
TEST=Verified that fingerprint still works in S0 and to wake device
from S3.
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I9007e5b0882ac1a6770db52d651218998f6d750d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45307
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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GPIO_144 is REPORT_EN pin for the touchscreen controller where 1 means
enable operation and 0 means stop operation. Override tree exposes
this pin as stop GPIO. Thus, it needs to be configured as active low
i.e. 0 = active (stop), 1 = inactive (enable report).
Change-Id: I349123655260349b78d2f75f846da0ce1dc966fc
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44911
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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v3.6+ of reference schematics have moved to using active low polarity
for touchscreen GPIO. This change sets the default polarity in
override tree accordingly to active low. To support boards from older
builds, variant_touchscreen_update() already updates the polarity to
active high.
BUG=b:161937506
Change-Id: I370bdb27ea5d0601612d13b515113a6048018964
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44909
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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The USB OC pin mapping is similar enough to move it to the base board
and just have two overrides for trembyle, which is based on an older
version of the schematics, and one override for woomax, which doesn't
use one USB port.
BUG=b:163081097
Change-Id: I7e305d7e6f51d7ef7a4c699e3bacc6bcd699d2f2
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44269
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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This change adds support for touchscreen power control using:
* GPIO_90 for trembyle based boards
* GPIO_32 for dalboz based boards
By default, baseboard tables configure these GPIOs as PAD_GPO driven
low and override trees expose these pads as enable_gpio to be used by
ACPI power resource.
In order to support pre-v3.6 boards, override tables configure these
pads as PAD_NC and drop the enable_gpio setting from device tree based
on board version.
BUG=b:161935640, b:162747210
Change-Id: Iba5e36b65b44ea11613b4d5fc8f13ce6433f83ab
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44193
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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BUG=b:162010077
Change-Id: Iba3e3ec62cdfd818077017abd28fa754c2ae7797
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44007
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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This change does the following:
a. USI_REPORT_EN is no longer set to high in coreboot. Instead
GPIO_144 is exposed as stop_gpio in ACPI to allow OS to control this
pad as required.
b. Appropriate delays are added for power-down sequencing:
- Delay after REPORT_EN is disabled - 1ms
- Delay after RESET is asserted - 1ms
BUG=b:159501288
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: If4d12fa0d4f4e5123d8fdccdabda996dcafa4523
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43701
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Morphius uses Goodix touchscreen and not G2 touchscreen. This change
updates hid and desc properties in devicetree accordingly.
BUG=b:159501288
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I2527fa5409bb127ac225c6fb2a5f1bc24895f6cc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43700
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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GPIO_9 is associated with gevent 22. Correct all the misconfigurations
and use macros for clarity as to what bit offset is being used instead
of open coding things.
BUG=b:161205804
Change-Id: Ic4cfd62763d72d12a55f89585f24e07df6af0f4f
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43516
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This information is redundant since it's already specified in
baseboard/devicetree_trembyle.cb or baseboard/devicetree_dalboz.cb
domain 0 is still required because sconfig uses it as an identity anchor
to match devicetree and overridetree.
BUG=b:157580724
TEST=Boot zork, usb functional
Change-Id: I3c3c1c2410166b99599d7343fae3ee756f4da321
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43437
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This change adds support for pen insert/eject operations in S0 and
wake on pen eject from S3 for morphius.
BUG=b:158814699,b:158719244
Change-Id: I3530a0aa83ec69559436687205c64524b862799b
Signed-off-by: Kevin Chiu <kevin.chiu@quanta.corp-partner.google.com>
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42950
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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update telemetry to improve the performance.
BUG=b:154863613
BRANCH=master
TEST=emerge-zork coreboot
Change-Id: Ia08259e81f360259f23ea0f9c5c128c9d0961322
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42815
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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This change adds support for fingerprint device in overridetree for
the following variants:
1. berknip
2. morphius
3. trembyle
Generates the following node in SSDT1:
Scope (\_SB.FUR1)
{
Device (CRFP)
{
Name (_HID, "PRP0001") // _HID: Hardware ID
Name (_UID, Zero) // _UID: Unique ID
Name (_DDN, "Fingerprint Reader") // _DDN: DOS Device Name
Method (_STA, 0, NotSerialized) // _STA: Status
{
Return (0x0F)
}
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
UartSerialBusV2 (0x002DC6C0, DataBitsEight, StopBitsOne,
0x00, LittleEndian, ParityTypeNone, FlowControlNone,
0x0040, 0x0040, "\\_SB.FUR1",
0x00, ResourceConsumer, , Exclusive,
)
GpioInt (Level, ActiveLow, ExclusiveAndWake, PullDefault, 0x0000,
"\\_SB.GPIO", 0x00, ResourceConsumer, ,
)
{ // Pin list
0x0006
}
})
Name (_S0W, 0x04) // _S0W: S0 Device Wake State
Name (_PRW, Package (0x02) // _PRW: Power Resources for Wake
{
0x0A,
0x03
})
Name (_DSD, Package (0x02) // _DSD: Device-Specific Data
{
ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301") /* Device Properties for _DSD */,
Package (0x01)
{
Package (0x02)
{
"compatible",
"google,cros-ec-uart"
}
}
})
}
}
BUG=b:147853944
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I7ccb3633332ce3e388293872af7b22f1867c8465
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42082
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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This is a copy of the mb/google/zork directory from the chromiumos
coreboot-zork branch. This was from commit 29308ac8606.
See https://chromium.googlesource.com/chromiumos/third_party/coreboot/+/29308ac8606/src/mainboard/google/zork
Changes:
* Minor changes to make the board build.
* Add bootblock.c.
* Modify romstage.c
* Removed the FSP_X configs from zork/Kconfig since they should be
set in picasso/Kconfig. picasso/Kconfig doesn't currently define the
binaries since they haven't been published. To get a working build
a custom config that sets FSP_X_FILE is required.
BUG=b:157140753
TEST=Build trembyle and boot to OS
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I3933fa54e3f603985a0818852a1c77d8e248484f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41581
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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