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Change-Id: I960870fabde1dacfe52a8a35c253b0bd097d3e10
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50183
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
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Add a function that initializes GPIOs based on the sleep type that
the system is coming back from. This allows initialization of the
fingerprint GPIOs which need to be handled differently between wake
from S3 and boot from S5.
On initial boot, the state of the FP sensor could be either
enabled or disabled. Because of this, on boot, we power off
the sensor for >200ms, to reset its state, then power it back on.
In suspend/resume, the fingerprint sensor should remain powered
the entire time.
If fingerprint is disabled on the trembyle-based board, set the pins
to no-connect. Dalboz doesn't have fingerprint and the GPIOS are
configured differently due to the FT5 chip having fewer GPIOS than
FP5, so nothing needs to be initialized there.
There were also a couple of trivial comment clean ups regarding the
FPMCU GPIOS.
BUG=b:171837716
TEST=Boot & Check GPIO states.
BRANCH=Zork
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I16a2e621145782e0a908bb3e49478586c09a0e0a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47308
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Since google_chromeec_cbi_get_board_version and google_chromeec_cbi_get_fw_config both call cbi_get_unit32 and return 0 as success, non-zero as failure. Let's add more readability for the false condition.
BUG=None
TEST=check with empty CBI value
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Ia49ac1ee35302f8f6afe8c0eb8e13afdf36c5b2b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46566
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The gpio90 EN_PWR_TOUCHSCREEN had been set to PAD_GPO(GPIO_90, LOW), but
addtional PAD_NC(GPIO_90) cause enable fail. remove it for issue fixed.
BRANCH=zork
BUG=b:168580357
TEST=Check Touchscreen function work
Signed-off-by: Lucas Chen <lucas.chen@quanta.corp-partner.google.com>
Change-Id: Id94dd63ba51759cebaf17779a5e659dbe0f1807f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45415
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Make GPIO_4 and GPIO_5 PAD_NC in ezkinil/gpio.c. None of the Ezkinil SKUs
use internal stylus and hence pen pads are configured as NC.
BUG=b:164892883, b:165342107
TEST=Verified taht pen detect GPIO does not cause spurious wakes.
BRANCH=None
Signed-off-by: Josie Nordrum <josienordrum@google.com>
Change-Id: I7557575cf8b8e0f849e05bda1d69acf61e91a157
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44629
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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GPIO_89 was marked as EN_DEV_BEEP_L in pre-v3.6 schematics, but it was
never really used on any of the zork variants. Starting with v3.6,
GPIO_89 is left unused in schematics.
This change configures GPIO_89 as PAD_NC in baseboard GPIO
table. Since EN_DEV_BEEP_L still needs to be driven high to allow
speakers to work, GPIO_89 is configured as PAD_GPO driven high on
pre-v3.6 schematics.
BUG=b:62108046
Change-Id: I026cd6cb598667ce6e115c3ec9357a6a56051d39
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44190
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This change adds support for touchscreen power control using:
* GPIO_90 for trembyle based boards
* GPIO_32 for dalboz based boards
By default, baseboard tables configure these GPIOs as PAD_GPO driven
low and override trees expose these pads as enable_gpio to be used by
ACPI power resource.
In order to support pre-v3.6 boards, override tables configure these
pads as PAD_NC and drop the enable_gpio setting from device tree based
on board version.
BUG=b:161935640, b:162747210
Change-Id: Iba5e36b65b44ea11613b4d5fc8f13ce6433f83ab
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44193
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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v3.6 of reference schematics have switched the polarity of reset
signal to touchscreen controller from active high to active low. This
change updates the default configuration in baseboard gpio tables to
set the reset GPIO to output low and override tables in variants to set the
reset GPIO to output high. Additionally, devicetree by default exposes
ACTIVE_LOW configuration for reset GPIO. In order to support pre-v3.6
boards, reset GPIO is updated to ACTIVE_HIGH based on board version.
BUG=b:161937506
Change-Id: I092f274d8eb1920a1cd6d3eccbe8f26b0b28928a
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44192
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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This change configures all missing pads in ramstage for trembyle
reference. This ensures that the state of all pads is set correctly
for the payload/OS. Also, all the pads for the platform are configured
in baseboard gpio table in ramstage to ensure that variants can
override any pads if required.
BUG=b:154351731
Change-Id: Idd827b6a4f995546493596f22249f8699bdf526b
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43697
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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This change drops the pulls configured on override GPIOs as they
already have external pull-ups. Also, pads which are unused are
configured as PAD_NC.
BUG=b:154351731
Change-Id: I8da5d51af25bbe2694c21ecb0868c9cc387243cb
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43562
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Board version 3 for Ezkinil follows Trembyle reference v3.51
schematics and hence GPIO_86 does not need a variant specific override.
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I7e04baad976f94d0d94e7196f0408c3c3237b2da
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42940
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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This change updates the baseboard GPIO table in ramstage to match v3
version of trembyle reference schematics. All variants using this
reference are accordingly updated to configure the GPIOs that changed
as part of v3 schematics.
BUG=b:157088093, b:154676993, b:157098434
TEST=Compiles
Signed-off-by: Martin Roth <martinroth@chromium.org>
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: Ib1d6ee2e995c1fca229c20ea63da9a45fb89f64a
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2251393
Reviewed-by: Aaron Durbin <adurbin@google.com>
Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42724
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This is a copy of the mb/google/zork directory from the chromiumos
coreboot-zork branch. This was from commit 29308ac8606.
See https://chromium.googlesource.com/chromiumos/third_party/coreboot/+/29308ac8606/src/mainboard/google/zork
Changes:
* Minor changes to make the board build.
* Add bootblock.c.
* Modify romstage.c
* Removed the FSP_X configs from zork/Kconfig since they should be
set in picasso/Kconfig. picasso/Kconfig doesn't currently define the
binaries since they haven't been published. To get a working build
a custom config that sets FSP_X_FILE is required.
BUG=b:157140753
TEST=Build trembyle and boot to OS
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I3933fa54e3f603985a0818852a1c77d8e248484f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41581
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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