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2020-10-19volteer+vendorcode: Retrieve Cr50 version only via SPIJes Klinke
No recent Chromebooks have used I2C for TPM communication, and as a result, a bug has crept in. The ability to extract Cr50 firmware string is only supported via SPI, yet code in mainboard and vendorcode attempt to do so unconditionally. This CL makes it such that the code also compiles for future designs using I2C. (Whether we want to enhance the I2C protocol to be able to provide the version string, and then implement the support is a separate question.) This effort is prompted by the desire to use reworked Volteer EVT devices for validating the new Ti50/Dauntless TPM. Dauntless will primarily be using I2C in upcoming designs. BRANCH=volteer TEST=util/abuild/abuild -t GOOGLE_VOLTEER -c max -x Change-Id: Ida1d732e486b19bdff6d95062a3ac1a7c4b58b45 Signed-off-by: jbk@chromium.org Reviewed-on: https://review.coreboot.org/c/coreboot/+/46436 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Caveh Jalali <caveh@chromium.org>
2020-10-19mb/google/volteer: Enable USB4 retimer driverDuncan Laurie
Enable the USB4 retimer driver with GPP_H10 as the power control. Change-Id: I166bc477f94c159bb411620a6bf77b5d1f194fb2 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44919 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2020-10-19mb/google/volteer/elemi: Add memory.c for DDR4Wisley Chen
Add new memory.c to support DDR4 memory types. BUG=b:170604353 TEST=emerge-volteer coreboot chromeos-bootimage Change-Id: If96b0bda0ce95766f0957c37aa7cbecefc9c03e0 Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46378 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2020-10-14mb/google/volteer: Disable HybridStorageMode for volteer baseboardShaunak Saha
HybridStorageMode FSP UPD needs to be set only for optane storage. Enabling HybridStorageMode causes some extra delay in FspSiliconInit due to HECI command and hence is avoided for NVMe and SATA scenerios. This change disables "HybridStorageMode" for volteer baseboard. For boards using optane HybridStorage needs to be enabled from overwrite devicetree. We are enabling HybridStorage for volteer and volteer2 as those plaforms have SKU's with optane storage. BUG=b:158573805 TEST=Build and boot non optane device and confirm that FspSiliconInit time is reduced. This saves ~100ms. Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Change-Id: I54fc78e3f888d4f2a02ba0ad6b9aef33eb872a9c Reviewed-on: https://review.coreboot.org/c/coreboot/+/45643 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-10-13{src/mb,util/autoport}: Use macro for DSDT revisionElyes HAOUAS
Change-Id: I5a5f4e7067948c5cc7a715a08f7a5a3e9b391191 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45904 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2020-10-13volteer: Create elemi variantWisley Chen
Create the elemi variant of the volteer reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.2.0). BUG=b:170604353 BRANCH=None TEST=util/abuild/abuild -p none -t google/volteer -x -a make sure the build includes GOOGLE_ELEMI Change-Id: I6013b6d8b28610a79f5ec49d373b2897799bffef Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46294 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2020-10-13mb, soc/intel: Switch to using drivers/wifi/generic for Intel WiFi devicesFurquan Shaikh
This change switches all mainboard devices to use drivers/wifi/generic instead of drivers/intel/wifi chip driver for Intel WiFi devices. There is no need for two separate chip drivers in coreboot to handle Intel and non-Intel WiFi devices since the differences can be handled at runtime using the PCI vendor ID. This also allows mainboard to easily multi-source WiFi chips and still use the same firmware image without having to distinguish between the chip drivers. BUG=b:169802515 BRANCH=zork Change-Id: Ieac603a970cb2c9bf835021d1fb0fd07fd535280 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46035 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-10-12mb/google/volteer/var/voxel: disable DdiPortHpdSheng-Liang Pan
GPP_A19 and GPP_A20 set no connection, disables DdiPort1Hpd and DdiPort2Hpd BUG=b:169690329 TEST=build and verify type-c(C0/C1) port functional normally Signed-off-by: Pan Sheng-Liang <sheng-liang.pan@quanta.corp-partner.google.com> Change-Id: I4405526ae777332d3c72041db7b4eda25ae31b8e Reviewed-on: https://review.coreboot.org/c/coreboot/+/46069 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: TH Lin <t.h_lin@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-12mb/google/volteer: Fix typo in baseboard power limits Sumeet R Pawnikar
Fix typo for power limit values under comment section in baseboard BUG=None BRANCH=None TEST=Build for volteer system Change-Id: I879b9587e863360bf4efda4099d96b42b904377e Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46220 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-10-12mb/google/volteer/variants/eldrid: Add SPD for H5ANAG6NCJR-XNCNick Vaccaro
Add SPD support for DDR4 memory part H5ANAG6NCJR-XNC. Eldrid should use DRAM_ID strap ID 4 (0100) on SKUs populated with H5ANAG6NCJR-XNC DDR4 memory parts. BUG=b:161772961 TEST="FW_NAME=eldrid emerge-volteer coreboot" and verify it builds successfully. Change-Id: Ia26315479ce1a749a0f7c9e81f134f7068d7eb0b Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45963 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-10mb/google/volteer: Use device aliasesDuncan Laurie
Use the device aliases provided by tigerlake chipset.cb instead of the raw pci device+function. Take advantage of the default states in chipset.cb and only list the devices that are enabled for all volteer variants. Change-Id: I5620004afd7fa4d50389f32dd79148960a2b2662 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44039 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-09mb/google/volteer/variants/volteer2: Update DPTF parametersTerry Chen
1. Apply the DPTF parameters received from the thermal team. BUG=b:169183507 TEST=build and verify by thermal tool Signed-off-by: Terry Chen <terry_chen@wistron.corp-partner.google.com> Change-Id: I1a1a0f9e86e519ac15904fac80cf3c2299213e52 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46087 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-10-08mb/google/volteer: disable TBT if no USB4 hardware availableNick Vaccaro
Implement mainboard_silicon_init_params() to allow for disabling of TBT root ports if the device does not have usb4 hardware. Add code to mainboard_memory_init_params() to disable memory-related settings associated with TBT in cases where no usb4 is available. BUG=b:167983038 TEST=none Change-Id: Iab23c07e15f754ca807f128b9edad7fdc9a44b9d Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45946 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2020-10-05mb/google/hatch,dedede,volteer: enable CHROMEOS_DRAM_PART_NUMBER_IN_CBINick Vaccaro
Enable CHROMEOS_DRAM_PART_NUMBER_IN_CBI on hatch, dedede, and volteer to use the common version of mainboard_get_dram_part_num(). Remove duplicate instances of mainboard_get_dram_part_num(). BUG=b:169789558, b:168724473 TEST="emerge-volteer coreboot && emerge-hatch coreboot && emerge-dedede coreboot" and verify it builds. Change-Id: I4e29d3e7ef0f3370eab9a6996a5c4a21a636b40e Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45883 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-05mb, soc: change mainboard_get_dram_part_num() prototypeNick Vaccaro
Change mainboard_get_dram_part_num() to return a constant character pointer to a null-terminated C string and to take no input parameters. This also addresses the issue that different SOCs and motherboards were using different definitions for mainboard_get_dram_part_num by consolidating to a single definition. BUG=b:169774661, b:168724473 TEST="emerge-volteer coreboot && emerge-dedede coreboot && emerge-hatch coreboot" and verify build completes successfully. Change-Id: Ie7664eab65a2b9e25b7853bf68baf2525b040487 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45873 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-05soc/intel/common/block/acpi: Factor out common platform.aslSubrata Banik
This patch moves platform.asl into common block acpi directory to avoid duplicating the same ASL code block across SoC directory. TEST=Able to build and boot TGL, CNL and CML platform. 1) Dump and disassemble DSDT, verify _PIC method present inside common platform.asl is still there. 2) Verify no ACPI error seen while running 'dmesg` from console. Signed-off-by: Subrata Banik <subrata.banik@intel.com> Change-Id: I5189b03d6abfaec39882d28b40a9bfa002128be3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45982 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-10-05mb/{google,intel}/{volteer,tglrvp}: Refer to common IPU ASLSubrata Banik
Delete SoC local copy of ipu.asl and refer from common block ipu.asl TEST=Dump and disassemble DSDT on tglrvp, verify IPU0 device present there. Signed-off-by: Subrata Banik <subrata.banik@intel.com> Change-Id: I6a0f8a919092f7bbcd64d4791746d30fdee33894 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45978 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-09-30mb/google/volteer: Update SLP_Sx assertion widths and PwrCycDurJamie Ryu
This patch updates the SLP_Sx assertion widths and power cycle duration for volteer. Power cycle duration: With default value, S0->S5 -> [ ~4.2 seconds delay ] -> S5->S0 With value set to 1, S0->S5 -> [ ~1.2 seconds delay ] -> S5->S0 BUG=b:159108661 TEST=Verified that the power cycle duration is 1~2s with a global reset on volteer. Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Change-Id: Idf4e0c3a60b4ac59e31df1357f2ff28f195ff17f Reviewed-on: https://review.coreboot.org/c/coreboot/+/44559 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: V Sowmya <v.sowmya@intel.com>
2020-09-29mb/google/volteer: Change default camera power GPIO to 0Daniel Kang
The default GPIO values for camera power were set as 1 so the LED was turned on by default when the board is powered on. This status is kept until the camera is probed then being turned off. So the LED is turned on for a few seconds during the boot up. By setting the default power to 0, the LED is lit only when camera is turned on for probing and this should be just a blink. BUG=b:167635396 BRANCH=none TEST=Build and boot volteer board. Monitor camera privacy LED and check it is not lit more than 0.5 seconds. Signed-off-by: Daniel Kang <daniel.h.kang@intel.com> Change-Id: Ic7df391aa512daafe6e1ce49e9222b90e17ad806 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45058 Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-29mb/google/volteer/halvor: Update settings for audio functionFrank Wu
Configure overridetree settings for audio function. BUG=b:153680359, b:163382106 TEST=FW_NAME=halvor emerge-volteer coreboot chromeos-bootimage Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Change-Id: I107f6fc21b99d80d69931139dc50e7d5873a8e52 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44409 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2020-09-29mb/google/volteer: Add "i2c-allow-low-power-probe" property forDaniel Kang
cameras There is a patch https://lkml.org/lkml/2020/9/3/235 which allows i2c device can support driver probe without power up the device. In order to support this, need add coreboot add "i2c-allow-low-power-probe" property. BUG=b:169058784 BRANCH=none TEST=Build and boot volteer board. Monitor camera privacy LED and check it blinks. It should not blink. Signed-off-by: Daniel Kang <daniel.h.kang@intel.com> Change-Id: I46f90ff8d412b18c7ee4bd7f22f9a7db771eb84f Reviewed-on: https://review.coreboot.org/c/coreboot/+/45160 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2020-09-28mb/volteer: Use Genesys Logic GL9755 for Delbin, Volteer2Ravi Sarawadi
Enable newly added PCIe Gen2 to SD 4.0 card reader controller GL9755 for Delbin and Volteer2. BUG=b:166141961 TEST=Boot to kernel on Delbin, Volteer2 boards. Check PC10 in IDON. Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Change-Id: I2589ab2334625ec0d20dbdd5f3a31d98235aad2d Reviewed-on: https://review.coreboot.org/c/coreboot/+/45708 Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-28mb/google/volteer/variants/eldrid: Configure GPP_S4 and GPP_S5nick_xr_chen
GPP_S4 and GPP_S5 use as DMIC pins that need to be defined as NF2 BUG=b:168564129 Signed-off-by: nick_xr_chen <nick_xr_chen@wistron.corp-partner.google.com> Change-Id: Ia1fca960ac85f253882f0aa68b370eed49ac67b7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45689 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com> Reviewed-by: Ravishankar Sarawadi <ravishankar.sarawadi@intel.com>
2020-09-28mb/google/volteer/var/terrador: Enable audio SMBIOS OEM stringKevin Cheng
It needs to use probe statement in overridetree.cb to enable the cache of fw_config field implemented by cb:44782 and cb:44783. BUG=b:161963281 TEST= dmidecode -t 11 shows correct audio fw_config. Handle 0x0009, DMI type 11, 5 bytes OEM Strings String 1: DB_USB-USB4_GEN2 String 2: AUDIO-MAX98373_ALC5682I_I2S_UP4 Signed-off-by: Kevin Cheng <kevin.cheng@intel.com> Change-Id: I68c19b67d945aaca3e9ebec87eb27a4b07e1a49e Reviewed-on: https://review.coreboot.org/c/coreboot/+/45673 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com> Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-09-28mb/google/volteer: Improve Eldrid Port 1 USB2 Eye Diagramnick_xr_chen
In order to pass DB type-C USB2 eye diagram, DB USB2 PHY register needs to be overridden. port#1 PortUsb20Enable=1 Usb2PhyPetxiset=7 Usb2PhyTxiset=7 Usb2PhyPredeemp=3 Usb2PhyPehalfbit=0 BUG=b:169105751 Signed-off-by: nick_xr_chen <nick_xr_chen@wistron.corp-partner.google.com> Change-Id: If076c644783fa2992ac062d6469f9c49e6d5ff24 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45598 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-09-25mb/google/volteer: Wake on AC connect and disconnectAbe Levkoy
Add AC connect and disconnect to S0ix lazy wake sources. BUG=b:161466940 BRANCH=master TEST=Connect and disconnect charger in S0ix; observe wake Change-Id: I30046a379ff75c33b991e355cc8d142241ee8b2e Signed-off-by: Abe Levkoy <alevkoy@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45669 Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-25volteer: Create boldar variantRonak Kanabar
Create the boldar variant of the volteer reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.2.0). Add "memory/Makefile.inc" generated by gen_part_id.go BUG=b:162202257 BRANCH=None TEST=util/abuild/abuild -p none -t google/volteer -x -a make sure the build includes GOOGLE_BOLDAR Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Change-Id: I92b4b917448d8e5e9176cb983adf7b209956d2c2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45648 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2020-09-24mb/google/volteer: Enable CnviBtAudioOffloadJohn Zhao
This change enables CnviBtAudioOffload. FSP is invoked to configure BT over USB and BT I2S pins for cAVS connection. BUG=b:169045123 TEST=Verifed CnviBtCore and CnviBtAudioOffload settings and FSP configuration. Booted up to kernel on Volteer. Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: I1780da0824d145a79743d5cffdea4821236d4f74 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45586 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Naveen M <naveen.m@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-09-24mb/google/volteer/var/voxel: Update gpio settings for EVTSheng-Liang Pan
Based on EVT schematic and gpio table of voxel, update gpio settings for voxel EVT. BUG=b:156841729 TEST=FW_NAME=voxel emerge-volteer coreboot chromeos-bootimage Signed-off-by: Pan Sheng-Liang <sheng-liang.pan@quanta.corp-partner.google.com> Change-Id: Idf88d83ad6d873283eb1eb8a45459ae3e74df124 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45173 Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-23treewide: rename GENERIC_SPD_BIN to HAVE_SPD_BIN_IN_CBFSMichael Niewöhner
The name GENERIC_SPD_BIN doesn't reflect anymore what that config is used for, so rename it to HAVE_SPD_BIN_IN_CBFS. Change-Id: I4004c48da205949e05101039abd4cf32666787df Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45147 Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-22mb/google: Drop unneeded empty linesElyes HAOUAS
Change-Id: I4151d1a6ce94763432f307fbc8bc4afe229856ea Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44616 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-09-21volteer: set GSPI CS to deasserted by defaultCaveh Jalali
This sets the state of GSPI chip select to 1 (deasserted) as applied by the FSP during the silicon init phase. GSPI 0 and 1 are set to CS mode manual in the SerialIoGSpiCsMode section which means we need to explicitly configure CS to deasserted in the SerialIoGSpiCsState section. GSPI0 is the CR50 and GSPI1 is the fingerprint sensor. We were running into problems where the normal expected CS toggle sequence to wake up CR50 did not work because CS was already asserted when it was expected to be deasserted, leading to TPM timeouts. BUG=b:168090038 TEST=booted on volteer, no more "TPM flow control failure" messages; verified fingerprint enrollment still works. Change-Id: I47aa5db429d75e66095d58a1eb77963dcfc3b9f3 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45384 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-21mb/google/volteer: Add firmware configuration for MAX98373_ALC5682I_I2S_UP4Frank Wu
Add MAX98373_ALC5682I_I2S_UP4 firmware configuration option and configure GPIOs properly for UP4 design. The design is also for Halvor. BUG=b:153680359, b:163382106 TEST=FW_NAME=halvor emerge-volteer coreboot chromeos-bootimage, fw_config value in Halvor: > AUDIO=MAX98373_ALC5682I_I2S_UP4 ectool cbi set 6 0x00000400 4 2 Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Change-Id: Ie25f278dfbdc2f41a36b70403699a2e3c2234600 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44560 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-09-21mb/google/volteer: fw_config: Add fields for keyboard featuresDuncan Laurie
Add newly defined fields for presence of keyboard backlight and number pad to the firmware configuration table. We don't have a need to use these in coreboot (yet) but this keeps the bit definitions in sync. BUG=b:166707536 TEST=abuild -t google/volteer Change-Id: I066e445f7d0be056e45737d2c538be1850ae85aa Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45346 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-09-18mb/google/volteer: Remove redundant GPIO decls in EldridTim Wawrzynczak
GPP_A19 and GPP_A20 are already declared as NC in the baseboard. Change-Id: I02f5751a70b51a197320b865d18da3a4ffeb87f7 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45485 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-18mb/google/volteer/eldrid: Add option to enable WiFi SAR configsMalik_Hsu
This change adds a user selectable option to enable all WiFi SAR configs that apply to volteer BUG=b:168169690 TEST=1. cros-workon-volteer start coreboot-private-files-baseboard-volteer 2. USE="project_eldrid" emerge-volteer chromeos-config coreboot-private-files-baseboard-volteer 3. check wifi_sar-eldrid.hex in coreboot-private/3rdparty/blobs/baseboard-volteer Change-Id: I6b74cd2b34ebb99cc59d456e28fd7ab2399d71d0 Signed-off-by: Malik_Hsu <malik_hsu@wistron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45233 Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-17mb/volteer: Select USE_CAR_NEM_ENHANCED_V2 for Tigerlake QS basedShreesh Chhabbi
platforms BUG=b:145958015 TEST= Build Volteer coreboot and boot on Volteer Proto 2 and Delbin. Cq-Depend:chrome-internal-review:3249528 Change-Id: I0ff896424ab23dba43075c44eb9b2c2c480ccbfb Signed-off-by: Shreesh Chhabbi <shreesh.chhabbi@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45456 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2020-09-17mb/google/volteer/variants/eldrid: Configure DP_HPD as PAD_NCnick_xr_chen
GPP_A19(DP_HPD1) and GPP_A20(DP_HPD2) were configured native function (NF1) without internal pull-down which wrongly presents HPD interrupts. This change configures GPP_A19 and GPP_A20 to be no connection and disables DdiPort1Hpd and DdiPort2Hpd. BUG=b:165893624, b:168090618 Signed-off-by: nick_xr_chen <nick_xr_chen@wistron.corp-partner.google.com> Change-Id: I31b25be1c9248debf855435c7b688b358e2cd57e Reviewed-on: https://review.coreboot.org/c/coreboot/+/45246 Reviewed-by: Scott Chao <scott_chao@wistron.corp-partner.google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-14mb/google/delbin: Configure DP_HPD as PAD_NC and disable DdiPortHpdRavi Sarawadi
GPP_A19(DP_HPD1) and GPP_A20(DP_HPD2) were configured native function (NF1) without internal pull-down which wrongly presents HPD interrupts. DP_HPD had been removed for EVT design as those events are through eSPI. This change configures GPP_A19 and GPP_A20 to be no connection and disables DdiPort1Hpd and DdiPort2Hpd. BUG=b:162566436 TEST=Booted to kernel and verified no kernel HPD pins assertion message on Delbin board. Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Change-Id: Ifdef8ee438276678258b75d2fb70c6dfc7ee0a33 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45031 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Caveh Jalali <caveh@chromium.org>
2020-09-14mb/google/volteer: Fix GPP_E12 definitionCaveh Jalali
GPP_E12 should not be defined in the baseboard as its use is determined by the variant. For legacy reasons, we still have GPP_E12 defined in early_gpio but should not. Malefor and volteer* have the same GPP_E12 definition, but that is a misconfiguration. I think that was a copy-paste that slipped through the reviews. BUG=b:157597158 TEST=volteer2 boots to the OS Change-Id: Ic3ef864827aa94b0b96e335565119f3d5d008837 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45197 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2020-09-14mb/google/volteer/var/voxel: Update DPTF parameters and TCC offsetDavid Wu
1. Set tcc offset to 5 degree celsius 2. Apply the DPTF parameters received from the thermal team. BUG=b:167523658 TEST=build and verify by thermal team Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I01a6fc5bd959798c8dd423df3907c69c883733e8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45111 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-09-14mb/google/volteer: Refactor baseboard devicetreeTim Wawrzynczak
Clean up the DPTF section of the baseboard devicetree; this makes overrides simpler, as not necessarily all of the fields need to be overridden. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Iad46fd02f7602c9419d7c3674b0d2b6f5add9a93 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45179 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-09-14mb/google/volteer: Add error handlingJohn Zhao
Coverity detects missing error handling after calling function tlcl_lib_init. This change checks the function tlcl_lib_init return value and handles error properly. Found-by: Coverity CID 1432491 TEST=None Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: Ife38b1450451cb25e5479760d640375db153e499 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45176 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-09-14mb/google/volteer: Enable EC software syncDavid Wu
Enable EC software sync for terrador and todor BUG=None TEST=emerge-volteer coreboot chromeos-bootimage Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I8c463eadd19d99dc04923f7400560cf7ba4b8101 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45186 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2020-09-11mb/google/volteer/variants/volteer2: route GPP_F14 via APICAlex Levin
GPP_F14 should be configured to be routed via APIC and not SCI. BUG=b:162528549 TEST=verified on a volteer2 Signed-off-by: Alex Levin <levinale@google.com> Change-Id: I7f2c7af230dd75b3cb3806e2b186725d49da9e68 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45279 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-09mb/google/volteer/var/trondo: Add memory parts and generate DRAM IDsDavid Wu
Add memory parts and generate DRAM IDs for trondo. BUG=None TEST=FW_NAME=trondo emerge-volteer coreboot chromeos-bootimage Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I2e89ecaf73a30595ed48ac9ce94ccbd4bb7ed3c2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45164 Reviewed-by: Michael Niewöhner Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-09mb/google/volteer/variants/eldrid: add memory.c for ddr4 supportnick_xr_chen
Add new memory.c to support DDR4 memory types. Use the new meminit_ddr() and variant_memory_sku() for eldrid variant code on memory.c The initial settings override the baseboard from volteer and fine tune gpio.c and overridetree.cb on eldrid's configuration. BUG=b:161772961 TEST='emerge-volteer coreboot chromeos-bootimage' and verify that Eldrid can boots. NOTE that tests the ddr4 side of the implementation. Change-Id: I2c7b30093a8d85bac5aba5b83768af5eb36c4f70 Signed-off-by: Nick Chen <nick_xr_chen@wistron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44632 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Caveh Jalali <caveh@chromium.org>
2020-09-08mb/google/volteer: config QS silicon devices for CSE LITEMark Hsieh
Configure eldrid to use CSE Lite. BUG=b:158140797 TEST=cd to volteer's asset_generation folder, execute "./gen_all_variant_images.sh" and verify that all variant images are produced. Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com> Change-Id: I357abdac4102f358d3aa1cb50f600312039ef140 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45018 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Caveh Jalali <caveh@chromium.org>
2020-09-08mainboard/google/volteer: Disable S0i3.4 if cr50 firmware is too oldJes Klinke
For Volteer (and future Tiger Lake boards) we can enable mode S0i3.4 only if we know that the Cr50 is generating 100us interrupt pulses. We have to do so, because the SoC is not guaranteed to detect pulses shorter than 100us in S0i3.4 substate. A new Kconfig setting CR50_USE_LONG_INTERRUPT_PULSES controls new code running in verstage, which will program a new Cr50 register, provided that Cr50 firmware is new enough to support the register. This CL adds code to detect the case when Cr50 is unable to generate longer pulses, and in that case explicitly disable the S0i3.4 substate as well as setting gpio_pm_override to all zeroes. This will increase power usage slightly, but guarantee that the GPIO block in the SoC does not switch to a slower sampling clock. In practice, this case will only be encountered in the factory, before the Cr50 chip is updated to a new RW image. (Prior to this change, the gpio_pm_override was hardcoded to zero for Volteer, but the S0i3.4 substate was not disabled. According to my conversations with Intel engineers, that was not enough to guarantee detection pulses shorter than 100us. But it is entirely possible that we have just been "lucky" that the SoC has not gone into low power mode during the boot process, where most of the cr50 communication happens.) TEST=util/abuild/abuild -t GOOGLE_VOLTEER -c max -x BUG=b:154333137 Change-Id: Idef1fffd410a345678da4b3c8aea46ac74a01470 Signed-off-by: Jes Bodi Klinke <jbk@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44359 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-09-06mb: remove duplicated Make code for spd.bin generationMichael Niewöhner
Drop duplicated code for spd.bin generation that is provided globally in lib/Makefile.inc. For all affected boards it has been verified that the output binary functionally matches the original one. The changed execution order of Make instructions influenced the cbfs file order. Hence, the rom images can't be compared directly. Thus, the output files of the two timeless abuild runs have been compared. Further, it was verified that the final files in cbfs stay identical, by comparing the extracted cbfs of each board. The boards (possibly) needing modification could be found with something like this (with false positives, though): find src/mainboard -name Makefile.inc | \ xargs egrep 'SPD_BIN|SPD_DEPS' | cut -d: -f1 | sort -u Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Change-Id: Icd3ac0fd6c901228554115c6350d88bb49874587 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44774 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-09-06mb/*: devicetree: drop now unneeded USBx_PORT_EMPTYMichael Niewöhner
Setting USBx_PORT_EMPTY is not a requirement anymore, since unset devicetree settings default to 0 and the OC pin now only gets set when the USB port is enabled (see CB:45112). Thus, drop the setting from all devicetrees. Change-Id: I899349c49fa7de1c1acdca24994ebe65c01d80c6 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45125 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2020-09-04mb/google/volteer/variant/lindar: Update memory settingsRasheed Hsueh
Based on the Lindar's schematic, generate memory settings. util: rename lp4x spds to include "lp4x-" in name BUG=b:161089195 TEST=FW_NAME=lindar emerge-volteer coreboot chromeos-bootimage Signed-off-by: Rasheed Hsueh <rasheed.hsueh@lcfc.corp-partner.google.com> Change-Id: I1ec35d62f8ed21356329b78a614114edad78c2bc Reviewed-on: https://review.coreboot.org/c/coreboot/+/45064 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Michael Niewöhner
2020-09-03mb/google/volteer/variants/volteer: route GPP_F14 via APICAlex Levin
GPP_F14 should be configured to be routed via APIC and not SCI. BUG=b:162528549 TEST=verified on a volteer Change-Id: Ie262ceeaea1c07bcc99e1545f5eb99e0d0dee905 Signed-off-by: Alex Levin <levinale@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44948 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-02Revert "mb/google/volteer/variant/lindar: Update memory settings."Patrick Georgi
This reverts commit 2ad859988b5243411393fdf3116eea281b92b1bb. Reason for revert: broke the build Change-Id: I7e7d917c2e8b698d5c7c3ce0b6d34e80696185f3 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44993 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-02mb/google/volteer/variant/lindar: Update memory settings.rasheed.hsueh
Based on the Lindar's schematic, generate memory settings. BUG=b:161089195 TEST=FW_NAME=lindar emerge-volteer coreboot chromeos-bootimage Signed-off-by: rasheed.hsueh <rasheed.hsueh@lcfc.corp-partner.google.com> Change-Id: I75fb9254ec7aa40acc2e125f0c4fd31003d28be6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44848 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Caveh Jalali <caveh@chromium.org>
2020-08-31mb/google/volteer: Add probed fw_configs to SMBIOS OEM stringsTim Wawrzynczak
Some Linux kernel drivers bind to "DMI quirks." In this case, the audio fw_config is added as an OEM string, e.g., "AUDIO-MAX98357_ALC5682I_I2S" so the audio topology can be correctly discovered. But add all successfully probed fw_config items as well, because this makes it easier to view what is selected from userspace. BUG=b:161963281 TEST=With CBI FW_CONFIG field set to 0x201: localhost ~ # dmidecode -t 11 # dmidecode 3.2 Getting SMBIOS data from sysfs. SMBIOS 3.0 present. Handle 0x0009, DMI type 11, 5 bytes OEM Strings String 1: DB_USB-USB4_GEN2 String 2: AUDIO-MAX98373_ALC5682I_I2S Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I7b7586b0ebfe7b2fd888f448a50ae086364fa718 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44783 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-08-31mb/google/volteer: add GPP_F11 to baseboard gpio_tableNick Vaccaro
GPP_F11 was in the early gpio table, but the definition was missing from the main gpio_table. This change adds GPP_F11 to the gpio_table array. BUG=none TEST="emerge-volteer coreboot" and verify it builds correctly. Change-Id: I40f887300a9dfd4f8e790031b77bbee8a014f499 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44745 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Caveh Jalali <caveh@chromium.org>
2020-08-31mb/google/volteer: add generic DDR4 SPDs for EldridNick Vaccaro
Add Makefile.inc to include six generic DDR4 SPDs for the following parts for Eldrid: DRAM Part Name DRAM ID to assign H5AN8G6NDJR-XNC 0 (0000) MT40A512M16TB-062E:J 1 (0001) H5ANAG6NCMR-XNC 2 (0010) K4A8G165WC-BCWE 0 (0000) K4AAG165WA-BCWE 3 (0011) MT40A1G16KD-062E:E 3 (0011) Add mem_list_variant.txt as a manifest of eldrid's DRAM parts for use by gen_spd, the generic DD4 SPD generation tool. Add dram_id_generated.txt to specify DRAM ID strap settings. NOTE that Eldrid specified DRAM IDs for the first three parts to be 0 though 2 (i.e. no combined DRAM IDs for parts that use the same SPD). BUG=b:161772961 TEST="FW_NAME=eldrid emerge-volteer coreboot" and verify it builds without error. Change-Id: Ica62e299ed40e60c2d5928b29ead5d2205b1af66 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44272 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-31mb/google/volteer/var/halvor: Update TBT2 setting for HalvorFrank Wu
Enable TBT2 setting in overridetree.cb based on schematic. BUG=b:165175296, b:166060548 BRANCH=none TEST=Check all USB ports USB2 and USB3 both functional Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Change-Id: I23ecf76a3c2f631211b0ae2898707c68862b374b Reviewed-on: https://review.coreboot.org/c/coreboot/+/44747 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2020-08-30mb/google/volteer: Update flashmap descriptor for CSE Lite FW updateJamie Ryu
To support CSE Lite firmware update, CSE RW partition is extracted from CSE blob binary and added to FW_MAIN_A and FW_MAIN_B. CSE RW size for TGL is close to 2.3MB; hence, the size of FW_MAIN_A and FW_MAIN_B is increased to avoid an overflow. BUG=b:140448618 TEST=build with me_rw binary blob for volteer and boot to kernel. Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Change-Id: Ie3c2b657f0426d206dfe3729829ec34ff57812c7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43790 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-28mb/google/volteer: add initial SPDs for Elemi variantNick Vaccaro
Add mem_list_variant.txt, a list of memory parts used by elemi SKUs. Add dram_id.generated.txt, a list of dram id's to use for each memory part. Add Makefile.inc, to specify DDR4 and build the SPD file list. BUG=b:165461530 TEST=none Change-Id: I6dbcccf577161cc0c787775e2ac03e0c7039baef Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44650 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-28mb/google/volteer: update Delbin SPD for H9HCNNNCPMMLXR-NEENick Vaccaro
I noticed that re-running the lpddr4x SPD parts id tool that generates the variants/VARIANT_NAME/memory/Makefile.inc changed the SPD that is used for the H9HCNNNCPMMLXR-NEE part. $ go run ./util/spd_tools/lp4x/gen_part_id.go \ src/soc/intel/tigerlake/spd src/mainboard/google/volteer/variants/delbin/memory src/mainboard/google/volteer/variants/delbin/memory/mem_list_variant.txt Based on the currently checked in generic SPDs for LPDDR4x, this operation changes the Makefile.inc to use lp4x-spd-3.hex for the H9HCNNNCPMMLXR-NEE part instead of lp4x-spd-2.hex. This change updates that discrepancy in Delbin's memory Makefile.inc. BUG=none TEST=none Change-Id: I9a19ab7b1bcdc3814fdd9c462ca2f590c8ed2935 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44785 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-28util: rename lp4x spds to include "lp4x-" in nameNick Vaccaro
Change lp4x spd names to include lp4x memory type (eg. lp4x-spd-1.hex). BUG=b:160157545 TEST=run gen_part_id for volteer variants and verify that it changed spd names to prepend the "lp4x-" to the filename.. Change-Id: I0c59da7eb78f34640aad2e852ca725d3e8571a8e Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44784 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-28util: volteer/dedede: move generic SPDs to common locationNick Vaccaro
Now that generic SPD files have the memory type prepended to the filename, they can be stored in the same location. This CL moves the generic SPDs to the new location. Change the ddr4 gen_part_id.go and gen_spd.go tools to use "ddr4_spd_manifest.generated" instead of "spd_manifest.generated". Change the lpddr4x gen_part_id.go and gen_spd.go tools to use "lp4x_spd_manifest.generated" instead of "spd_manifest.generated". Move TGL DDR4 and LPDDR4x generic SPDs into a common location. Move JSL DDR4 and LPDDR4x generic SPDs into a common location. Change the volteer/spd/Makefile.inc to use the new path for the spds. Change the dedede/spd/Makefile.inc to use the new path for the spds. BUG=b:165854055 TEST="emerge-volteer coreboot" and verify all variants build correctly. Change-Id: I83b088cb718d15ffd3012c84a12b5231ae84a3e4 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44648 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-27mb/google/volteer*: Enable IPURavi Sarawadi
Enable IPU for Volteer and Volteer2 variants for MIPI camera. BUG=165340186 BRANCH=None TEST=IPU is enabled and shows in lspci. Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Change-Id: I66d60474e16c7a9aa8006d42b22510c1495dbd84 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44628 Reviewed-by: Daniel H Kang <daniel.h.kang@intel.corp-partner.google.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-26mb/google/volteer/variant/lindar: Update gpio and devicetree settingsJulia Tsai
Based on schematic and gpio table of lindar, generate gpio and overridetree.cb settings for lindar. BUG=b:161089195 TEST=FW_NAME=lindar emerge-volteer coreboot chromeos-bootimage Signed-off-by: Julia Tsai <julia.tsai@lcfc.corp-partner.google.com> Change-Id: Ib869eef08433dab367edd46b3dc577190b6673d8 Signed-off-by: rasheed.hsueh <rasheed.hsueh@lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44079 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Zhuohao Lee <zhuohao@chromium.org>
2020-08-26mb/google/volteer/var/halvor: Update USB relevant GPIO settingsEric Lai
Follow HW schematic to correct DDSP_HPD1/2/3 and USB_OC3 pin. BUG=b:165175296 BRANCH=none TEST=Check all USB ports USB2 and USB3 both functional Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I2f941141d761b1b69bc8f9ef0b0c4516062fec4a Reviewed-on: https://review.coreboot.org/c/coreboot/+/44651 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2020-08-25mb/google/volteer: Enable CSE Board Reset OverrideTim Wawrzynczak
This will ensure that the cold reset is performed when CSE Lite jumps from RO to RW. BUG=b:162977697 TEST=Verify CSE reset is cold (sits in S5 for PCH Min Slp Duration time) Change-Id: Ib1173e219ba46ee3275824220c8cf790b1d497fa Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44684 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-08-24mb/google/volteer/var/terrador: Add PMC.MUX.CONx devices to devicetreeDavid Wu
Add PMC.MUX.CONx devices to devicetree for terrador. BUG=b:164941862 TEST=FW_NAME=terrador emerge-volteer coreboot chromeos-bootimage Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I3f5ea4c0fbcc0117934a1ec1c350e867d881eb9d Reviewed-on: https://review.coreboot.org/c/coreboot/+/44543 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-08-24mb/google/volteer/var/todor: Add PMC.MUX.CONx devices to devicetreeDavid Wu
Add PMC.MUX.CONx devices to devicetree for todor. BUG=b:164941862 TEST=FW_NAME=todor emerge-volteer coreboot chromeos-bootimage Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: Iaef603553597685b03e805603352f38d70d65a5a Reviewed-on: https://review.coreboot.org/c/coreboot/+/44542 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-08-24mb/google/volteer: Update settings for FPMCU on HalvorJohn Su
Configure gpio settings for FPMCU on Halvor. BUG=b:153680359 TEST=After flash FP MCU FW, during bootup we see spi id spi-PRP0001:01 in dmesg. Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Change-Id: I5503cfe0fb9933e98ed01afeef8cad1345593ac6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44575 Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Caveh Jalali <caveh@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-24mb/google/volteer/var/halvor: Correct USB device tree settingEric Lai
Halvor uses TBT 0/1/2 for USB type C. We doesn't use PCIE/USB3 port therefore disable PCIE/USB3 ports and enable TBT 2. Follow volteer to set USB2 OC_SKIP. BUG=b:165175296 BRANCH=none TEST=Check all USB ports USB2 and USB3 both functional Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Ifb844ce475f3d58f0c95be0f172fc49edb4cd5fe Reviewed-on: https://review.coreboot.org/c/coreboot/+/44649 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Caveh Jalali <caveh@chromium.org>
2020-08-24mb/google/volteer/*/gpio.c: add GPP_D16 to early_gpio_tableCaveh Jalali
GPP_D16 is routed to the main power enable pin on several PCIe SD card controllers on SD daughterboards. We should enable the power to these chips as early as possible so they can participate in PCIe enumeration. BUG=b:162722965 TEST=Verified RTS5261 and GL9755 daughterboards enumerate on PCI and can read SD cards. Change-Id: Icf5e770f540e5d1e27b40f270bb004f4196bc7be Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44117 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2020-08-19mb/google/volteer: Implement weak function `cse_board_reset`Tim Wawrzynczak
Since Volteer also uses the CSE Lite SKU and the cr50, it is subject to a problem where old cr50 FW will not be able to properly detect an SoC reset, so the reset on cold boots caused by the CSE Lite RO->RW jump should instead get an assist from the EC, which can perform a full cold reset. BUG=b:162977697 TEST=Verify EC performs the cold reset Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Ie8ae21c203da218459d5fd30a23be23520ed0598 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44536 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-08-19mb/google/volteer: Update settings for trackpad on HalvorJohn Su
Configure gpio settings for trackpad. BUG=b:153680359 TEST=FW_NAME=halvor emerge-volteer coreboot chromeos-bootimage Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Change-Id: I525ba688f71b7a1893bcb64c77e02c8e2506d7b0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44524 Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-18mb/google/volteer: Configure DP_HPD as PAD_NC and disable DdiPortHpdJohn Zhao
GPP_A19(DP_HPD1) and GPP_A20(DP_HPD2) were configured native function (NF1) without internal pull-down which wrongly presents HPD interrupts. DP_HPD had been removed for EVT design as those events are through eSPI. This change configures GPP_A19 and GPP_A20 to be no connection and disables DdiPort1Hpd and DdiPort2Hpd. BUG=b:162566436 TEST=Booted to kernel and verified no kernel HPD pins assertion message on Volteer EVT board. Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: Ia3245741b776b75073d2b43d36c8ea40b476b3ed Reviewed-on: https://review.coreboot.org/c/coreboot/+/44501 Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-17mb/google/volteer: Make devicetree default as Aux Orientation retimer controlledBrandon Breitenstein
With new board designs being introduced it does not make sense for the default devicetree setting to be retimer disabled on port 0 for Aux Orientation. Change the default to be Aux Orintation retimer controlled on all ports and move the SOC controlled overrides to the corresponding overridetree files. BUG=NONE BRANCH=NONE TEST=Built image for delbin and verified that port 0 flip is working. Change-Id: I5ff59493472db096c027d223f2fd61545dc935e2 Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44358 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
2020-08-17mb/google/volteer: Define stop_gpio for goodix touch screenCaveh Jalali
This applies to the goodix touch screen on both the volteer and volteer2 variants: Define GPP_E3 as the stop_gpio for the touch screen "Report_Switch" signal. Goodix defines a 1ms (minimum) delay after stop off. In addition, no longer drive this GPIO high by default as it is now controlled by the kernel through ACPI. BUG=b:153705232 TEST=touch screen still functional on volteer; confirmed timings with scope (VDD, RESET, REPORT_SWITCH) Change-Id: I3ead9cf79812d08c4917be4585ed273050465a9b Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44356 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-08-14mb/google/volteer: Only enable TBT root ports if USB4 is supportedBrandon Breitenstein
TBT ports should be disabled if the DB is a USB3 DB. It is assumed if the DB doesn't support USB4 the platform as a whole should only be USB3 capable and TBT functionality on both ports should not be enabled. BUG=NONE BRANCH=NONE TEST=Built coreboot and verified that TBT was disabled on platform with USB3 DB and enabled on platform with USB4/TBT DB Change-Id: I594f2e9483aaf896de2b6aea9a3460bd3826c58c Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43771 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-08-13mb/google/volteer/var/halvor: Update dq/dqs mappingsFrank Wu
Update dq/dqs mappings based on halvor schematics. BUG=b:162892573 BRANCH=none TEST=FW_NAME=halvor emerge-volteer coreboot chromeos-bootimage Then boot Halvor successfully. Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Change-Id: Id4ffcbd4f015afe6507ed2b1d562519c5b240409 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44284 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2020-08-13mb/google/volteer/halvor: Enable card reader function on HalvorFrank Wu
Configure gpio settings for enabling card reader function. BUG=b:153680359 TEST=FW_NAME=halvor emerge-volteer coreboot chromeos-bootimage Verify that the sd card is mount on /dev/mmcblk0 successfully. Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Change-Id: I51752f47bc8d31d3a11da728ce00ca754381fde9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44169 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Caveh Jalali <caveh@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-12mb/google/volteer/halvor: Update settings for WiFi/BT functionsFrank Wu
Configure gpio/overridetree settings for WiFi/BT functions. Then WiFi/BT functions are enabled on Halvor. BUG=b:153680359, b:163004808 TEST=FW_NAME=halvor emerge-volteer coreboot chromeos-bootimage Verify that WiFi/BT can scan devices successfully. Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Change-Id: I085b192bb768c2c1238f3f857d315502ac10857e Reviewed-on: https://review.coreboot.org/c/coreboot/+/44372 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-12volteer: Create lindar variantJulia Tsai
Create the lindar variant of the volteer reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.1.2). BUG=b:161089195 BRANCH=None TEST=util/abuild/abuild -p none -t google/volteer -x -a make sure the build includes GOOGLE_LINDAR Signed-off-by: Julia Tsai <julia.tsai@lcfc.corp-partner.google.com> Change-Id: I08923cde932b7304bcb01cd747530c87949e4692 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44074 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Zhuohao Lee <zhuohao@google.com> Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-08-10mb/google/volteer: Pull up GPP_D16 instead of driving itCaveh Jalali
The latest realtek RTS5261 SD daughterboard exposes the PRSNT# pin to GPP_D16 but there is a RTS5261 requirement to pull up this pin and not drive it at power on. We can meet this requirement without breaking other boards by changing GPP_D16 to be a no-connect with an internal pull up. Other boards use this signal as an enable input, so changing this to pull up is OK. BUG=b:162722965 TEST=Verified RTS5261 and GL9755 daughterboards enumerate on PCI and can read SD cards. Change-Id: I096d76ec12b7c3afaf02e621fd301b6704913d5d Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44116 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-08-10mb/google/volteer/var/terrador: Update gpio settings for Proto2David Wu
Based on latest schematic and gpio table of terrador, update gpio settings for terrador Proto2. BUG=b:151978872 TEST=FW_NAME=terrador emerge-volteer coreboot chromeos-bootimage Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I64b4fcbaabc487206d14d794af319e6df6f99581 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44164 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2020-08-07mb/google/volteer: support variant defined spd pathsNick Vaccaro
Allow variants to override the SPD_SOURCE_PATH to allow supporting different types of DDR. BUG=b:163065661 TEST="emerge-volteer coreboot" and verify all variants build. Change-Id: Id52e651848548a783d6d9f57e88f6099425b063e Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44274 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Caveh Jalali <caveh@chromium.org>
2020-08-07Revert "mb/google/volteer/var/halvor: Update dq/dqs mappings"Paul Fagerburg
This reverts commit 3d813cbede650a89a519d5896652328e4ecf88c6. Reason for revert: the CL made the build unstable. Signed-off-by: Paul Fagerburg <pfagerburg@chromium.org> Change-Id: I9d067eb13196ff7d537d557d8ff864b1572a3b04 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43076 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Shelley Chen <shchen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-06mb/google/volteer/var/halvor: Update dq/dqs mappingsAmanda Huang
Update dq/dqs mappings based on halvor schematics. BUG=b:162892573 BRANCH=none TEST=FW_NAME=halvor emerge-volteer coreboot chromeos-bootimage Change-Id: I98f79283aa18f6fd41114fb6b60cac1cbed69de7 Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43988 Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-06mb/google/volteer: add support for ddr4 memoryNick Vaccaro
Add new ddr_memory_cfg structure to support both DDR4 and LPDDR4x memory types. Change existing variant code to use the new meminit_ddr() call instead of calling meminit_lpddr4x() directly. BUG=b:161772961 TEST='emerge-volteer coreboot chromeos-bootimage' and verify that volteer still boots. NOTE that this only tests the lpddr4 side of the implementation as I do not have a DDR4 board to test this on. Change-Id: Id4bca2bfa97530f0d04a0e8d90f01b8281d2aea6 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44250 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Caveh Jalali <caveh@chromium.org>
2020-08-05mb/google/volteer/var/voxel: Add Raydium touchscreen supportDavid Wu
Update gpio GPP_E7 and enable the Raydium TS support BUG=b:157402209,b:162632701,b:162636271 BRANCH=master TEST= 1. emerge-volteer coreboot chromeos-bootimage 2. boot up on voxel DUT and make sure the raydium TS can work. Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I377aded4982ece71f4dabb58f307f68c713edcd2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44055 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: YH Lin <yueherngl@google.com> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Sheng-Liang Pan <sheng-liang.pan@quanta.corp-partner.google.com>
2020-08-03mb/google/volteer: Change wake to be triggered on a raising edgeAlex Levin
ACPI_GPIO_IRQ_EDGE_BOTH sets both edges as wake. The desired behavior is wake on rising edge, change to ACPI_GPIO_INPUT_ACTIVE_LOW. Fixing for both Volteer and Volteer2 variants. BUG=b:146083964 BRANCH=None TEST=tested on a Volteer Change-Id: I2d3339151bf4e2cbae60aaf97ba1bd7909a2b9a9 Signed-off-by: Alex Levin <levinale@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44089 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2020-08-03mb/google/volteer/var/todor: Support ELAN i2c-hid touchpadDavid Wu
Update ELAN i2c-hid touchpad configuration BUG=b:160741785 BRANCH=None TEST=Verify touchpad is working fine. Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I2549048766d0707666910bd86c46ac9201bf3905 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43998 Reviewed-by: Caveh Jalali <caveh@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-29mb/google/volteer: Update TCSS D3Hot and D3Cold configurationJohn Zhao
It is expected TCSS D3Hot is enabled. D3Cold configuration is through SoC stepping determination. D3Cold is disabled on pre-QS platform and enabled on QS platform. BUG=None TEST=Verified both of TCSS D3Hot and D3Cold configuration on Volteer. Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: I9a8b838dcb449ca78d15b18543d97d84b59417ac Reviewed-on: https://review.coreboot.org/c/coreboot/+/44004 Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Divya S Sasidharan <divya.s.sasidharan@intel.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-28mb/google/volteer/var/voxel: Add memory configurationSheng-Liang Pan
Update dq/dqs mappings based on voxel schematics. BUG=b:155062561 BRANCH=none TEST=FW_NAME=voxel emerge-volteer coreboot chromeos-bootimage Signed-off-by: Pan Sheng-Liang <sheng-liang.pan@quanta.corp-partner.google.com> Change-Id: Ida248094a1477fe457026e18f313385082ee71f0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43794 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-28mb/google/volteer/var/volteer: I2C5 trackpad bus freq 400 kHz Johnny Li
The current I2C5 bus frequency is 367 kHZ, which does not meet the spec. This change updates scl_lcnt, scl_hcnt, scl_hcnt value for I2C5 to bring the bus frequency closer to 400kHz. BUG=b:153588771 TEST=Verified that I2C5 frequency is between 389-396kHz. Signed-off-by: Johnny Li <johnny_li@wistron.corp-partner.google.com> Change-Id: If59502aec7c3ab55864a518d626cde52aee18373 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43746 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Caveh Jalali <caveh@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-28mb/google/volteer2: Add support for passive USB-C daughterboardCaveh Jalali
This copies over the USB daughterboard device tree config from volteer to volteer2. These two boards are basically identical in this area so the config should also be identical. BUG=b:158673460 TEST=none Change-Id: If8a82bc18b36d92a1c851b49612edfbefa18ec54 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43849 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-07-28mb/google/volteer: sync'ing todor with terradorYH Lin
Todor is created to take the place of terrador therefore copying terrador content into todor's setup. BUG=b:162110806 BRANCH=None TEST=util/abuild/abuild -p none -t google/volteer -x -a make sure the build includes GOOGLE_TODOR Signed-off-by: YH Lin <yueherngl@google.com> Change-Id: I63151728a04f2252ca8a77158a2656ad8b1e1b51 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43841 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2020-07-28mb/google/volteer: Create todor variantYH Lin
Create the todor variant of the volteer reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.1.1). In addition, * sort the variant names in alphabetical order. * todor uses the same config options as terrador. BUG=b:162110806 BRANCH=None TEST=util/abuild/abuild -p none -t google/volteer -x -a make sure the build includes GOOGLE_TODOR Signed-off-by: YH Lin <yueherngl@google.com> Change-Id: I7aa7acf1f3c3cc14b92ded05d5868818a627a432 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43838 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Caveh Jalali <caveh@chromium.org>
2020-07-28volteer: Create eldrid variantMiceLin
Create the eldrid variant of the volteer reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.1.1). BUG=b:162115131 BRANCH=None TEST=util/abuild/abuild -p none -t google/volteer -x -a make sure the build includes GOOGLE_ELDRID Signed-off-by: MiceLin <mice_lin@wistron.corp-partner.google.com> Change-Id: I1cd07ee7a87335e1e0b51d65c26bffc3bc46037c Reviewed-on: https://review.coreboot.org/c/coreboot/+/43797 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2020-07-27mb/google/volteer: Add gpio-keys ACPI node for PENHAlex Levin
Use gpio_keys driver to add ACPI node for pen eject event. Also setting gpio wake pin for wake events. Removal and insertion (both edges) triggers IRQ and only removal is a wake event (rising edge). Adding for both Volteer and Volteer2 variants. BUG=b:146083964 BRANCH=None TEST=tested on a Volteer Change-Id: Ida3217a5b156320856ce3302c2623eba2230f28d Signed-off-by: Alex Levin <levinale@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43764 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>