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path: root/src/mainboard/google/volteer/variants/voxel/overridetree.cb
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2021-01-12mb/google/volteer: Configure Voxel USB2 ports for Type CJohn Zhao
Two USB2 ports 4 and 9 are assigned to type C connectors on Voxel board. This update configures these USB2 ports for Type C which will allow USB2 port reset message upstream from PCH to CPU to recover a USB3 device that downgraded to USB2 to upgrade back to USB3. BUG=b:176575892 TEST=Booted to kernel on Voxel board and verified usb2 port reset message enable bits through pch xhci_mmio_base + R_XHCI_MEM_U2PRM_U2PRDE where the offset register R_XHCI_MEM_U2PRM_U2PRDE has value 0x92f4. Validated various USB3 devices enumeration. Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: Ia370a449a41701e690c1c507d70bedfce2076a65 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49053 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Chiranjeevi Rapolu <chiranjeevi.rapolu@intel.corp-partner.google.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2020-12-09mb/google/volteer/variant/volta: add Synaptics touchpad.Sheng-Liang Pan
add new Synaptics touchpad for volta. BUG=b:174802144 TEST=emerge-volteer coreboot and check touchpad function work. Signed-off-by: Pan Sheng-Liang <sheng-liang.pan@quanta.corp-partner.google.com> Change-Id: I7fc8d08b8b2229ca9252618f159fc9c6f91f9d7f Reviewed-on: https://review.coreboot.org/c/coreboot/+/48395 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-08mb/google/volteer/var/voxel: Update DPTF parametersSheng-Liang Pan
remove TCC offset setting in overridetree.cb, use default setting(# TCC of 90) in baseboard. BUG=b:174547185 BRANCH=volteer TEST=emerge-volteer coreboot Signed-off-by: Pan Sheng-Liang <sheng-liang.pan@quanta.corp-partner.google.com> Change-Id: Iaac1fae12ccaa8a623bc2dc3105262918523d440 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48264 Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-24mb/google/volteer/var/voxel: Update DPTF parametersSheng-Liang Pan
update the DPTF parameters received from the thermal team. BUG=b:167523658 TEST=emerge-volteer coreboot Signed-off-by: Pan Sheng-Liang <sheng-liang.pan@quanta.corp-partner.google.com> Change-Id: Iafc3fb389ade5cfec79a816a28880262bdce7c74 Reviewed-on: https://review.coreboot.org/c/coreboot/+/47858 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-20mb/google/volteer/variants: Set TCSS PCIe RP0 to hidden by defaultDuncan Laurie
Set the default state of the TCSS PCIe RP0 to hidden so that coreboot does not allocate resources to this hotplug root port. The default behavior on the reference design is that there is only one USB4 port attached to port C1 while port C0 is only a USB3 port. Meanwhile the Voxel and Terrador variants do have USB4 on both C0 and C1 ports, so these boards change the default to 'on' so that coreboot does allocate resources for the hotplug port. BUG=b:159143739 BRANCH=volteer TEST=build volteer and voxel and check the resulting static.c to ensure the device is hidden or not. Also boot with the two different configurations and ensure resources are assigned or not. Finally check that S0ix still functions with the C0 port set to 'hidden' after authorizing a PCIe tunnel on port C1. Signed-off-by: Duncan Laurie <dlaurie@google.com> Change-Id: I8bb05ae8cd14412854212b7ed189cfa43d602c1d Reviewed-on: https://review.coreboot.org/c/coreboot/+/47198 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-20mb/google/volteer/variants: Enable RTD3 for the NVMe deviceDuncan Laurie
Enable Runtime D3 for the volteer variants that have GPIO power control of the NVMe device attached to PCIe Root Port 9. Enable the GPIO for power control for variants that do not already have it configured to allow the power to be disabled in D3 state. BUG=b:160996445 TEST=tested on delbin Change-Id: I6ebf813c6c3364fec2e489a9742f04452be92c45 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46262 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-13mb/google/volteer: Configure IRQs as level triggered for HID over I2CKarthikeyan Ramasubramanian
As per HID over I2C Protocol Specification[1] Version 1.00 Section 7.4, the interrupt line used by the device is required to be level triggered. Hence, this change updates the configuration of the HID over I2C devices to be level triggered. References: [1] http://download.microsoft.com/download/7/d/d/7dd44bb7-2a7a-4505-ac1c-7227d3d96d5b/hid-over-i2c-protocol-spec-v1-0.docx BUG=b:172846122 TEST=./util/abuild/abuild Change-Id: Ie7b82ea07ef97b2096d75229c445bd3a65cb3be0 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47416 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-11-02mb/google/volteer/variants: Describe USB ports in devicetreeDuncan Laurie
Add the USB ports to the devicetree for describing them in ACPI, including defining the port relationships and defining the reset GPIO for the bluetooth device. BUG=b:151731851 TEST=tested on volteer, all other boards were checked against the latest available schematic. Signed-off-by: Duncan Laurie <dlaurie@google.com> Change-Id: Ia1e5b71e7750a478ff79372c48616bbf5c21b79c Reviewed-on: https://review.coreboot.org/c/coreboot/+/46853 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-10-30tigerlake mainboards: switch to devtree aliases for PMC MUX connectorsTim Wawrzynczak
Now that soc_get_pmc_mux_device() is gone, the PMC MUX connector devices can be hooked up together via devicetree aliases. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Ib51764da5b3c029f9ac7ac60199a0aedfc7f29b1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45878 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-26mb/google/volteer/var/voxel: Disable SRCCLKREQ1#Sheng-Liang Pan
According to the schematic,SRCCLKREQ1# is not connected,so disable it on voxel. BUG=b:171279034 BRANCH=volteer TEST="emerge-volteer coreboot" compiles successfully. Signed-off-by: Pan Sheng-Liang <sheng-liang.pan@quanta.corp-partner.google.com> Change-Id: Ibc4f766bd737f30a9ac3c7354d54398e0c36d59d Reviewed-on: https://review.coreboot.org/c/coreboot/+/46612 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-12mb/google/volteer/var/voxel: disable DdiPortHpdSheng-Liang Pan
GPP_A19 and GPP_A20 set no connection, disables DdiPort1Hpd and DdiPort2Hpd BUG=b:169690329 TEST=build and verify type-c(C0/C1) port functional normally Signed-off-by: Pan Sheng-Liang <sheng-liang.pan@quanta.corp-partner.google.com> Change-Id: I4405526ae777332d3c72041db7b4eda25ae31b8e Reviewed-on: https://review.coreboot.org/c/coreboot/+/46069 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: TH Lin <t.h_lin@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-10mb/google/volteer: Use device aliasesDuncan Laurie
Use the device aliases provided by tigerlake chipset.cb instead of the raw pci device+function. Take advantage of the default states in chipset.cb and only list the devices that are enabled for all volteer variants. Change-Id: I5620004afd7fa4d50389f32dd79148960a2b2662 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44039 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-14mb/google/volteer/var/voxel: Update DPTF parameters and TCC offsetDavid Wu
1. Set tcc offset to 5 degree celsius 2. Apply the DPTF parameters received from the thermal team. BUG=b:167523658 TEST=build and verify by thermal team Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I01a6fc5bd959798c8dd423df3907c69c883733e8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45111 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-08-05mb/google/volteer/var/voxel: Add Raydium touchscreen supportDavid Wu
Update gpio GPP_E7 and enable the Raydium TS support BUG=b:157402209,b:162632701,b:162636271 BRANCH=master TEST= 1. emerge-volteer coreboot chromeos-bootimage 2. boot up on voxel DUT and make sure the raydium TS can work. Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I377aded4982ece71f4dabb58f307f68c713edcd2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44055 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: YH Lin <yueherngl@google.com> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Sheng-Liang Pan <sheng-liang.pan@quanta.corp-partner.google.com>
2020-07-06mb/google/volteer: Rename remaining pmc_mux/con to connPatrick Georgi
CB:43090 renamed con to conn to avoid issues when building on Windows. CB:42905 introduced more uses of the old name. Adapt the latter to comply with the former. Change-Id: I723141add5452fc541f67cb8591793f2d64cc231 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43141 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Christian Walter <christian.walter@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-06mb/google/volteer/var/voxel: Update gpio settings and overridetree.cbDavid Wu
Based on schematic and gpio table of voxel, generate gpio settings and overridetree.cb for voxel. BUG=b:157879197,b:155062762 TEST=FW_NAME=voxel emerge-volteer coreboot chromeos-bootimage Verify that the image-voxel.bin is generated successfully. Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I49c1923e63d87f11de362fd893905ac2f1137bba Reviewed-on: https://review.coreboot.org/c/coreboot/+/42731 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Caveh Jalali <caveh@chromium.org>
2020-06-04mb/google/volteer: Create voxel variantDavid Wu
Create the voxel variant of the volteer reference board BUG=b:157879197 BRANCH=None TEST=util/abuild/abuild -p none -t google/volteer -x -a make sure the build includes GOOGLE_VOXEL Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I8ba5412be211730db84675927c500238cb20ff3d Reviewed-on: https://review.coreboot.org/c/coreboot/+/41968 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
generated by cgit v1.2.3 (git 2.39.1) at 2024-07-07 22:52:42 +0000