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BT_DISABLE_L (GPP_A13) has to asserted in early_gpio_table to reset
bluetooth on reset.
BUG=b:171085081
TEST=volteer2 boots; scope shows assertion of the signal
Change-Id: Iaa5799e9cab69c074b7920604c8a6c85ad07358a
Signed-off-by: Alex Levin <levinale@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48518
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
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Update Power Limit2 (PL2) minimum value to the same as maximum value for
volteer variants like baseboard, delbin, eldrid, terrador and todor.
All other variants uses the DTT entries from baseboard devicetree since
there is no override present for those variants. DTT does not throttle PL2,
so this minimum value change here does not impact any existing behavior on
the system.
BUG=None
BRANCH=volteer
TEST=Build and test on volteer system
Change-Id: I568e87c87ef517e96eaab3ff144b1674d26ae1e6
Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48292
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Remove the following devices
- Goodix Touchscreen
- SAR0 Proximity Sensor
BUG=b:173480406
TEST=FW_NAME=terrador emerge-volteer coreboot chromeos-bootimage
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I6b56ca136533b53ff7e003a665be67fbe12c1ade
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47690
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The GPP_F16 is for enable_gpio after check the schematic.
BUG=b:151978872
TEST=FW_NAME=terrador emerge-volteer coreboot chromeos-bootimage
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I63f43c231e624ed034ef18e8f06942ff3622d821
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47742
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
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As per HID over I2C Protocol Specification[1] Version 1.00 Section 7.4,
the interrupt line used by the device is required to be level triggered.
Hence, this change updates the configuration of the HID over I2C devices
to be level triggered.
References:
[1] http://download.microsoft.com/download/7/d/d/7dd44bb7-2a7a-4505-ac1c-7227d3d96d5b/hid-over-i2c-protocol-spec-v1-0.docx
BUG=b:172846122
TEST=./util/abuild/abuild
Change-Id: Ie7b82ea07ef97b2096d75229c445bd3a65cb3be0
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47416
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Terrador and Todor are fanless design, so disable DPTF active policy.
BUG=b:171019363,b:170699797
BRANCH=volteer
TEST=build and verify by thermal team
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I53a33b8706d7a7d4013a2a5627a620223fcffc3e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46874
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Now that soc_get_pmc_mux_device() is gone, the PMC MUX connector devices
can be hooked up together via devicetree aliases.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Ib51764da5b3c029f9ac7ac60199a0aedfc7f29b1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45878
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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According to the schematic, SRCCLKREQ1# is not connected, so disable it
for terrador and todor.
BUG=b:171278849
BRANCH=volteer
TEST="emerge-volteer coreboot" compiles successfully.
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I5f7734d64390bfadbdb8d152261103adb8e75f40
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46592
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sheng-Liang Pan <sheng-liang.pan@quanta.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Configure board specific DPTF parameters for terrador and todor
BUG=b:171019363,b:170699797
BRANCH=volteer
TEST=build and verify by thermal team
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I19935ca98ec7a078869e73d65ea471df70f37121
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46487
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Use the device aliases provided by tigerlake chipset.cb instead of
the raw pci device+function. Take advantage of the default states
in chipset.cb and only list the devices that are enabled for all
volteer variants.
Change-Id: I5620004afd7fa4d50389f32dd79148960a2b2662
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44039
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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It needs to use probe statement in overridetree.cb to enable the cache
of fw_config field implemented by cb:44782 and cb:44783.
BUG=b:161963281
TEST= dmidecode -t 11 shows correct audio fw_config.
Handle 0x0009, DMI type 11, 5 bytes
OEM Strings
String 1: DB_USB-USB4_GEN2
String 2: AUDIO-MAX98373_ALC5682I_I2S_UP4
Signed-off-by: Kevin Cheng <kevin.cheng@intel.com>
Change-Id: I68c19b67d945aaca3e9ebec87eb27a4b07e1a49e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45673
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Setting USBx_PORT_EMPTY is not a requirement anymore, since unset
devicetree settings default to 0 and the OC pin now only gets set when
the USB port is enabled (see CB:45112).
Thus, drop the setting from all devicetrees.
Change-Id: I899349c49fa7de1c1acdca24994ebe65c01d80c6
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45125
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
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Change lp4x spd names to include lp4x memory type (eg. lp4x-spd-1.hex).
BUG=b:160157545
TEST=run gen_part_id for volteer variants and verify that it changed
spd names to prepend the "lp4x-" to the filename..
Change-Id: I0c59da7eb78f34640aad2e852ca725d3e8571a8e
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44784
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add PMC.MUX.CONx devices to devicetree for todor.
BUG=b:164941862
TEST=FW_NAME=todor emerge-volteer coreboot chromeos-bootimage
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: Iaef603553597685b03e805603352f38d70d65a5a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44542
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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GPP_D16 is routed to the main power enable pin on several PCIe SD card
controllers on SD daughterboards. We should enable the power to these
chips as early as possible so they can participate in PCIe
enumeration.
BUG=b:162722965
TEST=Verified RTS5261 and GL9755 daughterboards enumerate on PCI and
can read SD cards.
Change-Id: Icf5e770f540e5d1e27b40f270bb004f4196bc7be
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44117
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
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Add new ddr_memory_cfg structure to support both DDR4 and LPDDR4x
memory types.
Change existing variant code to use the new meminit_ddr() call
instead of calling meminit_lpddr4x() directly.
BUG=b:161772961
TEST='emerge-volteer coreboot chromeos-bootimage' and verify that
volteer still boots. NOTE that this only tests the lpddr4 side
of the implementation as I do not have a DDR4 board to test this on.
Change-Id: Id4bca2bfa97530f0d04a0e8d90f01b8281d2aea6
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44250
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
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Update ELAN i2c-hid touchpad configuration
BUG=b:160741785
BRANCH=None
TEST=Verify touchpad is working fine.
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I2549048766d0707666910bd86c46ac9201bf3905
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43998
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Todor is created to take the place of terrador therefore
copying terrador content into todor's setup.
BUG=b:162110806
BRANCH=None
TEST=util/abuild/abuild -p none -t google/volteer -x -a
make sure the build includes GOOGLE_TODOR
Signed-off-by: YH Lin <yueherngl@google.com>
Change-Id: I63151728a04f2252ca8a77158a2656ad8b1e1b51
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43841
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
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Create the todor variant of the volteer reference board by copying
the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.1.1).
In addition,
* sort the variant names in alphabetical order.
* todor uses the same config options as terrador.
BUG=b:162110806
BRANCH=None
TEST=util/abuild/abuild -p none -t google/volteer -x -a
make sure the build includes GOOGLE_TODOR
Signed-off-by: YH Lin <yueherngl@google.com>
Change-Id: I7aa7acf1f3c3cc14b92ded05d5868818a627a432
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43838
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
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