coreboot.git - my copy of coreboot

Age	Commit message (Collapse)	Author
2020-05-21	mb/google/volteer: fix error in generic SPD	Nick Vaccaro
	The SPD_LPDDR4X_200b_8bank_1Rx16_16Gb_DDP_4267.spd.hex SPD contained an incorrect SDRAM Max Cycle Time (0 instead of 0x0f). After fixing that error, I noticed that two generic SPDs could be collapsed into one, so I removed one of the duplicate generic SPDs (SPD_LPDDR4X_200b_8bank_1Rx16_16Gb_16Row_DDP_4267.spd.hex), and changed Makefile to collapse volteer's DRAM ID 2 into ID 0. BUG=b:156126658, b:156058720 TEST=Flash and boot a ripto to kernel. Also verified that ripto can boot successfully to the kernel at 4267 MT/sec with FSP built in debug mode with RMT enabled. Change-Id: Ib52bf674ebf91854d3d078015aa640aa7ee98a6f Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41345 Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-13	mb/google/volteer: move SPD files to variant directories	Nick Vaccaro
	Memory SPD files for each variant are now stored in the variant's mb/google/volteer/variants/<variant_name>/spd directory instead of storing them in mb/google/volteer/spd. This change moves SPDs to where they are needed and changes the makefile to look for them in their new locations. BUG=b:156126658 TEST="emerge-volteer coreboot chromeos-bootimage", flash and boot a proto2 SKU4 to the kernel. Change-Id: I759c979027477a2a4c5489a6b12278799488d6e7 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41184 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>