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path: root/src/mainboard/google/volteer/variants/delbin
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2020-11-02mb/google/volteer/variants/delbin: Update DPTF parameters for delbinFrank Chu
Configure board specific DPTF parameters for delbin BUG=b:168958222 BRANCH=volteer TEST=build and verify by thermal team Signed-off-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com> Change-Id: I69aa6046fdc90a2cf59ea3a13fdb15c8bc0d29a2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46676 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-30tigerlake mainboards: switch to devtree aliases for PMC MUX connectorsTim Wawrzynczak
Now that soc_get_pmc_mux_device() is gone, the PMC MUX connector devices can be hooked up together via devicetree aliases. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Ib51764da5b3c029f9ac7ac60199a0aedfc7f29b1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45878 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-23mb/google/volteer: Add settings for noise mitgationShaunak Saha
Enable acoustic noise mitgation for volteer platforms. BUG=b:153015585 BRANCH=none TEST= Measure the change in noise level by changing the values in devicetree. Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Change-Id: I69a6453091bf607d3c5847c99bc077e6b7dbc639 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45053 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-10mb/google/volteer: Use device aliasesDuncan Laurie
Use the device aliases provided by tigerlake chipset.cb instead of the raw pci device+function. Take advantage of the default states in chipset.cb and only list the devices that are enabled for all volteer variants. Change-Id: I5620004afd7fa4d50389f32dd79148960a2b2662 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44039 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-14mb/google/delbin: Configure DP_HPD as PAD_NC and disable DdiPortHpdRavi Sarawadi
GPP_A19(DP_HPD1) and GPP_A20(DP_HPD2) were configured native function (NF1) without internal pull-down which wrongly presents HPD interrupts. DP_HPD had been removed for EVT design as those events are through eSPI. This change configures GPP_A19 and GPP_A20 to be no connection and disables DdiPort1Hpd and DdiPort2Hpd. BUG=b:162566436 TEST=Booted to kernel and verified no kernel HPD pins assertion message on Delbin board. Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Change-Id: Ifdef8ee438276678258b75d2fb70c6dfc7ee0a33 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45031 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Caveh Jalali <caveh@chromium.org>
2020-08-28mb/google/volteer: update Delbin SPD for H9HCNNNCPMMLXR-NEENick Vaccaro
I noticed that re-running the lpddr4x SPD parts id tool that generates the variants/VARIANT_NAME/memory/Makefile.inc changed the SPD that is used for the H9HCNNNCPMMLXR-NEE part. $ go run ./util/spd_tools/lp4x/gen_part_id.go \ src/soc/intel/tigerlake/spd src/mainboard/google/volteer/variants/delbin/memory src/mainboard/google/volteer/variants/delbin/memory/mem_list_variant.txt Based on the currently checked in generic SPDs for LPDDR4x, this operation changes the Makefile.inc to use lp4x-spd-3.hex for the H9HCNNNCPMMLXR-NEE part instead of lp4x-spd-2.hex. This change updates that discrepancy in Delbin's memory Makefile.inc. BUG=none TEST=none Change-Id: I9a19ab7b1bcdc3814fdd9c462ca2f590c8ed2935 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44785 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-28util: rename lp4x spds to include "lp4x-" in nameNick Vaccaro
Change lp4x spd names to include lp4x memory type (eg. lp4x-spd-1.hex). BUG=b:160157545 TEST=run gen_part_id for volteer variants and verify that it changed spd names to prepend the "lp4x-" to the filename.. Change-Id: I0c59da7eb78f34640aad2e852ca725d3e8571a8e Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44784 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-24mb/google/volteer/*/gpio.c: add GPP_D16 to early_gpio_tableCaveh Jalali
GPP_D16 is routed to the main power enable pin on several PCIe SD card controllers on SD daughterboards. We should enable the power to these chips as early as possible so they can participate in PCIe enumeration. BUG=b:162722965 TEST=Verified RTS5261 and GL9755 daughterboards enumerate on PCI and can read SD cards. Change-Id: Icf5e770f540e5d1e27b40f270bb004f4196bc7be Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44117 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2020-08-06mb/google/volteer: add support for ddr4 memoryNick Vaccaro
Add new ddr_memory_cfg structure to support both DDR4 and LPDDR4x memory types. Change existing variant code to use the new meminit_ddr() call instead of calling meminit_lpddr4x() directly. BUG=b:161772961 TEST='emerge-volteer coreboot chromeos-bootimage' and verify that volteer still boots. NOTE that this only tests the lpddr4 side of the implementation as I do not have a DDR4 board to test this on. Change-Id: Id4bca2bfa97530f0d04a0e8d90f01b8281d2aea6 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44250 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Caveh Jalali <caveh@chromium.org>
2020-07-27mb/google/volteer: Modify Delbin variantKane Chen
Update delbin configuration include GPIO, memory SPD table, I2C devices and USB type C. BUG=b:158797761 BRANCH=None TEST=emerge-volteer coreboot Signed-off-by: Kane Chen <kane_chen@pegatron.corp-partner.google.com> Change-Id: I59ce4720e0ffeeeb2c9440bb300686def80211ea Reviewed-on: https://review.coreboot.org/c/coreboot/+/42301 Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-26*/mb/google/volteer/**/gpio.h: Fix up license headerAngel Pons
There's a `GPL-2.0-or-later` version of this file in volteer2, so use it in place of these weirdly-licensed files. Change-Id: Icde2f6539d9c726d6967350f74e7bc015e01e7b5 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43855 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-07-24mb/google/volteer: Remove unused dptf.asl filesTim Wawrzynczak
In the middle of the Great DPTF Refactor of 2020, new volteer variants were added, but their dptf.asl files are no longer used, so delete them. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I52f2042aa870a29026eb9fe122340ad07654e706 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43828 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Caveh Jalali <caveh@chromium.org>
2020-07-14mainboard/volteer: Enable SaGv for volteer2, delbin & voxelShreesh Chhabbi
SaGv needs to be enabled for only QS. On ES2, we are seeing system instability. BUG=b:159198381 TEST=Tested for boot. Power and performance tests were run with volteer2 with qs setup. System showed stability. Tested for boot stability on on delbin. Change-Id: I1bce3b9f837fb19ba5a20ae31750a73474a86788 Signed-off-by: Shreesh Chhabbi <shreesh.chhabbi@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42483 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Caveh Jalali <caveh@chromium.org>
2020-06-24volteer: Create delbin variantZhuohao Lee
Create the delbin variant of the volteer reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.1.1). BUG=b:158797761 BRANCH=None TEST=util/abuild/abuild -p none -t google/volteer -x -a make sure the build includes GOOGLE_DELBIN Signed-off-by: Zhuohao Lee <zhuohao@chromium.org> Change-Id: Icf5fc6b9cc6a7c47e52103b2d396bcddb26adf50 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42709 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
generated by cgit v1.2.3 (git 2.39.1) at 2024-07-09 01:18:12 +0000