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path: root/src/mainboard/google/volteer/chromeos.fmd
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2020-12-09mb/google/volteer: Reorganize FMAPFurquan Shaikh
This change reorganizes FMAP for volteer to make use of the lower 16MiB of the SPI flash for RW_SECTION_A and RW_MISC in addition to RW_LEGACY. This is now possible because TGL supports memory mapping of BIOS region greater than 16MiB. Following changes are made in chromeos.fmd as part of this: 1. Move RW_SECTION_A and RW_MISC to lower 16MiB. 2. Reduce size of RW_LEGACY to 2MiB since we longer need to use it as a placeholder in the lower half of the SPI flash. 3. Reduce size of RW_ELOG to 4KiB as coreboot does not support a larger region for ELOG. 4. Increase WP_RO to 8MiB to allow larger space for firmware screens. GBB size is thus increased to 448KiB. BUG=b:171534504 Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I0c3c0af94183a80c23d196422d3c8cf960b9d9f5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48187 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2020-11-18mb/google/volteer: Update flashmap descriptor to add ME_RW_A/B regionJamie Ryu
The current CSE firmware update implementation adds CSE RW binary to FW_MAIN_A/B and this increases the boot time due to the size increase of these regions leading to higher loading and hashing time. To mitigate this issue, CSE RW binary is moved from FW_MAIN_A/B to new region, ME_RW_A/B under RW_SECTON_A/B, and this updates the flashmap to add ME_RW_A/B region for CSE RW binary. BUG=b:169077783 TEST=build with cse rw binary, flash and verify volteer2 boots to OS. Verify me_rw binary is added to ME_RW_A/B region. Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Change-Id: I87da3824933ed2dd8e8ed0fed8686d2a3527faea Reviewed-on: https://review.coreboot.org/c/coreboot/+/46431 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-08-30mb/google/volteer: Update flashmap descriptor for CSE Lite FW updateJamie Ryu
To support CSE Lite firmware update, CSE RW partition is extracted from CSE blob binary and added to FW_MAIN_A and FW_MAIN_B. CSE RW size for TGL is close to 2.3MB; hence, the size of FW_MAIN_A and FW_MAIN_B is increased to avoid an overflow. BUG=b:140448618 TEST=build with me_rw binary blob for volteer and boot to kernel. Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Change-Id: Ie3c2b657f0426d206dfe3729829ec34ff57812c7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43790 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-09mb/google/volteer: add volteer mainboard initial supportNick Vaccaro
Created a new Google baseboard named volteer from scratch. BUG=b:142961277 BRANCH=master TEST="emerge-volteer coreboot" compiles successfully. Change-Id: I03a13f3df4e819ab9cf63ad69867c807d2a1b651 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38620 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>