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path: root/src/mainboard/google/veyron_rialto/sdram_inf
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2016-10-06google/veyron_rialto: Add lpddr3-K4E6E304EB-2GB-1CH memory configurationJeffy Chen
Add lpddr3-K4E6E304EB-2GB-1CH memory configuration for rialto. BUG=chrome-os-partner:56759 BRANCH=none TEST=Build Change-Id: I698fe450d48b64a06232aa44ecf91d688d9dc17a Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: d3edecdb135939c3264ab1b831e7821d3a3e0149 Original-Change-Id: I7dae9fd822abeff5b08de0ab9262e1817ac58531 Original-Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/380443 Original-Commit-Ready: Alexandru Stan <amstan@chromium.org> Original-Tested-by: Alexandru Stan <amstan@chromium.org> Original-Reviewed-by: Alexandru Stan <amstan@chromium.org> Original-Reviewed-by: Jonathan Dixon <joth@chromium.org> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/16699 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-08-01Add newlines at the end of all coreboot filesMartin Roth
Change-Id: I7930d5cded290f2605d0c92a9c465a3f0c1291a2 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/15974 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-04-21veyron: The ODT function is disabled for LPDDR3jinkun.hong
We found that we should better keep ODT off for LPDDR3 on our boards. BRANCH=veyron BUG=chrome-os-partner:37346 TEST=Boot veyron_speedy normal Change-Id: Id158c88769cf7ed1a5127cd09bad679a2f5e6a01 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 0d85725a6faedb5bdbe8731991c225c31f138599 Original-Change-Id: Iebb8e74706756508dd56b85ad87baad48893c619 Original-Signed-off-by: jinkun.hong <jinkun.hong@rock-chips.com> Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/255381 Reviewed-on: http://review.coreboot.org/9830 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-15veyron: Add veyron_rialto boardjinkun.hong
Derived from of veyron_brain with new memory configuration. BUG=chrome-os-partner:35072 TEST=built and boot on rialto-rev0 boards. BRANCH=veyron Change-Id: I2c6f74d231e39de76ef2399fdb20efae977b34fa Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 17d66e5f58562427badd6973ebb053f58573c040 Original-Change-Id: I8626ff5da8098ca120481b8cda0c6703f806711e Original-Signed-off-by: jinkun.hong <jinkun.hong@rock-chips.com> Original-Signed-off-by: Hung-Te Lin <hungte@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/238946 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Trybot-Ready: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/9649 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>