aboutsummaryrefslogtreecommitdiff
path: root/src/mainboard/google/veyron_mickey/sdram_configs.c
AgeCommit message (Collapse)Author
2020-05-11treewide: Remove "this file is part of" linesPatrick Georgi
Stefan thinks they don't add value. Command used: sed -i -e '/file is part of /d' $(git grep "file is part of " |egrep ":( */\*.*\*/\$|#|;#|-- | *\* )" | cut -d: -f1 |grep -v crossgcc |grep -v gcov | grep -v /elf.h |grep -v nvramtool) The exceptions are for: - crossgcc (patch file) - gcov (imported from gcc) - elf.h (imported from GNU's libc) - nvramtool (more complicated header) The removed lines are: - fmt.Fprintln(f, "/* This file is part of the coreboot project. */") -# This file is part of a set of unofficial pre-commit hooks available -/* This file is part of coreboot */ -# This file is part of msrtool. -/* This file is part of msrtool. */ - * This file is part of ncurses, designed to be appended after curses.h.in -/* This file is part of pgtblgen. */ - * This file is part of the coreboot project. - /* This file is part of the coreboot project. */ -# This file is part of the coreboot project. -# This file is part of the coreboot project. -## This file is part of the coreboot project. --- This file is part of the coreboot project. -/* This file is part of the coreboot project */ -/* This file is part of the coreboot project. */ -;## This file is part of the coreboot project. -# This file is part of the coreboot project. It originated in the - * This file is part of the coreinfo project. -## This file is part of the coreinfo project. - * This file is part of the depthcharge project. -/* This file is part of the depthcharge project. */ -/* This file is part of the ectool project. */ - * This file is part of the GNU C Library. - * This file is part of the libpayload project. -## This file is part of the libpayload project. -/* This file is part of the Linux kernel. */ -## This file is part of the superiotool project. -/* This file is part of the superiotool project */ -/* This file is part of uio_usbdebug */ Change-Id: I82d872b3b337388c93d5f5bf704e9ee9e53ab3a9 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41194 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-06mb/google/veyron_mickey: Use SPDX for GPL-2.0-only filesAngel Pons
Done with sed and God Lines. Only done for C-like code for now. Change-Id: Icabeae8d5c6c8be8dc284354e1523cec04c9fe30 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40200 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-18mainboard/google: Remove copyright noticesPatrick Georgi
They're listed in AUTHORS and often incorrect anyway, for example: - What's a "Copyright $year-present"? - Which incarnation of Google (Inc, LLC, ...) is the current copyright holder? - People sometimes have their editor auto-add themselves to files even though they only deleted stuff - Or they let the editor automatically update the copyright year, because why not? - Who is the copyright holder "The coreboot project Authors"? - Or "Generated Code"? Sidestep all these issues by simply not putting these notices in individual files, let's list all copyright holders in AUTHORS instead and use the git history to deal with the rest. Change-Id: I09cc279b1f75952bb397de2c3f2b299255163685 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39607 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2019-03-20src: Use 'include <string.h>' when appropriateElyes HAOUAS
Drop 'include <string.h>' when it is not used and add it when it is missing. Also extra lines removed, or added just before local includes. Change-Id: Iccac4dbaa2dd4144fc347af36ecfc9747da3de20 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31966 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-03-04arch/io.h: Drop unnecessary includeKyösti Mälkki
Change-Id: I91158452680586ac676ea11c8589062880a31f91 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/31692 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-09Veyron: fix sdram config for Hynix H9CCNNNBKTMLBR-NTDLoop_Wu
Sdram config sdram-lpddr3-hynix-4GB.inc for H9CCNNNBKTMLBR-NTD can't boot on Mickey. It's confirmed that the right config for Hynix H9CCNNNBKTMLBR-NTD is sdram-lpddr3-hynix-2GB-BK.inc. BUG=b:122239609 BRANCH=master TEST=boot on mickey Change-Id: Ifeaadda50d939e0c118cb7fe3964dcd08b709c2a Signed-off-by: Loop_Wu <Loop_Wu@asus.com> Reviewed-on: https://review.coreboot.org/c/30761 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-10-31Veyron: add Hynix H9CCNNNBKTMLBR-NTD ddr with RAMID '00Z1'Loop_Wu
Confirm with RK, H9CCNNNBKTMLBR-NTD uses this sdram config. sdram-lpddr3-hynix-4GB.inc BUG=b:117967129 BRANCH=master TEST=None Change-Id: I98afc33fd2cb61343be0dcdc007add75bee9c2af Signed-off-by: Loop_Wu <Loop_Wu@asus.com> Reviewed-on: https://review.coreboot.org/29366 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2017-03-07google/veyron: add K4B4G1646E-BYK0 ddr with ramid 000ZShunqian Zheng
The K4B4G1646E-BYK0 shares sdram config with K4B4G1646D-BYK0. For clarity, sdram-ddr3-samsung-2GB now is used by - K4B4G1646D-BYK0 - K4B4G1646E-BYK0 - K4B4G1646Q-HYK0 BUG=chrome-os-partner:62131 BRANCH=veyron TEST=emerge Change-Id: Ie43f23bf8f5f5b1acbb74c85cac17fe181c841c4 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 46d62d87101e0ee1050b00db02b3ecaa4587e9f4 Original-Change-Id: I461c6f36c28ea0eeaf7d64292c9c87ab0c9de443 Original-Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/446197 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-(cherry picked from commit f98251a4a4fe4d49721a936a684f6ac80f3f6405) Original-Reviewed-on: https://chromium-review.googlesource.com/446300 Reviewed-on: https://review.coreboot.org/18519 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2017-03-07google/veyron_*: Add new Micron and Hynix modulesDavid Hendricks
This adds SDRAM entries for the following modules: - Micron: DDMT52L256M64D2PP-107 - Hynix: H9CCNNNBKTALBR-NUD They are compatible with Samsung K4E8E324EB-EGCF, so this just copies sdram-lpddr3-samsung-2GB-24EB.inc and changes the name used in the comment near the top. Notes on our "special snowflake" boards: - veyron_danger's RAM ID is hard-coded to zero, so I skipped changes involving the binary first numbering scheme. - Rialto's SDRAM mapping is different, so I padded its SDRAM entries to 24 to match other boards. - veyron_mickey requires different MR3 and ODT settings than other boards due to its unique PCB (chrome-os-partner:43626). BUG=chrome-os-partner:59997 BRANCH=none TEST=Booted new modules on Mickey (see BUG) Change-Id: If2e22c83f4a08743f12bbc49b3fabcbf1d7d07dd Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 35cac483e86e57899dbb0898dad3510f4c2ab2d3 Original-Change-Id: I22386a25b965a4b96194d053b97e3269dbdea8c7 Original-Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/412328 Original-Reviewed-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Queue: Jiazi Yang <Tomato_Yang@asus.com> Original-Tested-by: Jiazi Yang <Tomato_Yang@asus.com> Original-(cherry picked from commit bd5aa1a5488b99f2edc3e79951064a1f824062f6) Original-Reviewed-on: https://chromium-review.googlesource.com/446299 Original-Commit-Ready: Shunqian Zheng <zhengsq@rock-chips.com> Original-Tested-by: Shunqian Zheng <zhengsq@rock-chips.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/18518 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-03google/veyron*: add DDR configs for new samsung DDRZhengShunQian
Add the new samsung DDR configs for all veyron except veyron_rialto: * K4E6E304EB-EGCE, ramid = 0010, 4GB * K4E8E324EB-EGCF, ramid = 1100, 2GB BRANCH=veyron BUG=none TEST=boot fievel board Change-Id: I747aa86f8c93174651a28face63b3386e22b23b3 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 5f55462e71bd481eda85af3d582cfe5b9873cc9c Original-Change-Id: I19123634c994f685683323f7d85cc4d35814e2ab Original-Signed-off-by: ZhengShunQian <zhengsq@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/345748 Original-Commit-Queue: Ren Kuo <ren.kuo@quantatw.com> Original-Reviewed-by: Philip Chen <philipchen@chromium.org> Original-(cherry-pick from cc990f27024255a326fd9fa9644deb28b01a31a7) Original-Reviewed-on: https://chromium-review.googlesource.com/404690 Original-Commit-Ready: Shunqian Zheng <zhengsq@rock-chips.com> Original-Tested-by: Shunqian Zheng <zhengsq@rock-chips.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/17209 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-01-21google/veyron_mickey: Update Hynix memory configurationLang Zhang
Update Hynix memory configuration for mickey so that it can boot on Hynix board. BUG=chrome-os-partner:48637 BRANCH=master TEST=Boot on mickey hynix board Change-Id: Ibbf90cf76793005e23a720b97540b268ebf0864d Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 071167b667685c26106641e6899984c7bd91e84b Original-Change-Id: Id63d74cac36b9fd84bdb88969291982e14fa7d01 Original-Signed-off-by: Lang Zhang <kingsley_zhang@asus.com> Original-Reviewed-on: https://chromium-review.googlesource.com/320623 Original-Commit-Ready: lang zhang <kingsley_zhang@asus.com> Original-Tested-by: lang zhang <kingsley_zhang@asus.com> Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: https://review.coreboot.org/13048 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-10-31tree: drop last paragraph of GPL copyright headerPatrick Georgi
It encourages users from writing to the FSF without giving an address. Linux also prefers to drop that and their checkpatch.pl (that we imported) looks out for that. This is the result of util/scripts/no-fsf-addresses.sh with no further editing. Change-Id: Ie96faea295fe001911d77dbc51e9a6789558fbd6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/11888 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-08-28veyron: add Nanya NT5CC256M16DP sdramjinkun.hong
BRANCH=None TEST=Boot from veyron BUG=None Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Original-Commit-Id: 6fe83821013954f0f2069598fd90a2d49de81101 Original-Change-Id: I68b105aa4bc3e82ef6a2421b127391e319c34d6e Original-Signed-off-by: jinkun.hong <jinkun.hong@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/294660 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-(cherry picked from commit c115d9a3ea2ca1cb62b2a1ee75996d8adb991d5d) Original-jwerner: Added Minnie Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/294763 Change-Id: I2bd6521c209db0e2d7d0bdb8ef2cde2715f321a6 Reviewed-on: http://review.coreboot.org/11399 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-05google/veyron_mickey: Add new mainboardDavid Hendricks
This simply copies veyron_brain to veyron_mickey and makes the minimal set of changes (s/brain/mickey) to make it compile. The follow-up patch will take into account board differences. BUG=none BRANCH=none TEST="emerge-veyron_mickey coreboot" doesn't fail Change-Id: I7d029b36d2fb865446490b896117ade632325a52 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 34f6b391290f99caf517d7e98c31c89dc57309be Original-Change-Id: I03a2b80eb441384f363910467180479521765431 Original-Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/271360 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/10408 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
generated by cgit v1.2.3 (git 2.39.1) at 2024-07-03 04:14:19 +0000