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There are two configs, sdram-lpddr3-hynix-2GB.inc and
sdram-lpddr3-samsung-2GB-24EB.inc that use .ddrconfig = 14.
Changing .ddrconfig from 14 to 3 improves performance
especially on contiguous memory accesses. Comparing the .ddrconfig:
- if .ddrconfig = 3,
C RDRR RRRR RRRR RRRR RBBB CCCC CCCC C---
- if .ddrconfig = 14,
C DRBB BRRR RRRR RRRR RRRR CCCC CCCC C---
where
- R: indicates Row bits
- B: indicates Bank bits
- C: indicates Column bits
- D: indicates Chip selects bits
.ddrconfig = 3 has multiple banks switching which improves DDR timing.
BUG=chrome-os-partner:57321
TEST=Boot from fievel and play video
BRANCH=veyron
Change-Id: Ifdcedc28e84429b8b79c7553b38b667631d29c09
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 93882e4f2000d93c9dae5e6d4b2e1f4b7bc9489e
Original-Change-Id: Ic98ebae48609a7604ec678b6bd14dd2b29b669c4
Original-Signed-off-by: ZhengShunQian <zhengsq@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/404691
Original-Commit-Ready: Shunqian Zheng <zhengsq@rock-chips.com>
Original-Tested-by: Shunqian Zheng <zhengsq@rock-chips.com>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/17210
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
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Add the new samsung DDR configs for all veyron except veyron_rialto:
* K4E6E304EB-EGCE, ramid = 0010, 4GB
* K4E8E324EB-EGCF, ramid = 1100, 2GB
BRANCH=veyron
BUG=none
TEST=boot fievel board
Change-Id: I747aa86f8c93174651a28face63b3386e22b23b3
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 5f55462e71bd481eda85af3d582cfe5b9873cc9c
Original-Change-Id: I19123634c994f685683323f7d85cc4d35814e2ab
Original-Signed-off-by: ZhengShunQian <zhengsq@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/345748
Original-Commit-Queue: Ren Kuo <ren.kuo@quantatw.com>
Original-Reviewed-by: Philip Chen <philipchen@chromium.org>
Original-(cherry-pick from cc990f27024255a326fd9fa9644deb28b01a31a7)
Original-Reviewed-on: https://chromium-review.googlesource.com/404690
Original-Commit-Ready: Shunqian Zheng <zhengsq@rock-chips.com>
Original-Tested-by: Shunqian Zheng <zhengsq@rock-chips.com>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/17209
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
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Provide a default value of 0 in drivers/spi as there weren't
default values aside from specific mainboards and arch/x86.
Remove any default 0 values while noting to keep the option's
default to 0.
BUG=chrome-os-partner:56151
Change-Id: If9ef585e011a46b5cd152a03e41d545b36355a61
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16192
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Martin Roth <martinroth@google.com>
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Change-Id: I7930d5cded290f2605d0c92a9c465a3f0c1291a2
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/15974
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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1. Currenty, boot reason is being added to elog only for some
ARM32/ARM64 platforms. Change this so that boot reason is logged by
default in elog for all devices which have CHROMEOS selected.
2. Add a new option to select ELOG_WATCHDOG_RESET for the devices that
want to add details about watchdog reset in elog. This requires a
special region WATCHDOG to be present in the memlayout.
3. Remove calls to elog add boot reason and watchdog reset from
mainboards.
BUG=chrome-os-partner:55639
Change-Id: I91ff5b158cfd2a0749e7fefc498d8659f7e6aa91
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15897
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
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VBOOT_VERIFY_FIRMWARE should be independent of CHROMEOS. This allows use
of verified boot library without having to stick to CHROMEOS.
BUG=chrome-os-partner:55639
Change-Id: Ia2c328712caedd230ab295b8a613e3c1ed1532d9
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15867
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
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I'm not even sure how this slipped through... looks like it had never
been there in the first place. Anyway, on ARM exceptions should always
be reinitialized in all stages to make sure the handlers are still
around (especially in an OVERLAP_VERSTAGE_ROMSTAGE board like this one).
Change-Id: Ic74ea1448d63b363f2ed59d9e2529971b3d32d9a
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/15099
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Update all of the license headers to make sure they are compliant
with coreboot's license header policy.
Change-Id: Ied67c5079a7f49594edb39caf61fe7f386c3f80d
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/14323
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Change the existing chromeos.fmd files and the dts-to-fmd script to mark
RW_LEGACY as CBFS, so it's properly "formatted".
BUG=chromium:595715
BRANCH=none
TEST=none
Change-Id: I76de26032ea8da0c7755a76a01e7bea9cfaebe23
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 717a00c459906fa87f61314ea4541c31b50539f4
Original-Change-Id: I4b037b60d10be3da824c6baecabfd244eec2cdac
Original-Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/336403
Original-Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Original-Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/14240
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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A long time ago many Chrome OS boards had pages full of duplicated
boilerplate code for the fill_lb_gpios() function, and we spent a lot of
time bikeshedding a proper solution that passes a table of lb_gpio
structs which can be concisely written with a static struct initializer
in http://crosreview.com/234648. Unfortunately we never really finished
that patch and in the mean time a different solution using the
fill_lb_gpio() helper got standardized onto most boards.
Still, that solution is not quite as clean and concise as the one we had
already designed, and it also wasn't applied consistently to all recent
boards (causing more boards with bad code to get added afterwards). This
patch switches all boards newer than Link to the better solution and
also adds some nicer debug output for the GPIOs while I'm there.
If more boards need to be converted from fill_lb_gpio() to this model
later (e.g. from a branch), it's quite easy to do with:
s/fill_lb_gpio(gpio++,\n\?\s*\([^,]*\),\n\?\s*\([^,]*\),\n\?\s*\([^,]*\),\n\?\s*\([^,]*\));/\t{\1, \2, \4, \3},/
Based on a patch by Furquan Shaikh <furquan@google.com>.
BUG=None
BRANCH=None
TEST=Booted on Oak. Ran abuild -x.
Change-Id: I449974d1c75c8ed187f5e10935495b2f03725811
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/14226
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
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The lint script didn't catch that these mainboard directories didn't
have board_info files.
Add all missing board_info.txt files
Change-Id: Ib1d61a3c04e91b22480527885faf60c22093d98a
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/14117
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
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This makes the test IDs the default, taken from depthcharge
master (board/*/fmap.dts, hwid property).
Change-Id: I25793962ac16f451f204dbba6ede6a64c847cfd5
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/13634
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins)
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This is a follow-up to CL:320623 to make veyron DRAM configs
uniform (except for Rialto).
As discussed in chrome-os-partner:43626, the mr[3] value and ODT
are set diffently for Mickey, thus the .inc files for other boards
have mr[3] = 1 and ODT disabled.
BUG=none
BRANCH=veyron
TEST=compile tested for veyron
Change-Id: I61798cfef779b0a3a510fd354ab53ffc63ca6c95
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 3b7cea6331bcec8aba09a204060e093d3dd732cb
Original-Signed-off-by: David Hendricks <dhendrix@chromium.org>
Original-Change-Id: Iacf821645a2dcceaed1c1c42e3e1b1c312b31eab
Original-Reviewed-on: https://chromium-review.googlesource.com/321870
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/13109
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
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These are generated from depthcharge's board/*/fmap.dts using the
dts-to-fmd.sh script.
One special case is google/veyron's chromeos.fmd, which is used for a
larger set of boards - no problem since the converted fmd was the same
for all of them.
Set aside 128K for the bootblock on non-x86 systems (where the COREBOOT
region ends up at the beginning of flash). This becomes necessary
because we're working without a real cbfs master header (exists for
transition only), which carved out the space for the offset.
Change-Id: Ieeb33702d3e58e07e958523533f83da97237ecf1
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/12715
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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This continues what was done in commit a73b93157f2
(tree: drop last paragraph of GPL copyright header)
Change-Id: Ifb8d2d13f7787657445817bdde8dc15df375e173
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12914
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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These platforms needed to be adjusted to fix various Kconfig warnings.
Both platforms needed MAINBOARD_HAS_NATIVE_VGA_INIT because they're setting
MAINBOARD_DO_NATIVE_VGA_INIT.
veyron_emile needed a few symbols that depend on CHROMEOS to be moved
into a new config CHROMEOS section. This matches the other CHROMEOS
platforms.
veyron_danger needed to select MAINBOARD_HAS_CHROMEOS before the
CHROMEOS symbol was set.
Change-Id: I8c7f594ba572a02513a68095c16314006fb4e379
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: http://review.coreboot.org/12462
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
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Emile has a on board ethernet.
BUG=chrome-os-partner:47465
TEST=vpd -s ethernet_mac0=001122334455
build and check the MAC address
Change-Id: I90ed0ed1253c804568fcdd3dd212bb062a48c836
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 99b275c594196de0811f68380e66c226d2649927
Original-Change-Id: I1690a1f39090c57c64d4965092c80eef9070babf
Original-Signed-off-by: ZhengShunQian <zhengsq@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/311900
Original-Commit-Ready: Shunqian Zheng <zhengsq@rock-chips.com>
Original-Tested-by: Shunqian Zheng <zhengsq@rock-chips.com>
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/12452
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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o. Make some gpio changes base on Emile spec.
o. Init sdmmc function.
o. Revert cpu freq reducing in recovery mode since Emile
have more effective thermal than Mickey.
o. Revert the changes of lpddr3-samsung-2GB config.
BUG=chrome-os-partner:46658
TEST=build and boot on Emile
BRANCH=veyron
Change-Id: Ibdc2ce511c8e215c202e2067d79f4c60cdfca738
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 39e5436c8aa3353af77f62e548f48d19dc722999
Original-Change-Id: Ib2c78c9b5e3ac6620ab1772879a7ea0f7007f96e
Original-Signed-off-by: ZhengShunQian <zhengsq@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/307651
Original-Commit-Ready: Shunqian Zheng <zhengsq@rock-chips.com>
Original-Tested-by: Shunqian Zheng <zhengsq@rock-chips.com>
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/12396
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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This is a copy of mickey and renamed.
CQ-DEPEND=CL:306967
BUG=chrome-os-partner:46658
TEST=build coreboot
BRANCH=veyron
Change-Id: I9e1232f3f1334ec747a5beb52f214635a7ab08ae
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 9316a9ec27d5799e290add1e5818f4449b680fde
Original-Change-Id: I906de7bbc8b8e110e0774c14ec636a327230b325
Original-Signed-off-by: ZhengShunQian <zhengsq@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/307620
Original-Commit-Ready: David Hendricks <dhendrix@chromium.org>
Original-Tested-by: David Hendricks <dhendrix@chromium.org>
Original-Tested-by: Shunqian Zheng <zhengsq@rock-chips.com>
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/12394
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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