| Age | Commit message (Collapse) | Author |
|---|
|
This patch removes a lot of code duplication between the virtually
identical Veyron Chromebook variants by merging the code into a single
directory and handling the different names solely within Kconfig. This
also allows us to easily add all the other Chromebook variants that have
only been kept in Google's firmware branch to avoid cluttering coreboot
too much, making it possible to build these boards with upstream
coreboot out of the box.
The only effective change this will have on the affected boards is
removing quirks for early board revisions (since revision numbers differ
between variants). Since all those quirks concerned early pre-MP
revisions, I doubt this will bother anyone (and the old code is still
available through the Google firmware branch if anyone needs it). It
will also expand a recent fix in Jerry that increased an LCD power-on
delay to make it compatible with another kind of panel to all boards,
which is probably not a bad idea anyway.
Leaving all non-Chromebook boards as they are for now since they often
contain more extensive differences.
BRANCH=None
BUG=None
TEST=Booted Jerry.
Change-Id: I4bd590429b9539a91f837459a804888904cd6f2d
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 10049a59a34ef45ca1458c1549f708b5f83e2ef9
Original-Change-Id: I6a8c813e58fe60d83a0b783141ffed520e197b3c
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/296053
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11555
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
We retroactively decided to use the variant name "pinky" for the Rk3288
board we're currently bringing up, and retcon the unadorned "veyron"
name to refer to the Rockchip evaluation board. Since we currently have
no interest to maintain coreboot support for that board in our tree,
let's rename everything to "veyron_pinky" and forget about "veyron".
CQ-DEPEND=CL:217592
BUG=chrome-os-partner:30167
TEST='emerge-veyron libpayload coreboot' fails but
'emerge-veyron_pinky libpayload coreboot' succeeds.
Change-Id: I88bf5cc2da7c2f969ea184b5f12affaa94045a06
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: aa8ec24b63d11798fec1993091b113a0c0938c7a
Original-Change-Id: I366391efc8e0a7c610584b50cea331a0164da6f3
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/217674
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/8869
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
Supports DDR3 and LPDDR3.Supports dual channel.ddr max freq is 533mhz.
ddr timing config file in src\mainboard\google\veyron\sdram_inf
Remove dpll init in rk clk_init(), add rkclk_configure_ddr(unsigned int hz).
BUG=chrome-os-partner:29778
TEST=Build coreboot
Change-Id: I429eb0b8c365c6285fb6cfef008b41776cc9c2d9
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 52838c68fe6963285c974af5dc5837e819efc321
Original-Change-Id: I6ddfe30b8585002b45060fe998c9238cbb611c05
Original-Signed-off-by: jinkun.hong <jinkun.hong@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/209465
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Commit-Queue: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/8865
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
|
