aboutsummaryrefslogtreecommitdiff
path: root/src/mainboard/google/veyron/sdram_inf/sdram-lpddr3-hynix-2GB.inc
AgeCommit message (Collapse)Author
2016-11-03google/veyron*: change .ddrconfig from 14 to 3ZhengShunQian
There are two configs, sdram-lpddr3-hynix-2GB.inc and sdram-lpddr3-samsung-2GB-24EB.inc that use .ddrconfig = 14. Changing .ddrconfig from 14 to 3 improves performance especially on contiguous memory accesses. Comparing the .ddrconfig: - if .ddrconfig = 3, C RDRR RRRR RRRR RRRR RBBB CCCC CCCC C--- - if .ddrconfig = 14, C DRBB BRRR RRRR RRRR RRRR CCCC CCCC C--- where - R: indicates Row bits - B: indicates Bank bits - C: indicates Column bits - D: indicates Chip selects bits .ddrconfig = 3 has multiple banks switching which improves DDR timing. BUG=chrome-os-partner:57321 TEST=Boot from fievel and play video BRANCH=veyron Change-Id: Ifdcedc28e84429b8b79c7553b38b667631d29c09 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 93882e4f2000d93c9dae5e6d4b2e1f4b7bc9489e Original-Change-Id: Ic98ebae48609a7604ec678b6bd14dd2b29b669c4 Original-Signed-off-by: ZhengShunQian <zhengsq@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/404691 Original-Commit-Ready: Shunqian Zheng <zhengsq@rock-chips.com> Original-Tested-by: Shunqian Zheng <zhengsq@rock-chips.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/17210 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2015-09-08veyron: Unify identical mainboardsJulius Werner
This patch removes a lot of code duplication between the virtually identical Veyron Chromebook variants by merging the code into a single directory and handling the different names solely within Kconfig. This also allows us to easily add all the other Chromebook variants that have only been kept in Google's firmware branch to avoid cluttering coreboot too much, making it possible to build these boards with upstream coreboot out of the box. The only effective change this will have on the affected boards is removing quirks for early board revisions (since revision numbers differ between variants). Since all those quirks concerned early pre-MP revisions, I doubt this will bother anyone (and the old code is still available through the Google firmware branch if anyone needs it). It will also expand a recent fix in Jerry that increased an LCD power-on delay to make it compatible with another kind of panel to all boards, which is probably not a bad idea anyway. Leaving all non-Chromebook boards as they are for now since they often contain more extensive differences. BRANCH=None BUG=None TEST=Booted Jerry. Change-Id: I4bd590429b9539a91f837459a804888904cd6f2d Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 10049a59a34ef45ca1458c1549f708b5f83e2ef9 Original-Change-Id: I6a8c813e58fe60d83a0b783141ffed520e197b3c Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/296053 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11555 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>