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path: root/src/mainboard/google/veyron/bootblock.c
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2016-08-18Kconfig: rename BOOT_MEDIA_SPI_BUS to BOOT_DEVICE_SPI_FLASH_BUSAaron Durbin
Provide a default value of 0 in drivers/spi as there weren't default values aside from specific mainboards and arch/x86. Remove any default 0 values while noting to keep the option's default to 0. BUG=chrome-os-partner:56151 Change-Id: If9ef585e011a46b5cd152a03e41d545b36355a61 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16192 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Martin Roth <martinroth@google.com>
2015-10-31tree: drop last paragraph of GPL copyright headerPatrick Georgi
It encourages users from writing to the FSF without giving an address. Linux also prefers to drop that and their checkpatch.pl (that we imported) looks out for that. This is the result of util/scripts/no-fsf-addresses.sh with no further editing. Change-Id: Ie96faea295fe001911d77dbc51e9a6789558fbd6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/11888 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-09-08rk3288: Allow board-specific APLL (CPU clock) settingsDavid Hendricks
This changes the API to rkclk_configure_cpu() such that we can pass in the desired APLL frequency in each veyron board's bootblock.c. Devices with a constrainted form facter (rialto and possibly mickey) will use this to run firmware at a slower speed to mitigate risk of thermal issues (due to the RK808, not the RK3288). BUG=chrome-os-partner:42054 BRANCH=none TEST=amstan says rialto is noticably cooler (and slower) Change-Id: I28b332e1d484bd009599944cd9f5cf633ea468dd Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: d10af5e18b4131a00f202272e405bd22eab4caeb Original-Change-Id: I960cb6ff512c058e72032aa2cbadedde97510631 Original-Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/297190 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/11582 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-09-08veyron: Unify identical mainboardsJulius Werner
This patch removes a lot of code duplication between the virtually identical Veyron Chromebook variants by merging the code into a single directory and handling the different names solely within Kconfig. This also allows us to easily add all the other Chromebook variants that have only been kept in Google's firmware branch to avoid cluttering coreboot too much, making it possible to build these boards with upstream coreboot out of the box. The only effective change this will have on the affected boards is removing quirks for early board revisions (since revision numbers differ between variants). Since all those quirks concerned early pre-MP revisions, I doubt this will bother anyone (and the old code is still available through the Google firmware branch if anyone needs it). It will also expand a recent fix in Jerry that increased an LCD power-on delay to make it compatible with another kind of panel to all boards, which is probably not a bad idea anyway. Leaving all non-Chromebook boards as they are for now since they often contain more extensive differences. BRANCH=None BUG=None TEST=Booted Jerry. Change-Id: I4bd590429b9539a91f837459a804888904cd6f2d Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 10049a59a34ef45ca1458c1549f708b5f83e2ef9 Original-Change-Id: I6a8c813e58fe60d83a0b783141ffed520e197b3c Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/296053 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11555 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>