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path: root/src/mainboard/google/urara/bootblock.c
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2015-12-31imgtec/pistachio: disable default RPU gate register valuesIonela Voinescu
The RPU Clock register defaults to on for all clocks. This is modified to OFF, and the MIPS clock control modified to ON, by default. This is because the linux kernel will manage the clocks at all times, but the RPU can only disable clocks if the WIFI module has been loaded. Change-Id: I155fb37afd585ca3436a77b97c99ca6e582cbb4f Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Reviewed-on: https://review.coreboot.org/12773 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-27mainboard/google/urara: change SYS PLL to 700MHzIonela Voinescu
This requires changes the interface that sets up the system PLL to support a given reference devider value and given feedback value. Also, this requires a change in the dividers used for UART, USB, I2C setup. Change-Id: I98cf7c655dbb3e95b8fcee3c7f468122021c70b5 Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Reviewed-on: https://review.coreboot.org/12765 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-10-31tree: drop last paragraph of GPL copyright headerPatrick Georgi
It encourages users from writing to the FSF without giving an address. Linux also prefers to drop that and their checkpatch.pl (that we imported) looks out for that. This is the result of util/scripts/no-fsf-addresses.sh with no further editing. Change-Id: Ie96faea295fe001911d77dbc51e9a6789558fbd6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/11888 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-05-21Remove address from GPLv2 headersPatrick Georgi
As per discussion with lawyers[tm], it's not a good idea to shorten the license header too much - not for legal reasons but because there are tools that look for them, and giving them a standard pattern simplifies things. However, we got confirmation that we don't have to update every file ever added to coreboot whenever the FSF gets a new lease, but can drop the address instead. util/kconfig is excluded because that's imported code that we may want to synchronize every now and then. $ find * -type f -exec sed -i "s:Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, *MA[, ]*02110-1301[, ]*USA:Foundation, Inc.:" {} + $ find * -type f -exec sed -i "s:Foundation, Inc., 51 Franklin Street, Suite 500, Boston, MA 02110-1335, USA:Foundation, Inc.:" {} + $ find * -type f -exec sed -i "s:Foundation, Inc., 59 Temple Place[-, ]*Suite 330, Boston, MA *02111-1307[, ]*USA:Foundation, Inc.:" {} + $ find * -type f -exec sed -i "s:Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.:Foundation, Inc.:" {} + $ find * -type f -a \! -name \*.patch \ -a \! -name \*_shipped \ -a \! -name LICENSE_GPL \ -a \! -name LGPL.txt \ -a \! -name COPYING \ -a \! -name DISCLAIMER \ -exec sed -i "/Foundation, Inc./ N;s:Foundation, Inc.* USA\.* *:Foundation, Inc. :;s:Foundation, Inc. $:Foundation, Inc.:" {} + Change-Id: Icc968a5a5f3a5df8d32b940f9cdb35350654bef9 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/9233 Tested-by: build bot (Jenkins) Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
2015-04-22google/urara: use board ID information to set up hardwareIonela Voinescu
The hardware initialization is now split in basic initialization (MIPS and system PLL, system clock, SPIM, UART), and initialization of other hardware blocks (USB, I2C, ETH). The second part uses board ID information to select setup that is board specific (currently only I2C interface is selected through board ID). BRANCH=none BUG=chrome-os-partner:37593 TEST=tested on bring up board for both Urara and Concerto; to simulate the use of Concerto (I2C3) DIP SW17 was set to 0. it works with default settings on Urara Change-Id: Ic5bbf28ab42545a4fb2aa6fd30592a02ecc15cb5 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: f2b3db2e7f9fa898214f974ca34ea427196d2e4e Original-Change-Id: Iac9a082ad84444af1d9d9785a2d0cc3205140d15 Original-Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Original-Reviewed-on: https://chromium-review.googlesource.com/257401 Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Original-Commit-Queue: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: http://review.coreboot.org/9888 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-21urara: I2C clock and MFIO setup function for all interfacesIonela Voinescu
The I2C MFIO setup function now supports all interfaces. Also, the API for the clock setup function changed to support all interfaces. BUG=chrome-os-partner:31438 TEST=tested on Pistachio bring up board; all I2C interfaces were tested with the TPM and they all work properly. BRANCH=none Change-Id: I6dfd1c4647335878402cabb2ae512d6e3737a433 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: f8a7ffb54e3f5092c9844b9b502949d3cfc053d1 Original-Change-Id: Ibd67c07acf3d1d9c594faa8ced5ab56d9abb2e40 Original-Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Original-Reviewed-on: https://chromium-review.googlesource.com/256362 Original-Reviewed-by: Chris Lane <chris.lane@frontier-silicon.com> Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/9840 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-21pistachio: add clock setup for all I2C interfacesIonela Voinescu
BUG=chrome-os-partner:31438 TEST=tested on Pistachio bring up board; all I2C interfaces were tested with the TPM and they all work properly. BRANCH=none Change-Id: I02202585140beb818212c02800f6b7e4966a922a Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 33b2adecc4939ac73fffba47adf1c8306a888b8d Original-Change-Id: Ida7eaa72d4d6e6b034319086410de5baa63788bc Original-Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Original-Reviewed-on: https://chromium-review.googlesource.com/256361 Original-Reviewed-by: Chris Lane <chris.lane@frontier-silicon.com> Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/9839 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-14urara: increase drive strength for SPIM1 MFIOsIonela Voinescu
This change is made only to make sure there is a good signal strength on the SPIM lines. BUG=chrome-os-partner:31438 TEST=tested on Pistachio bring up board; works properly BRANCH=none Change-Id: I5b9427b14a407746fb5b707fa3b07a1a6774bfb1 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: e9d953283a5b43bf967128ca73db0e90c2df32df Original-Change-Id: Ia589134cf0557613697d49fb0bdb1848af66f0e8 Original-Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Original-Reviewed-on: https://chromium-review.googlesource.com/249732 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/9675 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-14urara: setup I2C0 clock and MFIOsIonela Voinescu
BUG=chrome-os-partner:31438 TEST=tested on Pistachio bring up board; works properly BRANCH=none Change-Id: Ic805311d3aaf40da601c88cd05a73254088374bd Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: ad9427c069ed34ab91e93df59ec3361499b54982 Original-Change-Id: If8e142273afd2d591a975f4e7e34aa73e8d71b0c Original-Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Original-Reviewed-on: https://chromium-review.googlesource.com/250451 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/9674 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-14urara: Reduce MIPS PLL jitterIonela Voinescu
The current MIPS PLL is configured in such a way that there is excessive jitter. Correct this by applying new PLL settings. The resultant frequency is 546MHz instead of 550MHz. BUG=chrome-os-partner:31438 TEST=tested on Pistachio bring up board as part of the JTAG loading script; BRANCH=none Change-Id: Ica1bfff29e01819b86cd2bb8b18d8adc9dfa3260 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 0c04354b49b73d234492521d81b6600d487175b0 Original-Change-Id: I28b41b1e82dbdf9da21bf0ab74f9722cdad923f1 Original-Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Original-Reviewed-on: https://chromium-review.googlesource.com/245620 Original-Reviewed-by: James Hartley <james.hartley@imgtec.com> Original-Reviewed-by: Andrew Bresticker <abrestic@chromium.org> Reviewed-on: http://review.coreboot.org/9671 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-14urara: add clock setup for MIPS CPU, ROM and EthernetIonela Voinescu
BUG=chrome-os-partner:31438 TEST=tested on Pistachio bring up board; works properly BRANCH=none Change-Id: Ie386d6af9eeba7a72b1b88d515e6cb1821569c6b Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: d4b8d8b6f965296f9ecf62da8e5f383c3667b077 Original-Change-Id: I9eb464340b0475ae735ba5573ab0841dac0d74eb Original-Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Original-Reviewed-on: https://chromium-review.googlesource.com/243215 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/9669 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-14urara: remove call to printk before UART is initializedIonela Voinescu
BUG=chrome-os-partner:31438 TEST=tested in Pistachio bring up board; previous delay at the beginning of bootblock is fixed. BRANCH=none Change-Id: I30335677c96bfd651bc49e36b562c48588009d67 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 3d1eb117644af1323dd940e0a82a2ef44025d5b9 Original-Change-Id: I122df1f985163836bb2ddd027ef6ab2ce265d5dd Original-Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Original-Reviewed-on: https://chromium-review.googlesource.com/243223 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/9668 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-14urara: Configure clocks and MFIOsIonela Voinescu
Set elements: - UART1 clock dividers and MFIOs - SPIM1 clock dividers and MFIOs - USB clock dividers - System clock divider - System PLL - MIPS CPU PLL BUG=chrome-os-partner:31438 TEST=tested on Pisachio bring up board; UART, SPI NOR, SPI NAND, and USB have proper functionality. BRANCH=none Change-Id: Ib01186a652fd59295a4cafc3ca99b94aa9564f74 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 65e68d82f34bb40ef3cfb397ecf5df0c83201151 Original-Change-Id: Ia2c31bbbfc020dc4fd71c72b877414adfdfc42a8 Original-Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Original-Reviewed-on: https://chromium-review.googlesource.com/241423 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/9662 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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