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2015-03-28storm: fix SW_RESET signal polarityVadim Bendebury
The actual level required to take the ethernet switch out of reset is low, not high. BUG=chrome-os-partner:31780 TEST=with this patch applied, when proto0.2 boots, the ethernet switch's LED blink once, as was the case with proto0. Change-Id: If4004ac5c2dc837270d4cb840d96ce92021d231e Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 9fa69d22de901cd0843948de0f95a66a2aa99353 Original-Change-Id: I81eeb73b85cf113709b6d4ac3aa7639a40fa6719 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/217416 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/9121 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-28storm: deassert SW_RESET signal at startupVadim Bendebury
The proto0.2 hardware connects gpio26 (sw reset) to the ethernet switch reset pit. The output stays low (or high-z) after power up, which holds the switch in reset. Deassert the signal at startup on hardware rev 1 and later. BUG=chrome-os-partner:31780 TEST=with this patch applied, when proto0.2 boots, the ethernet switch's LED blink once, as was the case with proto0. Change-Id: I4c5a0cc499563a33aa7d29be7767d0ec5d93c20f Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 6788962172c6e29e193fa3e85ca79cb83a96e154 Original-Change-Id: I81b3dccb1d1d43c5c1e6dcb5400af8eed6dee870 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/217087 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/9120 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-28storm: make sure board ID is calculated only onceVadim Bendebury
Figuring out board_id on storm requires reading tertiary gpios, which takes time. Let's calculate it once and reuse it when necessary. BUG=none TEST=verified board ID reported as 0 and 1 on proto0 and proto0.2 respectively. Change-Id: I69f6afa3de8a175a1d723e95902efd15607e68b7 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 080c839c1c0c1b5e389b2382144ef67535bb4ff1 Original-Change-Id: I4e237077d1d9a96daebba462cd00f3f40be14518 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/217086 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/9119 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-28storm: reset TPM properly on proto0Vadim Bendebury
The proto0 storm hardware has the TPM reset line wired to the SOC GPIO22 pin instead of the system reset. This causes all kind of TPM behavior problems and requires frequent power cycles. Adding explicit TPM reset makes all those problems go away. BUG=chrome-os-partner:30705, chrome-os-partner:30829 TEST=tried resetting proto0 at different moments during boot up - the TPM does not fail anymore. Change-Id: Idfa16e6e868336f38861edeb75703fff3f35172c Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: d5e07815c227089b7f266ba5329812bf309b87e6 Original-Change-Id: Ia877fcd9efaf3ba12c8fe8c2958bd81c4bf22799 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/211497 Original-Reviewed-by: Trevor Bourget <tbourget@codeaurora.org> Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/9118 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-28storm: supply vboot GPIO settings in coreboot tableVadim Bendebury
Storm provides three real and two fake gpios. To keep things simple, define them all as active low and provide appropriate values for the fake ones. BUG=chrome-os-partner:30705 TEST=with the appropriate depthcharge change booted proto0, observed appropriate behavior following the dev switch setting Change-Id: I248b90ee06d226a223b6fc0993f209acdd58c77d Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: d48d1dcc88df0c1bd4c50f14dd2e7cd1dd4fba5d Original-Change-Id: Icb7fb55949fa97ead9d19f0da76392ee63bbb5b8 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/210922 Reviewed-on: http://review.coreboot.org/9117 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-26fix how to interpret board id read from gpiosDaisuke Nojiri
nyan blaze fails to boot because tristates of the board id are interpreted in the reverse order. this change fixes it. BUG=none TEST=Booted Blaze to Linux. Built firmware for Storm. Branch=none Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Change-Id: I4ff8a15cf62869cea22931b5255c3a408a778ed2 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 3f59b13d615a8985edf2029d89af05e95aefad33 Original-Change-Id: I6d81092becb60d12e1cd2a92fc2c261da42c60f5 Original-Reviewed-on: https://chromium-review.googlesource.com/211700 Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Original-Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: http://review.coreboot.org/8980 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-26Restore name of the function reading tertiary GPIO statesVadim Bendebury
The name was changed due to review comments misunderstanding, it should be restored to properly convey what the function does. BUG=chrome-os-partner:30489 TEST=verified that Storm still properly reports board ID Change-Id: Iba33cf837e137424bfac970b0c9764d26786be9c Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: c0fff28c6ebf255cb9cf9dfe4c961d7a25bb13ff Original-Change-Id: I4bd63f29afbfaf9f3e3e78602564eb52f63cc487 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/211413 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/8979 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-23Enable publishing of board ID where supportedVadim Bendebury
These boards are supposed to be able to determine the board ID at run time based on GPIO settings. BUG=chrome-os-partner:30489 TEST=verified that all boards build. Checked that storm proto0 reports board ID of 0 on the console Original-Change-Id: Iadd758a799d69e1e34579d7d495378856b64c45b Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/210119 (cherry picked from commit f4d41ddf906c1bf0d10da38011998fa0a630c332) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I0d5f94d3428157a70f0a9d711b57432e3f796733 Reviewed-on: http://review.coreboot.org/8722 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-03-23storm: Add board ID calculation functionVadim Bendebury
storm uses three GPIOs in tertiary mode, such that proto0 returns value of 8 when the GPIOs are interpreted as a single tertiary number. Adjust the calculated value to return board ID of 0 on proto0, and monotonously incrementing values on newer boards. BUG=chrome-os-partner:30489 TEST=when enabled, the board ID value of zero is reported on the console. Original-Change-Id: I2ff8fd5cbc8d568877b6f8bf220e146893f1e4be Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/210118 (cherry picked from commit 6ba24f31583933f02be111c8767ae9df56537011) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I35ee218df35a0924d4bb8fcbc6c875450a609f24 Reviewed-on: http://review.coreboot.org/8721 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-03-23ipq806x: implement GPIO APIVadim Bendebury
Add implementation of the GPIO API defined in src/include/gpiolib.h. Also, clean up the GPIO driver, make it use pointers instead of integers for register address. This requires a touch in the SPI driver, where the CS GPIO is toggled and in the board function where it enables USB interface. BUG=chrome-os-partner:30489 TEST=tested with the following patches, observed proto0 properly read the board ID. Original-Change-Id: I0962947c6bb32a854ca300752d259a48e9e7b4eb Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/210115 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> (cherry picked from commit e951f735001509d135cc61530ed0eecb5fc31a85) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I8a612dce000931835054086c1b02ebfc43dc57d2 Reviewed-on: http://review.coreboot.org/8718 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-03-20romstages: use common run_ramstage()Aaron Durbin
Instead of sprinkling the cbfs calls around (as well as getting return values incorrect) use the common run_ramstage() to perform the necessary work to load and run ramstage. Change-Id: I37b1e94be36ef7a43efe65b2db110742fa105169 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/8710 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-05storm: Provide ability to build ap148 variantVadim Bendebury
With BOARD_VARIANT_AP148 configuration option enabled the image will be built for 512MB DRAM instead of 1024MB and the mainboard_part_number field in the lb_mainboard entry will be set to "AP148" instead of "Storm". BUG=chrome-os-partner:30440 TEST=manual . built and booted both AP148 and proto0 all the way to reading the kernel . verified that the config file includes correct part number and memory size . verified proper machine IDs reportted when starting the kernel Original-Change-Id: Ie609544a460fc991e66e8b95e8d7a3ed5e845f7b Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/207427 Original-Reviewed-by: Trevor Bourget <tbourget@codeaurora.org> Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> (cherry picked from commit a80ab00f27eef9e3aa2f761659d6945d6fce2ef6) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I477e672dc4f48fa9c9893bf0759704501ea07b1a Reviewed-on: http://review.coreboot.org/8590 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: David Hendricks <dhendrix@chromium.org>
2015-01-09storm: Increase DRAM size to 1024MBDavid Hendricks
BUG=chrome-os-partner:29871 BRANCH=storm TEST=builds and boots (sort of) Original-Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Change-Id: I82e1792152d17d689e129c9941e8972221bde366 Original-Reviewed-on: https://chromium-review.googlesource.com/206011 Original-Reviewed-by: Stefan Reinauer <reinauer@chromium.org> (cherry picked from commit 8995fde9bdfb8af8fb86525fd67a61614881f78e) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ice4a5382903b0ab6e085c39d05c46601373080eb Reviewed-on: http://review.coreboot.org/8148 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-01-09storm: USB fixes for proto0Vadim Bendebury
The actual storm device has a single USB interface, which needs to be explicitly turned on using GPIO51. BUG=chrome-os-partner:29871 TEST=verified that depthcharge finds and boots a kernel from USB stick Original-Change-Id: Iaf868812c96e1e3289b9403855c4cc8f87c1e368 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/205329 Original-Reviewed-by: Stefan Reinauer <reinauer@chromium.org> Original-Reviewed-by: Trevor Bourget <tbourget@codeaurora.org> (cherry picked from commit aa22376ffac22309a298dfa844e7f61c97d57d3e) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ic0f34622e61a65a0540c0f3fca26fb057fa85fb7 Reviewed-on: http://review.coreboot.org/8147 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2015-01-04ipq806x: Add USB supportJulius Werner
This patch adds code to initialize the two DWC3 USB host controllers and their associated PHYs to the IPQ806x SoC (closely imitating the existing DWC3 implementation for Exynos5), and uses them to initialize USB on the Storm mainboard. BUG=chrome-os-partner:29375 TEST=Hack up netboot to get around missing SPI flash, load a file over TFTP. Hack a storage read into the storage attach function, dump the data and confirm that it looks right. Enable USB debugging and confirm 3.0 devices get enumerated at SuperSpeed (mostly). Original-Change-Id: Iaf7b96bef994081ca222b7de9d8e8c49751d3f1d Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/202157 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> (cherry picked from commit 6349e7281d5accb1247acb0537a48fa3a5e1bf97) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I749d265d45c6a807a7559bd4df2490a6eb8067af Reviewed-on: http://review.coreboot.org/8056 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-01-03mainboard/storm: setup mmu in storm mainboard_initDeepa Dinamani
enable protection of zero page access, provide for uncached device memory range, and protect against access outside of DRAM except to device registers. BUG=chrome-os-partner:28467 TEST=verified mmu.pagetable.list output: _______address___________|_physical________________|sec|_d_|_size____|_permissions____________________|_glb|_shr|_pageflags______________________| C:00000000--000FFFFF| | | | | | | | | C:00100000--3FFFFFFF| A:00:00100000--3FFFFFFF| ns| 00| 00100000| P:readwrite U:readwrite notexec| yes| no | strongly ordered | C:40000000--428FFFFF| A:00:40000000--428FFFFF| ns| 00| 00100000| P:readwrite U:readwrite exec | yes| no | write-back/no write alloc | C:42900000--43CFFFFF| A:00:42900000--43CFFFFF| ns| 00| 00100000| P:readwrite U:readwrite notexec| yes| no | strongly ordered | C:43D00000--5FFFFFFF| A:00:43D00000--5FFFFFFF| ns| 00| 00100000| P:readwrite U:readwrite exec | yes| no | write-back/no write alloc | Original-Change-Id: If9beb10938841aead5105d662f0aef741995d708 Original-Signed-off-by: Deepa Dinamani <deepad@codeaurora.org> Original-Reviewed-on: https://chromium-review.googlesource.com/200341 Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Original-Commit-Queue: Vadim Bendebury <vbendeb@chromium.org> Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org> (cherry picked from commit 09dd137453d8c6f1b60692b01226498e22f34fb2) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Conflicts: src/mainboard/google/storm/mainboard.c Change-Id: Idff7e3f0bc5903933e9f1b980f595666380696d1 Reviewed-on: http://review.coreboot.org/8010 Reviewed-by: David Hendricks <dhendrix@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-01-03storm: enable early consoleVadim Bendebury
Include the required modules in romstage and enable early console. BUG=chrome-os-partner:27784 TEST=observe the romstage prompt in the console output: coreboot-4.0 romstage Tue May 13 17:08:58 PDT 2014 starting... Original-Change-Id: Ie3853b9afc53246e6eb997f279ccd4dbb08f748b Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/199673 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 6e643d3425ee226b3ebfbf329b35e7017f83d0c3) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ibdc695da634356988b3e551b0a9e4be2e129ccb4 Reviewed-on: http://review.coreboot.org/7997 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-01-03storm/ipq8064: add dynamic CBMEM supportVadim Bendebury
Squashed the correction patch with the original to avoid confusion in coreboot.org review. All what's needed apart from configuring the feature is to provide a function which would report the top of DRAM address. BUG=chrome-os-partner:27784 TEST=manual . with all other patches applied, the image proceeds all the way to trying to download 'fallback/payload'. Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Change-Id: Ifa586964c931976df1dff354066670463f8e9ee3 Original-Reviewed-on: https://chromium-review.googlesource.com/197897 (cherry picked from commit 54fed275fe80dee66d423ddd78a071d3f063464a) Signed-off-by: Marc Jones <marc.jones@se-eng.com> storm: initialize dynamic cbmem properly Dynamic cbmem support has been enabled on storm, but the proper initialization at romstage is missing. Proper DRAM base address definition is also necessary so that CBMEM is placed in the correct address range (presently at the top of DRAM). BUG=chrome-os-partner:27784 TEST=build boot coreboot on ap148, observe the following in the console output: Wrote coreboot table at: 5fffd000, 0xe8 bytes, checksum 44a5 coreboot table: 256 bytes. CBMEM ROOT 0. 5ffff000 00001000 COREBOOT 1. 5fffd000 00002000 Original-Change-Id: I74ccd252ddfdeaa0a5bcc929be72be174f310730 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/199674 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit e2aeb2f4e7f3959d5f5336f42a29909134a7ddb7) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I45f7016dd510fe0e924b63eb85da607c1652af74 Reviewed-on: http://review.coreboot.org/7996 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-01-03storm: ipq8064: enable CBFS SPI wrapperVadim Bendebury
This change forces storm platform to use the common CBFS SPI wrapper, which makes the SOC specific CBFS code unnecessary and requires including SPI controller support in all coreboot stages. BUG=chrome-os-partner:27784 TEST=manual . with this change and the rest of the patches coreboot on AP148 comes up all the way to attempting to boot the payload (reading earlier stages from the SPI flash along the way). Original-Change-Id: Ib468096f8e844deca11909293d90fc327aa99787 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/197932 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> (cherry picked from commit 794418a132b5be5a2c049f28202da3cec7ce478d) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I751c51c91f29da4f54fcfe05e7b9a2e8f956c4f2 Reviewed-on: http://review.coreboot.org/7994 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-12-31ipq8064/storm: UART enable and various fixesVadim Bendebury
The original patch from chromium was a bit of a mishmash. Between that, rebasing and using the coreboot.org UART infrastructure, the patch has changed a bit from the original. It seems reasonable to keep these changes together. - build in the ipq UART and turn on bootblock console - sets LPAE and ROM header address - adds cpd.c to storm The original commit: ipq8064: make UART driver work in bootblock This patch it the last one in the chain adapting the ipq9064 UART driver for use in coreboot. A new config option (CONSOLE_SERIAL_IPQ806X) is being introduced to control inclusion of the driver. The previously introduced uart_wrapper.c is now included in the build to provide the console driver structure used by ramstage. Necessary configuration options are added to allow use of UART in the bootblock. BUG=chrome-os-partner:27784 TEST=with this change the coreboot image on AP148 prints a banner on start up: coreboot-4.0 Wed Apr 23 16:24:51 PDT 2014 starting... Original-Change-Id: I129ee30ba17a5061b30cfee56c135df31eba98b5 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/196663 (cherry picked from commit 42ca8994361327c24e7a611505b21534dd231f30) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I1175e74ed639cdc27a1a677fba65de2dd2b13a91 Reviewed-on: http://review.coreboot.org/7875 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins)
2014-12-30ipq8064: prepare uart driver for use in corebootVadim Bendebury
The IO accessor wrappers are used to allow integer register addresses. A structure defining UART interface configuration is declared and defined. A few long lines are wrapped. Interface functions are renamed to match the wrapper API. cdp.c is edited to fit into coreboot compilation environment, and the only function required by the UART driver if exposed, the rest are compiled out for now. BUG=chrome-os-partner:27784 TEST=after all patches are applied the serial console on AP148 becomes operational. Original-Change-Id: I80c824d085036c0f90c52aad77843e87976dbe49 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/196662 Original-Reviewed-by: Stefan Reinauer <reinauer@chromium.org> (cherry picked from commit 5e9af53a069cd048334a3a28f0a4ce9df7c96992) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I80c824d085036c0f90c52aad77843e87976dbe49 Reviewed-on: http://review.coreboot.org/7874 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-12-01Mark non-executable files non-executablePatrick Georgi
No need to mark Makefiles, C files or devicetrees executable. Change-Id: Ide3a0efc5b14f2cbd7e2a65c541b52491575bb78 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: http://review.coreboot.org/7618 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-11-12Copy u-boot sources as is and modify the tree to still buildVadim Bendebury
This patch brings in ipq806x source files from the vendor's u-boot tree as it was published in the 'cs_banana' release. The following files are being copied: arch/arm/cpu/armv7/ipq/clock.c => src/soc/qualcomm/ipq806x/clock.c arch/arm/cpu/armv7/ipq/gpio.c => src/soc/qualcomm/ipq806x/gpio.c arch/arm/cpu/armv7/ipq/timer.c => src/soc/qualcomm/ipq806x/timer.c arch/arm/include/asm/arch-ipq806x/clock.h => src/soc/qualcomm/ipq806x/clock.h arch/arm/include/asm/arch-ipq806x/gpio.h => src/soc/qualcomm/ipq806x/gpio.h arch/arm/include/asm/arch-ipq806x/gsbi.h => src/soc/qualcomm/ipq806x/gsbi.h arch/arm/include/asm/arch-ipq806x/iomap.h => src/soc/qualcomm/ipq806x/iomap.h arch/arm/include/asm/arch-ipq806x/timer.h src/soc/qualcomm/ipq806x/timer.h arch/arm/include/asm/arch-ipq806x/uart.h => src/soc/qualcomm/ipq806x/uart.h board/qcom/ipq806x_cdp/ipq806x_cdp.c => src/mainboard/google/storm/cdp.c board/qcom/ipq806x_cdp/ipq806x_cdp.h => src/soc/qualcomm/ipq8064/cdp.h drivers/serial/ipq806x_uart.c => src/console/ipq806x_console.c Note that local timer.c gets overwritten with the original version. To prevent a build breakage some shortly to be reverted modifications had to be made to src/soc/qualcomm/ipq806x/Makefile.inc and src/soc/qualcomm/ipq806x/cbfs.c. BRANCH=none BUG=chrome-os-partner:27784 TEST='emerge-storm coreboot' still succeeds Original-Change-Id: I3f50bfbec2e18a3b5d2c640cff353a26f88c98c1 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/193722 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> (cherry picked from commit 3c9c2ede7e97e330cad2c2f3e557cc9bcdaecdcc) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ia7bc66cecfc16f1dd4a9f3cb9840cbe91878adf4 Reviewed-on: http://review.coreboot.org/7263 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-11-12Include IPQ8064 SBLs code in the coreboot bootblockVadim Bendebury
We want the coreboot build produce an image which can be run on the target, even if the remaining parts of the bootprom (recovery path, read-write stages, gbb, etc.) are not available yet. This is achieved by including the Qualcomm SBLs blob in the bootblock. CQ-DEPEND=CL:193518 BRANCH=None BUG=chrome-os-partner:27784 TEST=manual . run the following commands inside chroot to confirm expected image layout (no actual code is executed on the target yet): $ emerge-storm coreboot $ \od -Ax -t x1 -v /build/storm/firmware/coreboot.rom 2>/dev/null | head -1 000000 d1 dc 4b 84 34 10 d7 73 15 00 00 00 ff ff ff ff $ \od -Ax -t x1 -v /build/storm/firmware/coreboot.rom | grep 220000 220000 05 00 00 00 03 00 00 00 00 00 00 00 00 00 01 2a Original-Change-Id: I10e8b81c7bd90e4550a027573ad3a26c38c3808a Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/193540 (cherry picked from commit 64e193974ee448f78e0a5775a440094901590afb) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Idbdbeb9d229eff94a7a94af5dc4844a295458200 Reviewed-on: http://review.coreboot.org/7262 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-10-01storm: Add generic support skeleton for stormFurquan Shaikh
Skeleton for storm mainboard Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://chromium-review.googlesource.com/190724 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Commit-Queue: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit ba371d410768fae169da929a23c40139d26a55d3) Removed 'select ARCH_ARM' and added 'select BOARD_ROMSIZE_KB_1024' to the Kconfig. Change-Id: I55c0ad6a47515ba4124b99a69d5776db2365f06e Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6975 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
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