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2022-04-21tpm: Refactor TPM Kconfig dimensionsJes B. Klinke
Break TPM related Kconfig into the following dimensions: TPM transport support: config CRB_TPM config I2C_TPM config SPI_TPM config MEMORY_MAPPED_TPM (new) TPM brand, not defining any of these is valid, and result in "generic" support: config TPM_ATMEL (new) config TPM_GOOGLE (new) config TPM_GOOGLE_CR50 (new, implies TPM_GOOGLE) config TPM_GOOGLE_TI50 (new to be used later, implies TPM_GOOGLE) What protocol the TPM chip supports: config MAINBOARD_HAS_TPM1 config MAINBOARD_HAS_TPM2 What the user chooses to compile (restricted by the above): config NO_TPM config TPM1 config TPM2 The following Kconfigs will be replaced as indicated: config TPM_CR50 -> TPM_GOOGLE config MAINBOARD_HAS_CRB_TPM -> CRB_TPM config MAINBOARD_HAS_I2C_TPM_ATMEL -> I2C_TPM && TPM_ATMEL config MAINBOARD_HAS_I2C_TPM_CR50 -> I2C_TPM && TPM_GOOGLE config MAINBOARD_HAS_I2C_TPM_GENERIC -> I2C_TPM && !TPM_GOOGLE && !TPM_ATMEL config MAINBOARD_HAS_LPC_TPM -> MEMORY_MAPPED_TPM config MAINBOARD_HAS_SPI_TPM -> SPI_TPM && !TPM_GOOGLE && !TPM_ATMEL config MAINBOARD_HAS_SPI_TPM_CR50 -> SPI_TPM && TPM_GOOGLE Signed-off-by: Jes B. Klinke <jbk@chromium.org> Change-Id: I4656b2b90363b8dfd008dc281ad591862fe2cc9e Reviewed-on: https://review.coreboot.org/c/coreboot/+/63424 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-11-15Reland "vboot_logic: Set VB2_CONTEXT_EC_TRUSTED in verstage_main"Hsuan-ting Chen
This reverts commit adb393bdd6cd6734fa2672bd174aca4588a68016. This relands commit 6260bf712a836762b18d80082505e981e040f4bc. Reason for revert: The original CL did not handle some devices correctly. With the fixes: * commit 36721a4 (mb/google/brya: Add GPIO_IN_RW to all variants' early GPIO tables) * commit 3bfe46c (mb/google/guybrush: Add GPIO EC in RW to early GPIO tables) * commit 3a30cf9 (mb/google/guybrush: Build chromeos.c in verstage This CL also fix the following platforms: * Change to always trusted: cyan. * Add to early GPIO table: dedede, eve, fizz, glados, hatch, octopus, poppy, reef, volteer. * Add to both Makefile and early GPIO table: zork. For mb/intel: * adlrvp: Add support for get_ec_is_trusted(). * glkrvp: Add support for get_ec_is_trusted() with always trusted. * kblrvp: Add support for get_ec_is_trusted() with always trusted. * kunimitsu: Add support for get_ec_is_trusted() and initialize it as early GPIO. * shadowmountain: Add support for get_ec_is_trusted() and initialize it as early GPIO. * tglrvp: Add support for get_ec_is_trusted() with always trusted. For qemu-q35: Add support for get_ec_is_trusted() with always trusted. We could attempt another land. Change-Id: I66b8b99d6e6bf259b18573f9f6010f9254357bf9 Signed-off-by: Hsuan Ting Chen <roccochen@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58253 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-10-15Revert "vboot_logic: Set VB2_CONTEXT_EC_TRUSTED in verstage_main"Hsuan-ting Chen
This reverts commit 6260bf712a836762b18d80082505e981e040f4bc. Reason for revert: This CL did not handle Intel GPIO correctly. We need to add GPIO_EC_IN_RW into early_gpio_table for platforms using Intel SoC. Signed-off-by: Hsuan Ting Chen <roccochen@chromium.org> Change-Id: Iaeb1bf598047160f01e33ad0d9d004cad59e3f75 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57951 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-10-05src/mainboard to src/security: Fix spelling errorsMartin Roth
These issues were found and fixed by codespell, a useful tool for finding spelling errors. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: Ie34003a9fdfe9f3b1b8ec0789aeca8b9435c9c79 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58081 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-09-16vboot_logic: Set VB2_CONTEXT_EC_TRUSTED in verstage_mainHsuan Ting Chen
vboot_reference is introducing a new field (ctx) to store the current boot mode in crrev/c/2944250 (ctx->bootmode), which will be leveraged in both vboot flow and elog_add_boot_reason in coreboot. In current steps of deciding bootmode, a function vb2ex_ec_trusted is required. This function checks gpio EC_IN_RW pin and will return 'trusted' only if EC is not in RW. Therefore, we need to implement similar utilities in coreboot. We will deprecate vb2ex_ec_trusted and use the flag, VB2_CONTEXT_EC_TRUSTED, in vboot, vb2api_fw_phase1 and set that flag in coreboot, verstage_main. Also add a help function get_ec_is_trusted which needed to be implemented per mainboard. BUG=b:177196147, b:181931817 BRANCH=none TEST=Test on trogdor if manual recovery works Signed-off-by: Hsuan Ting Chen <roccochen@chromium.org> Change-Id: I479c8f80e45cc524ba87db4293d19b29bdfa2192 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57048 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-16mb/google: Unify all variants to start with "-> "Martin Roth
All variants originally had been changed to start with an arrow with two spaces following it to line up with the platform name. A number of recent platforms were added only using a single space. This change updates them all to have two spaces so they line up again. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: Iab9e6207fff5a7d2f6d76e5ca33eeaca721a224f Reviewed-on: https://review.coreboot.org/c/coreboot/+/57391 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-09-07mb/google: Add board name comments for each boardMartin Roth
Roughly half the boards had a "title" comment for the board. This adds it for the rest of the boards to make everything consistent. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: Ib941318842136212727f56fc6130381c5c9cd55b Reviewed-on: https://review.coreboot.org/c/coreboot/+/57390 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-07-26mb/*: Specify type of `MAINBOARD_PART_NUMBER` onceAngel Pons
Specify the type of the `MAINBOARD_PART_NUMBER` Kconfig symbol once instead of doing so on each and every mainboard. Change-Id: I3692f9e82fe90af4d0da1d037018a20aa1b45793 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56554 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-26mb/*: Specify type of `MAINBOARD_DIR` onceAngel Pons
Specify the type of the `MAINBOARD_DIR` Kconfig symbol once instead of doing so on each and every mainboard. Change-Id: If1cc538b0c4938dac193699897b690e402b3c1e8 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56553 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-21mb/: Drop the provided name in chip_opsKyösti Mälkki
Little point to replicate a string already provided both as a global Kconfig and global mainboard_part_number. Change-Id: I1fd138c711ebbb37c39b2c8f554b1f2e1a364424 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50719 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: ron minnich <rminnich@gmail.com>
2021-02-15src: use ARRAY_SIZE where possiblePatrick Georgi
Generated with a variant of https://coccinelle.gitlabpages.inria.fr/website/rules/array.cocci Change-Id: I083704fd48faeb6c67bba3367fbcfe554a9f7c66 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50594 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-03src: Remove unused <boardid.h>Elyes HAOUAS
Change-Id: I960870fabde1dacfe52a8a35c253b0bd097d3e10 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50183 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2020-12-31coreboot_table: Convert some CONFIG(CHROMEOS) preprocessorKyösti Mälkki
Change-Id: I1e63a419db92642df6b7956050c39540c2ae11d6 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48781 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-13treewide: Add Kconfig variable MEMLAYOUT_LD_FILEFurquan Shaikh
This change defines a Kconfig variable MEMLAYOUT_LD_FILE which allows SoC/mainboard to provide a linker file for the platform. x86 already provides a default memlayout.ld under src/arch/x86. With this new Kconfig variable, it is possible for the SoC/mainboard code for x86 to provide a custom linker file as well. Makefile.inc is updated for all architectures to use this new Kconfig variable instead of assuming memlayout.ld files under a certain path. All non-x86 boards used memlayout.ld under mainboard directory. However, a lot of these boards were simply including the memlayout from SoC. So, this change also updates these mainboards and SoCs to define the Kconfig as required. BUG=b:155322763 TEST=Verified that abuild with --timeless option results in the same coreboot.rom image for all boards. Change-Id: I6a7f96643ed0519c93967ea2c3bcd881a5d6a4d6 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42292 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-01src: Fix up #-commented SPDX headersAngel Pons
Delete leading empty comment lines. Change-Id: I8e14a0ad1e1e2227e4fb201f5d157f56f289f286 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41838 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-05-18mainboard/*/*/*.cb: Remove leading blank lines from SPDX headerElyes HAOUAS
Change-Id: Ia0dbf7b946d42bda11b904a9caff5a402b553b33 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41359 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-05-18mainboard/*/*/Kconfig*: Remove leading blank lines from SPDX headerElyes HAOUAS
Change-Id: I7089b29e881d74d31477e2df1c5fa043fe353343 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41358 Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-18src: Remove leading blank lines from SPDX headerElyes HAOUAS
Change-Id: I8a207e30a73d10fe67c0474ff11324ae99e2cec6 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41360 Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-11treewide: Remove "this file is part of" linesPatrick Georgi
Stefan thinks they don't add value. Command used: sed -i -e '/file is part of /d' $(git grep "file is part of " |egrep ":( */\*.*\*/\$|#|;#|-- | *\* )" | cut -d: -f1 |grep -v crossgcc |grep -v gcov | grep -v /elf.h |grep -v nvramtool) The exceptions are for: - crossgcc (patch file) - gcov (imported from gcc) - elf.h (imported from GNU's libc) - nvramtool (more complicated header) The removed lines are: - fmt.Fprintln(f, "/* This file is part of the coreboot project. */") -# This file is part of a set of unofficial pre-commit hooks available -/* This file is part of coreboot */ -# This file is part of msrtool. -/* This file is part of msrtool. */ - * This file is part of ncurses, designed to be appended after curses.h.in -/* This file is part of pgtblgen. */ - * This file is part of the coreboot project. - /* This file is part of the coreboot project. */ -# This file is part of the coreboot project. -# This file is part of the coreboot project. -## This file is part of the coreboot project. --- This file is part of the coreboot project. -/* This file is part of the coreboot project */ -/* This file is part of the coreboot project. */ -;## This file is part of the coreboot project. -# This file is part of the coreboot project. It originated in the - * This file is part of the coreinfo project. -## This file is part of the coreinfo project. - * This file is part of the depthcharge project. -/* This file is part of the depthcharge project. */ -/* This file is part of the ectool project. */ - * This file is part of the GNU C Library. - * This file is part of the libpayload project. -## This file is part of the libpayload project. -/* This file is part of the Linux kernel. */ -## This file is part of the superiotool project. -/* This file is part of the superiotool project */ -/* This file is part of uio_usbdebug */ Change-Id: I82d872b3b337388c93d5f5bf704e9ee9e53ab3a9 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41194 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-09src/: Replace GPL boilerplate with SPDX headersPatrick Georgi
Used commands: perl -i -p0e 's|\/\*[\s*]*.*is free software[:;][\s*]*you[\s*]*can[\s*]*redistribute[\s*]*it[\s*]*and\/or[\s*]*modify[\s*]*it[\s*]*under[\s*]*the[\s*]*terms[\s*]*of[\s*]*the[\s*]*GNU[\s*]*General[\s*]*Public[\s*]*License[\s*]*as[\s*]*published[\s*]*by[\s*]*the[\s*]*Free[\s*]*Software[\s*]*Foundation[;,][\s*]*version[\s*]*2[\s*]*of[\s*]*the[\s*]*License.[\s*]*This[\s*]*program[\s*]*is[\s*]*distributed[\s*]*in[\s*]*the[\s*]*hope[\s*]*that[\s*]*it[\s*]*will[\s*]*be[\s*]*useful,[\s*]*but[\s*]*WITHOUT[\s*]*ANY[\s*]*WARRANTY;[\s*]*without[\s*]*even[\s*]*the[\s*]*implied[\s*]*warranty[\s*]*of[\s*]*MERCHANTABILITY[\s*]*or[\s*]*FITNESS[\s*]*FOR[\s*]*A[\s*]*PARTICULAR[\s*]*PURPOSE.[\s*]*See[\s*]*the[\s*]*GNU[\s*]*General[\s*]*Public[\s*]*License[\s*]*for[\s*]*more[\s*]*details.[\s*]*\*\/|/* SPDX-License-Identifier: GPL-2.0-only */|' $(cat filelist) perl -i -p0e 's|\/\*[\s*]*.*is[\s*]*free[\s*]*software[:;][\s*]*you[\s*]*can[\s*]*redistribute[\s*]*it[\s*]*and/or[\s*]*modify[\s*]*it[\s*]*under[\s*]*the[\s*]*terms[\s*]*of[\s*]*the[\s*]*GNU[\s*]*General[\s*]*Public[\s*]*License[\s*]*as[\s*]*published[\s*]*by[\s*]*the[\s*]*Free[\s*]*Software[\s*]*Foundation[;,][\s*]*either[\s*]*version[\s*]*2[\s*]*of[\s*]*the[\s*]*License,[\s*]*or[\s*]*.at[\s*]*your[\s*]*option.[\s*]*any[\s*]*later[\s*]*version.[\s*]*This[\s*]*program[\s*]*is[\s*]*distributed[\s*]*in[\s*]*the[\s*]*hope[\s*]*that[\s*]*it[\s*]*will[\s*]*be[\s*]*useful,[\s*]*but[\s*]*WITHOUT[\s*]*ANY[\s*]*WARRANTY;[\s*]*without[\s*]*even[\s*]*the[\s*]*implied[\s*]*warranty[\s*]*of[\s*]*MERCHANTABILITY[\s*]*or[\s*]*FITNESS[\s*]*FOR[\s*]*A[\s*]*PARTICULAR[\s*]*PURPOSE.[\s*]*See[\s*]*the[\s*]*GNU[\s*]*General[\s*]*Public[\s*]*License[\s*]*for[\s*]*more[\s*]*details.[\s*]*\*\/|/* SPDX-License-Identifier: GPL-2.0-or-later */|' $(cat filelist) perl -i -p0e 's|\/\*[\s*]*.*is[\s*#]*free[\s*#]*software[;:,][\s*#]*you[\s*#]*can[\s*#]*redistribute[\s*#]*it[\s*#]*and/or[\s*#]*modify[\s*#]*it[\s*#]*under[\s*#]*the[\s*#]*terms[\s*#]*of[\s*#]*the[\s*#]*GNU[\s*#]*General[\s*#]*Public[\s*#]*License[\s*#]*as[\s*#]*published[\s*#]*by[\s*#]*the[\s*#]*Free[\s*#]*Software[\s*#]*Foundation[;:,][\s*#]*either[\s*#]*version[\s*#]*3[\s*#]*of[\s*#]*the[\s*#]*License[;:,][\s*#]*or[\s*#]*.at[\s*#]*your[\s*#]*option.[\s*#]*any[\s*#]*later[\s*#]*version.[\s*#]*This[\s*#]*program[\s*#]*is[\s*#]*distributed[\s*#]*in[\s*#]*the[\s*#]*hope[\s*#]*that[\s*#]*it[\s*#]*will[\s*#]*be[\s*#]*useful[;:,][\s*#]*but[\s*#]*WITHOUT[\s*#]*ANY[\s*#]*WARRANTY[;:,][\s*#]*without[\s*#]*even[\s*#]*the[\s*#]*implied[\s*#]*warranty[\s*#]*of[\s*#]*MERCHANTABILITY[\s*#]*or[\s*#]*FITNESS[\s*#]*FOR[\s*#]*A[\s*#]*PARTICULAR[\s*#]*PURPOSE.[\s*#]*See[\s*#]*the[\s*#]*GNU[\s*#]*General[\s*#]*Public[\s*#]*License[\s*#]*for[\s*#]*more[\s*#]*details.[\s*]*\*\/|/* SPDX-License-Identifier: GPL-3.0-or-later */|' $(cat filelist) perl -i -p0e 's|(\#\#*)[\w]*.*is free software[:;][\#\s]*you[\#\s]*can[\#\s]*redistribute[\#\s]*it[\#\s]*and\/or[\#\s]*modify[\#\s]*it[\s\#]*under[\s \#]*the[\s\#]*terms[\s\#]*of[\s\#]*the[\s\#]*GNU[\s\#]*General[\s\#]*Public[\s\#]*License[\s\#]*as[\s\#]*published[\s\#]*by[\s\#]*the[\s\#]*Free[\s\#]*Software[\s\#]*Foundation[;,][\s\#]*version[\s\#]*2[\s\#]*of[\s\#]*the[\s\#]*License.*[\s\#]*This[\s\#]*program[\s\#]*is[\s\#]*distributed[\s\#]*in[\s\#]*the[\s\#]*hope[\s\#]*that[\s\#]*it[\s\#]*will[\#\s]*be[\#\s]*useful,[\#\s]*but[\#\s]*WITHOUT[\#\s]*ANY[\#\s]*WARRANTY;[\#\s]*without[\#\s]*even[\#\s]*the[\#\s]*implied[\#\s]*warranty[\#\s]*of[\#\s]*MERCHANTABILITY[\#\s]*or[\#\s]*FITNESS[\#\s]*FOR[\#\s]*A[\#\s]*PARTICULAR[\#\s]*PURPOSE.[\#\s]*See[\#\s]*the[\#\s]*GNU[\#\s]*General[\#\s]*Public[\#\s]*License[\#\s]*for[\#\s]*more[\#\s]*details.\s(#* *\n)*|\1 SPDX-License-Identifier: GPL-2.0-only\n\n|' $(cat filelist) perl -i -p0e 's|(\#\#*)[\w*]*.*is free software[:;][\s*]*you[\s*]*can[\s*]*redistribute[\s*]*it[\s*]*and\/or[\s*]*modify[\s*]*it[\s*]*under[\s*]*the[\s*]*terms[\s*]*of[\s*]*the[\s*]*GNU[\s*]*General[\s*]*Public[\s*]*License[\s*]*as[\s*]*published[\s*]*by[\s*]*the[\s*]*Free[\s*]*Software[\s*]*Foundation[;,][\s*]*version[\s*]*2[\s*]*of[\s*]*the[\s*]*License.[\s*]*This[\s*]*program[\s*]*is[\s*]*distributed[\s*]*in[\s*]*the[\s*]*hope[\s*]*that[\s*]*it[\s*]*will[\s*]*be[\s*]*useful,[\s*]*but[\s*]*WITHOUT[\s*]*ANY[\s*]*WARRANTY;[\s*]*without[\s*]*even[\s*]*the[\s*]*implied[\s*]*warranty[\s*]*of[\s*]*MERCHANTABILITY[\s*]*or[\s*]*FITNESS[\s*]*FOR[\s*]*A[\s*]*PARTICULAR[\s*]*PURPOSE.[\s*]*See[\s*]*the[\s*]*GNU[\s*]*General[\s*]*Public[\s*]*License[\s*]*for[\s*]*more[\s*]*details.\s(#* *\n)*|\1 SPDX-License-Identifier: GPL-2.0-only\n\n|' $(cat filelist) Change-Id: Ia01908544f4b92a2e06ea621eca548e582728280 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41178 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-23mb/google/smaug: Always add RTC driverPatrick Georgi
The device is always there, the Chromium OS config always enables it, so let's mirror that here for a better out of the box experience. Change-Id: Ic43a314aaed635ae2943df02abc5d163cc3c4ffd Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40658 Reviewed-by: Michael Niewöhner Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-06mb/google/smaug: Use SPDX for GPL-2.0-only filesAngel Pons
Done with sed and God Lines. Only done for C-like code for now. Change-Id: I5e297e7c68d5c2646d1a086ae1a5b64fef7ed730 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40195 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-03-18mainboard/google: Remove copyright noticesPatrick Georgi
They're listed in AUTHORS and often incorrect anyway, for example: - What's a "Copyright $year-present"? - Which incarnation of Google (Inc, LLC, ...) is the current copyright holder? - People sometimes have their editor auto-add themselves to files even though they only deleted stuff - Or they let the editor automatically update the copyright year, because why not? - Who is the copyright holder "The coreboot project Authors"? - Or "Generated Code"? Sidestep all these issues by simply not putting these notices in individual files, let's list all copyright holders in AUTHORS instead and use the git history to deal with the rest. Change-Id: I09cc279b1f75952bb397de2c3f2b299255163685 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39607 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2020-03-07chromeos: stop sharing write protect GPIO with depthchargeJoel Kitching
wpsw_boot is deprecated in favour of wpsw_cur. As such, coreboot no longer needs to share "write protect" GPIO with depthcharge. BUG=b:124141368, chromium:950273 TEST=make clean && make test-abuild BRANCH=none Change-Id: I2fcb7f82aa063fd72928171af5cbef0356ba620c Signed-off-by: Joel Kitching <kitching@google.com> Cq-Depend: chromium:2088434 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39318 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-28mainboard/google: Remove unused include <stdlib.h>Elyes HAOUAS
Change-Id: I9e71474bea61befd61900aff554f32f1bc782a77 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33699 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2019-11-23Kconfig: comply to Linux 5.3's Kconfig language rulesPatrick Georgi
Kconfig became stricter on what it accepts, so accomodate before updating to a new release. Change-Id: I92a9e9bf0d557a7532ba533cd7776c48f2488f91 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37156 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2019-10-27src/mainboard: change "unsigned" to "unsigned int"Martin Roth
Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I46d131f76ec930d2ef0f74e6eaabae067df10754 Reviewed-on: https://review.coreboot.org/c/coreboot/+/36330 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-09-30mb: remove test-only HWIDsHung-Te Lin
The CONFIG_GBB_HWID can be generated automatically now so we can remove the test-only HWIDs set in board config files. BUG=b:140067412 TEST=Built few boards (kukui, cheza, octopus) and checked HWID: futility gbb -g coreboot.rom Change-Id: I4070f09d29c5601dff1587fed8c60714eb2558b7 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35635 Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-13mainboard: remove "recovery" gpio, selectively add "presence" gpio.Matt Delco
The gpio table is only used by depthcharge, and depthcharge rarely has a need for the "recovery" gpio. On a few boards it does use the gpio as a signal for confirming physical presence, so on that boards we'll advertise the board as "presence". All these strings probably should have been #defines to help avoid typos (e.g., the "ec_in_rw" in stout seems questionable since everybody else uses "EC in RW"). Cq-Depend: chromium:1580454 BUG=b:129471321 BRANCH=None TEST=Local compile and flash (with corresponding changes to depthcharge) to 2 systems, one with a "presence" gpio and another without. Confirmed that both systems could enter dev mode. Change-Id: Id6d62d9e48d3e6646cbc1277ea53f0ca95dd849e Signed-off-by: Matt Delco <delco@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32718 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-05-06Fix code that would trip -Wtype-limitsJulius Werner
This patch fixes up all code that would throw a -Wtype-limits warning. This sometimes involves eliminating unnecessary checks, adding a few odd but harmless casts or just pragma'ing out the warning for a whole file -- I tried to find the path of least resistance. I think the overall benefit of the warning outweighs the occasional weirdness. Change-Id: Iacd37eb1fad388d9db7267ceccb03e6dcf1ad0d2 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32537 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-04-11chromeos: clean up "recovery" and "write protect" GPIOsJoel Kitching
The "write protect" GPIO's cached value is never actually read after entering depthcharge. Ensure the value from get_write_protect_state() is being transferred accurately, so that we may read this GPIO value in depthcharge without resampling. The cached value of the "recovery" GPIO is read only on certain boards which have a physical recovery switch. Correct some of the values sent to boards which presumably never read the previously incorrect value. Most of these inaccuracies are from non-inverted values on ACTIVE_LOW GPIOs. BUG=b:124141368, b:124192753, chromium:950273 TEST=make clean && make test-abuild BRANCH=none Change-Id: Ic17a98768703d7098480a9233b752fe5b201bd51 Signed-off-by: Joel Kitching <kitching@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32233 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-04-06src: Use include <delay.h> when appropriateElyes HAOUAS
Change-Id: I23bc0191ca8fcd88364e5c08be7c90195019e399 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32012 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: David Guckian
2019-03-29src: Use include <reset.h> when appropriateElyes HAOUAS
Change-Id: I3b852cae4ef84d257bf1e5486447583bdd16b441 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/29301 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-03-20src: Use 'include <string.h>' when appropriateElyes HAOUAS
Drop 'include <string.h>' when it is not used and add it when it is missing. Also extra lines removed, or added just before local includes. Change-Id: Iccac4dbaa2dd4144fc347af36ecfc9747da3de20 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31966 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-03-08coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)Julius Werner
This patch is a raw application of find src/ -type f | xargs sed -i -e 's/IS_ENABLED\s*(CONFIG_/CONFIG(/g' Change-Id: I6262d6d5c23cabe23c242b4f38d446b74fe16b88 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31774 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-03-05mainboard: Enable PRESERVE flag in all vboot/chromeos FMD filesHung-Te Lin
For Chrome OS (or vboot), The PRESERVE flags should be applied on following sections: RO_PRESERVE, RO_VPD, RW_PRESERVE, RW_ELOG, RW_NVRAM, RW_SMMSTORE, RW_VPD, RO_FSG (b:116326638), SI_GBE (chromium:936768), SI_PDR (chromium:936768) With the new PRESERVE flag, we don't need RO_PRESERVE and RW_PRESERVE in the future. But it's still no harm to use it if there are multiple sections all needing to be preserved. BUG=chromium:936768 TEST=Builds google/eve and google/kukui inside Chrome OS source tree. Also boots successfully on eve and kukui devices. Change-Id: I6664ae3d955001ed14374e2788d400ba5fb9b7f8 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31709 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-03-04device/mmio.h: Add include file for MMIO opsKyösti Mälkki
MMIO operations are arch-agnostic so the include path should not be arch/. Change-Id: I0fd70f5aeca02e98e96b980c3aca0819f5c44b98 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/31691 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-04arch/io.h: Drop unnecessary includeKyösti Mälkki
Change-Id: I91158452680586ac676ea11c8589062880a31f91 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/31692 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-28mb/*/*/Kconfig: Remove useless commentElyes HAOUAS
Change-Id: Ibdff50761a205d936b0ebe067f418be0a2051798 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/29871 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hellsenberg <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: David Guckian Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2018-11-05mainboard: Remove unneeded include <console/console.h>Elyes HAOUAS
Change-Id: Ib3aafcc586b1631a75f214cfd19706108ad8ca93 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29285 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-30src: Add missing include <stdint.h>Elyes HAOUAS
Change-Id: I6a9d71e69ed9230b92f0f330875515a5df29fc06 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29312 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-22reset: Convert individual boards to `board_reset()`Nico Huber
Change-Id: I6182da172ae2f4107a9b5d8190e4b3b10ed2f0b9 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/29048 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-06-04security/tpm: Unify the coreboot TPM software stackPhilipp Deppenwiese
* Remove 2nd software stack in pc80 drivers directory. * Create TSPI interface for common usage. * Refactor TSS / TIS code base. * Add vendor tss (Cr50) directory. * Change kconfig options for TPM to TPM1. * Add user / board configuration with: * MAINBOARD_HAS_*_TPM # * BUS driver * MAINBOARD_HAS_TPM1 or MAINBOARD_HAS_TPM2 * Add kconfig TPM user selection (e.g. pluggable TPMs) * Fix existing headers and function calls. * Fix vboot for interface usage and antirollback mode. Change-Id: I7ec277e82a3c20c62a0548a1a2b013e6ce8f5b3f Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: https://review.coreboot.org/24903 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-05-08mb/google: Get rid of device_tElyes HAOUAS
Use of device_t has been abandoned in ramstage. Change-Id: I8e549e4222ae2ed6b9c46f81c5b5253e8b227ee8 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26086 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-02-22mainboard/google: Disable big, pit, and ryu ec buildsMartin Roth
The EC builds for nyan_big, peach_pit, and smaug (ryu) have been removed from the latest EC codebase, so don't try to build them by default anymore. Change-Id: I53901b32753c5b9b050f517bbf3f10b9071913d4 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/23826 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-07boardid: Switch from Kconfig to weak functionsJulius Werner
This patch switches the board_id and ram_code helper framework to use weak functions rather than Kconfigs to determine whether the board supplies these IDs. This cuts down on the amount of boilerplate Kconfigs many boards have to set and also gives them more flexibility, such as being able to determine at runtime whether a given ID is present. Change-Id: I97d6d1103ebb2a2a7cf1ecfc45709c7e8c1a5cb0 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/22695 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-12-07boardid: Minor clean up and standardizationJulius Werner
Merge the different coreboot table strapping ID structures into one because they're really just all the same, and I want to add more. Make the signature of the board_id() function return a uint32_t because that's also what goes in the coreboot table. Add a printk to the generic code handling strapping IDs in ramstage so that not every individual mainboard implementation needs its own print. (In turn, remove one such print from fsp1_1 code because it's in the way of my next patch.) Change-Id: Ib9563edf07b623a586a4dc168fe357564c5e68b5 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/22741 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-11-17mb/google: Add Chromebook marketing namesJonathan Neuschäfer
It's sometimes hard to find the code name of a Chromebook. Add the marketing names to Kconfig, since they are easily available. Information (mostly) taken from: https://www.chromium.org/chromium-os/developer-information-for-chrome-os-devices Unknown boards (unreleased, etc.): * Fizz * Foster * Nasher, Coral * Purin * Rotor * Rowan * Scarlet, Nefario * Soraka * Urara * Veyron_Rialto Baseboards: * Glados * Gru * Jecht * Kahlee * Nyan * Oak * Poppy * Rambi * Zoombini White label boards: * Enguarde * Heli * Relm, Wizpig TODO: How does this interact with the board_status code? Change-Id: I20a36e23bd3eea8c526a0b3b53cd676cebf9cd86 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/22404 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2017-08-18include/device: Split i2c.h into threeNico Huber
Split `i2c.h` into three pieces to ease reuse of the generic defi- nitions. No code is changed. * `i2c.h` - keeps the generic definitions * `i2c_simple.h` - holds the current, limited to one controller driver per board, devicetree independent I2C interface * `i2c_bus.h` - will become the devicetree compatible interface for native I2C (e.g. non-SMBus) controllers Change-Id: I382d45c70f9314588663e1284f264f877469c74d Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/20845 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-06-13Consolidate reset API, add generic reset_prepare mechanismJulius Werner
There are many good reasons why we may want to run some sort of generic callback before we're executing a reset. Unfortunateley, that is really hard right now: code that wants to reset simply calls the hard_reset() function (or one of its ill-differentiated cousins) which is directly implemented by a myriad of different mainboards, northbridges, SoCs, etc. More recent x86 SoCs have tried to solve the problem in their own little corner of soc/intel/common, but it's really something that would benefit all of coreboot. This patch expands the concept onto all boards: hard_reset() and friends get implemented in a generic location where they can run hooks before calling the platform-specific implementation that is now called do_hard_reset(). The existing Intel reset_prepare() gets generalized as soc_reset_prepare() (and other hooks for arch, mainboard, etc. can now easily be added later if necessary). We will also use this central point to ensure all platforms flush their cache before reset, which is generally useful for all cases where we're trying to persist information in RAM across reboots (like the new persistent CBMEM console does). Also remove cpu_reset() completely since it's not used anywhere and doesn't seem very useful compared to the others. Change-Id: I41b89ce4a923102f0748922496e1dd9bce8a610f Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/19789 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-06-08device/Kconfig: Introduce MAINBOARD_FORCE_NATIVE_VGA_INITNico Huber
MAINBOARD_FORCE_NATIVE_VGA_INIT is to be selected instead of the user option MAINBOARD_DO_NATIVE_VGA_INIT. The distinction is necessary to use the latter in a choice. Change-Id: I689aa5cadea9e1091180fd38b1dc093c6938d69c Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/19813 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-05-30tegra210: Remove fake cpu_reset()Julius Werner
The Tegra210 SoC never had a proper cpu_reset() implementation, so it's pointless to pretend there is one. Most ARM SoCs/boards only define hard_reset() at the moment anyway, so let's stick with that. Change-Id: I40f39921fa99d6dfabf818e7abe7a5732341cf4f Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/19786 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
2017-03-28vboot: Move remaining features out of vendorcode/google/chromeosJulius Werner
This patch attempts to finish the separation between CONFIG_VBOOT and CONFIG_CHROMEOS by moving the remaining options and code (including image generation code for things like FWID and GBB flags, which are intrinsic to vboot itself) from src/vendorcode/google/chromeos to src/vboot. Also taking this opportunity to namespace all VBOOT Kconfig options, and clean up menuconfig visibility for them (i.e. some options were visible even though they were tied to the hardware while others were invisible even though it might make sense to change them). CQ-DEPEND=CL:459088 Change-Id: I3e2e31150ebf5a96b6fe507ebeb53a41ecf88122 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/18984 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-28vboot: Assume EC_SOFTWARE_SYNC and VIRTUAL_DEV_SWITCH by defaultJulius Werner
The virtualized developer switch was invented five years ago and has been used on every vboot system ever since. We shouldn't need to specify it again and again for every new board. This patch flips the Kconfig logic around and replaces CONFIG_VIRTUAL_DEV_SWITCH with CONFIG_PHYSICAL_DEV_SWITCH, so that only a few ancient boards need to set it and it fits better with CONFIG_PHYSICAL_REC_SWITCH. (Also set the latter for Lumpy which seems to have been omitted incorrectly, and hide it from menuconfig since it's a hardware parameter that shouldn't be configurable.) Since almost all our developer switches are virtual, it doesn't make sense for every board to pass a non-existent or non-functional developer mode switch in the coreboot tables, so let's get rid of that. It's also dangerously confusing for many boards to define a get_developer_mode() function that reads an actual pin (often from a debug header) which will not be honored by coreboot because CONFIG_PHYSICAL_DEV_SWITCH isn't set. Therefore, this patch removes all those non-functional instances of that function. In the future, either the board has a physical dev switch and must define it, or it doesn't and must not. In a similar sense (and since I'm touching so many board configs anyway), it's annoying that we have to keep selecting EC_SOFTWARE_SYNC. Instead, it should just be assumed by default whenever a Chrome EC is present in the system. This way, it can also still be overridden by menuconfig. CQ-DEPEND=CL:459701 Change-Id: If9cbaa7df530580a97f00ef238e3d9a8a86a4a7f Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/18980 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-18google/chromeec: Add common infrastructure for boot-mode switchesFurquan Shaikh
Instead of defining the same functions for reading/clearing boot-mode switches from EC in every mainboard, add a common infrastructure to enable common functions for handling boot-mode switches if GOOGLE_CHROMEEC is being used. Only boards that were not moved to this new infrastructure are those that do not use GOOGLE_CHROMEEC or which rely on some mainboard specific mechanism for reading boot-mode switches. BUG=None BRANCH=None TEST=abuild compiles all boards successfully with and without ChromeOS option. Change-Id: I267aadea9e616464563df04b51a668b877f0d578 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17449 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner <jwerner@chromium.org>
2016-09-30Kconfig: Prefix hex defaults with 0xMartin Roth
Because these variables had "non-hexidecimal" defaults, they were updated by kconfig when writing defconfig files. Change-Id: Ic1a070d340708f989157ad18ddc79de7bb92d873 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/16827 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-08-18Kconfig: rename BOOT_MEDIA_SPI_BUS to BOOT_DEVICE_SPI_FLASH_BUSAaron Durbin
Provide a default value of 0 in drivers/spi as there weren't default values aside from specific mainboards and arch/x86. Remove any default 0 values while noting to keep the option's default to 0. BUG=chrome-os-partner:56151 Change-Id: If9ef585e011a46b5cd152a03e41d545b36355a61 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16192 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Martin Roth <martinroth@google.com>
2016-08-15mainboard/google: remove unused BOOT_MEDIA_SPI_CHIP_SELECT optionAaron Durbin
The BOOT_MEDIA_SPI_CHIP_SELECT option is not used in any of the code. Remove its usage. BUG=chrome-os-partner:56151 Change-Id: I522b62a2371b8a167ce17c48117669390cda14cd Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16185 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-07-28vboot: Separate vboot from chromeosFurquan Shaikh
VBOOT_VERIFY_FIRMWARE should be independent of CHROMEOS. This allows use of verified boot library without having to stick to CHROMEOS. BUG=chrome-os-partner:55639 Change-Id: Ia2c328712caedd230ab295b8a613e3c1ed1532d9 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/15867 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-04-13mainboard/google: Update license headersMartin Roth
Update all of the license headers to make sure they are compliant with coreboot's license header policy. Change-Id: Ied67c5079a7f49594edb39caf61fe7f386c3f80d Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/14323 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-04-05chromeos: Simplify fill_lb_gpios even furtherJulius Werner
A long time ago many Chrome OS boards had pages full of duplicated boilerplate code for the fill_lb_gpios() function, and we spent a lot of time bikeshedding a proper solution that passes a table of lb_gpio structs which can be concisely written with a static struct initializer in http://crosreview.com/234648. Unfortunately we never really finished that patch and in the mean time a different solution using the fill_lb_gpio() helper got standardized onto most boards. Still, that solution is not quite as clean and concise as the one we had already designed, and it also wasn't applied consistently to all recent boards (causing more boards with bad code to get added afterwards). This patch switches all boards newer than Link to the better solution and also adds some nicer debug output for the GPIOs while I'm there. If more boards need to be converted from fill_lb_gpio() to this model later (e.g. from a branch), it's quite easy to do with: s/fill_lb_gpio(gpio++,\n\?\s*\([^,]*\),\n\?\s*\([^,]*\),\n\?\s*\([^,]*\),\n\?\s*\([^,]*\));/\t{\1, \2, \4, \3},/ Based on a patch by Furquan Shaikh <furquan@google.com>. BUG=None BRANCH=None TEST=Booted on Oak. Ran abuild -x. Change-Id: I449974d1c75c8ed187f5e10935495b2f03725811 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/14226 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2016-03-25google/intel mainboards: Add missing board_info.txt filesMartin Roth
The lint script didn't catch that these mainboard directories didn't have board_info files. Add all missing board_info.txt files Change-Id: Ib1d61a3c04e91b22480527885faf60c22093d98a Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/14117 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins)
2016-02-12tegra132/210: Remove memlayout_vboot2.ldJulius Werner
Having two separate memlayouts is an unnecessary complication. Contributors need to make sure that their code fits into the vboot one (with smaller stage sizes) either way, and the Tegras have plenty of SRAM anyway. Let's just make the vboot layout the default (as it was done on other SoCs) to keep things easier to maintain. The empty SRAM holes on non-vboot systems where the verstage and work buffer would've been won't hurt them. BRANCH=None BUG=None TEST=Ran abuild with and without --chromeos on Foster, Rush, Ryu and Smaug. Change-Id: If37228facb4de1459cc720dca10bf03e04eb9930 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/13667 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-02-12chromebooks: Define GBB hardware IDsPatrick Georgi
This makes the test IDs the default, taken from depthcharge master (board/*/fmap.dts, hwid property). Change-Id: I25793962ac16f451f204dbba6ede6a64c847cfd5 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/13634 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins)
2016-02-09chromebooks: Configure Chrome EC board namesPatrick Georgi
For devices with Chrome EC, state the "board" name(s), so they're built as part of the image. A number of EC boards aren't supported in the Chrome EC master branch, they're brought along but commented out, waiting for a port to master in the Chrome EC code base. Change-Id: Ic6ab821de55cf9b4e8b48fe5ebc603adeb8bb28b Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/13548 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-01-21chromeos: import Chrome OS fmapsPatrick Georgi
These are generated from depthcharge's board/*/fmap.dts using the dts-to-fmd.sh script. One special case is google/veyron's chromeos.fmd, which is used for a larger set of boards - no problem since the converted fmd was the same for all of them. Set aside 128K for the bootblock on non-x86 systems (where the COREBOOT region ends up at the beginning of flash). This becomes necessary because we're working without a real cbfs master header (exists for transition only), which carved out the space for the offset. Change-Id: Ieeb33702d3e58e07e958523533f83da97237ecf1 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/12715 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-12-10cbfs/vboot: remove firmware component supportAaron Durbin
The Chrome OS verified boot path supported multiple CBFS instances in the boot media as well as stand-alone assets sitting in each vboot RW slot. Remove the support for the stand-alone assets and always use CBFS accesses as the way to retrieve data. This is implemented by adding a cbfs_locator object which is queried for locating the current CBFS. Additionally, it is also signalled prior to when a program is about to be loaded by coreboot for the subsequent stage/payload. This provides the same opportunity as previous for vboot to hook in and perform its logic. BUG=chromium:445938 BRANCH=None TEST=Built and ran on glados. CQ-DEPEND=CL:307121,CL:31691,CL:31690 Change-Id: I6a3a15feb6edd355d6ec252c36b6f7885b383099 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12689 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-07arm64: Remove cpu intialization through device-treeFurquan Shaikh
Since, SMP support is removed for ARM64, there is no need for CPU initialization to be performed via device-tree. Change-Id: I0534e6a93c7dc8659859eac926d17432d10243aa Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: http://review.coreboot.org/11913 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner <jwerner@chromium.org>
2015-11-07arm64: remove spin table supportAaron Durbin
As ARM Trusted Firmware is the only first class citizen for booting arm64 multi-processor in coreboot remove spintable support. If SoCs want to bring up MP then ATF needs to be ported and integrated. Change-Id: I1f38b8d8b0952eee50cc64440bfd010b1dd0bff4 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11908 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner <jwerner@chromium.org>
2015-10-31tree: drop last paragraph of GPL copyright headerPatrick Georgi
It encourages users from writing to the FSF without giving an address. Linux also prefers to drop that and their checkpatch.pl (that we imported) looks out for that. This is the result of util/scripts/no-fsf-addresses.sh with no further editing. Change-Id: Ie96faea295fe001911d77dbc51e9a6789558fbd6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/11888 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-09-04bootmode: add display_init_required()Aaron Durbin
Some of the Chrome OS boards were directly calling vboot called in some form after contorting around #ifdef preprocessor macros. The reasoning is that Chrome OS doesn't always do display initialization during startup. It's runtime dependent. While this is a requirement that doesn't mean vboot functions should be sprinkled around in the mainboard and chipset code. Instead provide one function, display_init_required(), that provides the policy for determining display initialization action. For Chrome OS devices this function honors vboot_skip_display_init() and all other configurations default to initializing display. Change-Id: I403213e22c0e621e148773597a550addfbaf3f7e Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11490 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2015-08-28Smaug: Add NVDEC and TSEC carveoutsTom Warren
The NV security team requested that coreboot allocate the NVDEC and TSEC carveouts. Added code to set up NVDEC (1 region, 1MB) and TSEC (2 regions, splitting 2MB), and set their lock bits. Kernel/trusted code should be able to use the regions now. Note that this change sets the UNLOCKED bit in Carveout1Cfg0 and Carveout4Cfg0/5Cfg0 (bit 1) to 0 in the BCT .inc files (both 3GB and 4GB BCTs) so that the BOMs can be written. Any future revisions to these BCT files should take this into account. BUG=None BRANCH=None TEST=Built and booted on my P5 A44. Saw the carveout regions in the boot spew, and CBMEM living just below the last region (TSEC). Dumped the MC GeneralizedCarveoutX registers and verified their values (same as BCT, with only BOM/CFG0 changed). Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Original-Commit-Id: a34b0772cd721193640b322768ce5fcbb4624f23 Original-Change-Id: I2abc872fa1cc4ea669409ffc9f2e66dbbc4efcd0 Original-Signed-off-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/290452 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Original-(cherry picked from commit f3bbf25397db4d17044e9cfd135ecf73df0ffa60) Original-Reviewed-on: https://chromium-review.googlesource.com/291081 Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Original-Trybot-Ready: Furquan Shaikh <furquan@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Change-Id: I924dfdae7b7c9b877cb1c93fd94f0ef98b728ac5 Reviewed-on: http://review.coreboot.org/11381 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-08-26ChromeOS mainboards: Move more Kconfig symbols under CHROMEOSMartin Roth
Move the CHROMEOS dependent symbols VIRTUAL_DEV_SWITCH and VBOOT_DYNAMIC_WORK_BUFFER under the CHROMEOS config options for the mainboards that use them. Change-Id: Iad126cf045cb3a312319037aff3c4b1f15f6529d Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: http://review.coreboot.org/11336 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2015-08-26Google Kconfig: Add MAINBOARD_HAS_NATIVE_VGA_INIT in good placesMartin Roth
Add 'select MAINBOARD_HAS_NATIVE_VGA_INIT' which is just used as a gate symbol to display MAINBOARD_DO_NATIVE_VGA_INIT to the mainboards that are already selecting MAINBOARD_DO_NATIVE_VGA_INIT. Since MAINBOARD_HAS_NATIVE_VGA_INIT is not used in any code, this should not have any other effects. This fixes the warning: warning: (BOARD_SPECIFIC_OPTIONS) selects MAINBOARD_DO_NATIVE_VGA_INIT which has unmet direct dependencies (VENDOR_ASUS && BOARD_ASUS_KFSN4_DRE || MAINBOARD_HAS_NATIVE_VGA_INIT) Change-Id: I8ceee69ebae90dc32f55df58c2e80fe25397f049 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: http://review.coreboot.org/11301 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-08-21ChromeOS: Fix Kconfig dependenciesMartin Roth
Add CHROMEOS dependencies to selects for the following Kconfig symbols: CHROMEOS_RAMOOPS_DYNAMIC CHROMEOS_RAMOOPS_NON_ACPI CHROMEOS_VBNV_CMOS CHROMEOS_VBNV_EC CHROMEOS_VBNV_FLASH EC_SOFTWARE_SYNC LID_SWITCH RETURN_FROM_VERSTAGE SEPARATE_VERSTAGE VBOOT_DISABLE_DEV_ON_RECOVERY VBOOT_EC_SLOW_UPDATE VBOOT_OPROM_MATTERS VBOOT_STARTS_IN_BOOTBLOCK WIPEOUT_SUPPORTED This gets rid of these sorts of Kconfig errors: warning: BOARD_SPECIFIC_OPTIONS selects CHROMEOS_VBNV_EC which has unmet direct dependencies (MAINBOARD_HAS_CHROMEOS && CHROMEOS) Note: These two boards would never actually have CHROMEOS enabled: intel/emeraldlake2 has MAINBOARD_HAS_CHROMEOS commented out google/peach_pit doesn't have MAINBOARD_HAS_CHROMEOS Change-Id: I51b4ee326f082c6a656a813ee5772e9c34f5c343 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: http://review.coreboot.org/11272 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-07-29Revert "smaug: Do not gate XUSB partitions"Andrew Bresticker
The PLLU and UTMIPLL power-up sequences have been fixed in the kernel. It's no longer necessary for the XUSB partitions to be ungated at boot. This reverts commit 3a4a8a97c1851b6f3dd211451d9678358fac3ad7. BUG=chrome-os-partner:41244 TEST=Build and boot on Smaug; xHCI still works. BRANCH=none CQ-DEPEND=CL:282765 Change-Id: Id9a1c9960b6c7286b3185c60371d864874f50bb3 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: d52e50240bca62997af729722fbcdf5226438b7f Original-Change-Id: Ieb9c8644a5fb108d77703933fde82d359f403fd1 Original-Signed-off-by: Andrew Bresticker <abrestic@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/286810 Original-Reviewed-by: Benson Leung <bleung@chromium.org> Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Original-Tested-by: Mark Kuo <mkuo@nvidia.com> Original-Reviewed-by: Mark Kuo <mkuo@nvidia.com> Reviewed-on: http://review.coreboot.org/11050 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-16smaug: correct odmdata in odmdata.cfgYen Lin
So odmdata has the correct UART port of 0. BUG=chrome-os-partner:40741 BRANCH=None TEST=build Smaug ok; and check scratch20 register Change-Id: I59154daa5b5627d3b594ff9505e4f02de0d4d7aa Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 814cd164ab9ed9bf2e072f3728e89ea8d7cf0343 Original-Change-Id: I2252b728775cf2550d666ead0085c0ab3b72e40b Original-Signed-off-by: Yen Lin <yelin@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/277024 Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/10954 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-16smaug: ramstage: include sdram_configs.cYen Lin
get_sdram_config() (in sdram_configs.c) will be needed in ramstage. BUG=chrome-os-partner:40741 BRANCH=None TEST=Build ok on Smaug Change-Id: I2920f8687b6a801a91dc5b5b50fc5637057e4321 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 4d3092e360b26cbda41549452aeeba9ffc0b92ed Original-Change-Id: I43a20f3178cbf5b57a3a9ca7391856787aa8cdb8 Original-Signed-off-by: Yen Lin <yelin@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/277373 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/10950 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-16smaug: Use VNBN_FLASH instead of VBNV_ECFurquan Shaikh
CQ-DEPEND=CL:285312 BUG=chrome-os-partner:36613 BRANCH=None TEST=Compiles successfully and boots to kernel prompt Change-Id: Ib90333e3331a90b4539d49e1a72833fe3385879f Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 042fc1a451081780f8af35af6943130f6412ca5f Original-Change-Id: I729996c04d8bd6a627421803a59037d7c47a3e98 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/285345 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Original-Trybot-Ready: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/10949 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-16smaug: Increase drive strength for QSPI PinmuxFurquan Shaikh
Change the drive strength for QSPI Pinmux to DRIVE_STRENGTH_2 as per recommendations from nVidia hardware engineers. BUG=chrome-os-partner:41877 BRANCH=None TEST=Compiles successfully and boots to kernel prompt Change-Id: I5a7b94acb57bbc21d277a49fd0a6b892638fc0ca Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 58d085e6acbcd0fd355b1c7efc10606312caf8e8 Original-Change-Id: I03dd288d2e335d40c83feaec7efbf10a7d3bf1e6 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/284959 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Original-Trybot-Ready: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/10945 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-13smaug: Set LDO2 voltage to 1.8VFurquan Shaikh
LDO2 regulator is used as an always-on reference for the droop alert circuit. Set output voltage to match kernel settings. CQ-DEPEND=CL:284649 BUG=chrome-os-partner:42305 BRANCH=None TEST=Compiles successfully and boots to kernel prompt Change-Id: I5ef4e266d8ec278dadffa846af8dc49b6d18c37e Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 611465f6248cba0ddce0083b431cb7ee17bc4b4c Original-Change-Id: I58cc473452b871392d813387707a0b8288e46561 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/284879 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Original-Trybot-Ready: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/10900 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2015-07-09smaug: Update PMIC settingsFurquan Shaikh
Update PMIC settings as per table provided by hardware eng team. Change-Id: I17a8a1a44fa8c9093e13e8d7e4a2f5b07a3b1f1f Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 3c49afd0d1a17b73f2192206ff7389e2f7930fec Original-Change-Id: I027febb6849f1c4d15bf56d8bcd29c431655c7b6 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/283543 Original-Trybot-Ready: Furquan Shaikh <furquan@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/10843 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-07-04Kconfig: Fix references to obsolete symbolsMartin Roth
These are all Kconfig symbols that have been removed or renamed. USE_PRINTK_IN_CAR was removed in commit 8c4f31b3 Drop the USE_PRINTK_IN_CAR option. It's a bogus decision... DYNAMIC_CBMEM was removed in commit e2b0affd Remove Kconfig variable that has no effect MAINBOARD_HAS_BOOTBLOCK_INIT was removed in commit 342535cc Remove Kconfig variable that has no effect CACHE_ROM was removed in commit 4337020b Remove CACHE_ROM. SMM_MODULES was removed in commit 44cbe10f smm: Merge configs SMM_MODULES and SMM_TSEG INCLUDE_MICROCODE_IN_BUILD was removed in commit eb73a218 soc/fsp_baytrail: Fix use of microcode-related Kconfig variables CAR_MIGRATION was removed in commit cbf5bdfe CBMEM: Always select CAR_MIGRATION REQUIRES_BLOB was removed in commit 70c85eab build system: Retire REQUIRES_BLOB CPU_MICROCODE_IN_CBFS was renamed to SUPPORT_CPU_UCODE_IN_CBFS in commit 66e0c4c8 - cpu: Rename CPU_MICROCODE_IN_CBFS to SUPPORT_CPU_UCODE_IN_CBFS CONSOLE_SERIAL_UART was renamed to CONSOLE_SERIAL in commit afa7b13b uart: Redefine Kconfig options CONSOLE_SERIAL8250MEM was renamed to DRIVERS_UART_8250MEM in commit afa7b13b - uart: Redefine Kconfig options Change-Id: I8952ca8c53ac2e6cec5f9c77d2f413f086bfab9d Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: http://review.coreboot.org/10766 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-07-03Kconfig whitespace cleanup: Change leading spaces to tabsMartin Roth
Change-Id: Icab6bd9f55f086da7b51ae463f34e29366d50e1a Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: http://review.coreboot.org/10764 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-06-30google/smaug: roll up fixes to compile with vbootPatrick Georgi
Change-Id: I256410ff6c0107bbbaaf49b909d63ca61e88a22c Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10731 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2015-06-30google/smaug: add new mainboardPatrick Georgi
This is an nvidia t210 based board. This includes Chrome OS downstream up to Change-Id: Ic89ed54c. Change-Id: I4d77659f4f2d21b1bbdcfc3467e1a166c02ddd47 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10635 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-14 02:48:22 +0000