| Age | Commit message (Collapse) | Author |
|---|
|
wpsw_boot is deprecated in favour of wpsw_cur. As such,
coreboot no longer needs to share "write protect" GPIO
with depthcharge.
BUG=b:124141368, chromium:950273
TEST=make clean && make test-abuild
BRANCH=none
Change-Id: I2fcb7f82aa063fd72928171af5cbef0356ba620c
Signed-off-by: Joel Kitching <kitching@google.com>
Cq-Depend: chromium:2088434
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39318
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Change-Id: I77c33c19b56dc9bd54e7555ce59f6a07bde3dbb6
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39081
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
|
|
Commit 6ae8b50 [chromeec: Depend on events_copy_b to identify wake source]
partially broke resume from suspend on Auron and Slippy variants when
multiple events exist in the EC event queue. In the case of the device
suspending manually and then subsequently having the lid closed, the device
will be stuck in a resume/suspend/resume loop until the device is forcibly
powered down.
Mitigate this by clearing any pending EC events on S3 wakeup.
Test: build/boot several Auron/Slippy variants, test suspend/resume functional
with both single and multiple events in EC event queue.
Change-Id: I7ec9ec575d41c5b7522c4e13fc32b0b7c77d20d9
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38984
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
Change based on google/auron that is similar to peppy.
This will be helpful for the next follow-up commit that will
add ACPI for the ambient light sensor.
Change-Id: Ib2a8356d261d211d5ed5c0b035c94ec56b9c25b3
Signed-off-by: Nicolò Veronese <nicveronese@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37992
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
|
|
The current BIOS-extracted VBT breaks backlight control
with Tianocore, so replace it with one that does. Settings
were exported using Intel BMP tool and the overlayed onto
a GOP-format (vs BIOS format) VBT file.
Test: boot google/wolf with both SeaBIOS and Tianocore payloads,
verify backlight control functional under both Linux and Windows.
Change-Id: Id6281c8dfb6e0001be8c4d9be1013f2d4bbb5880
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38397
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
|
|
Denary, also known as "decimal" or "base 10," is the standard
number system used around the world. Therefore, make use of it.
Change-Id: I7f2937bb7715e0769db3be8cb30d305f9d78b6f8
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37849
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
|
|
Remove commented-out entries in dsdt.asl, and then remove files that do
not get built.
Change-Id: I579e7ffbc2d6596fd7ffe6863ff3b3fb14b0ade6
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37857
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
|
|
Adapted from Chromium commit b8dcb1a [Peppy: Update Memory IDs]
Add Hynix memory HMT425S6CFR6A support.
RAM_ID: 011 4GB Hynix HMT425S6CFR6A
RAM_ID: 111 2GB Hynix HMT425S6CFR6A
Original-Change-Id: I26d5c4ad00509e7823c325ee8391e0b18fee44d8
Original-Signed-off-by: David Wu <David_Wu@quantatw.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/1074849
Original-Reviewed-by: Duncan Laurie <dlaurie@google.com>
Original-Tested-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I4d165f61b8a13e5ed025e9ddbc4330db88e2fa3d
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37941
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
Recent changes to the Atmel touchscreen driver in the mainline
kernel broke functionality with devices running upstream coreboot,
due relying on another driver (chromeos_laptop) which makes the
assumption that the i2c devices are be in PCI mode (as with the
stock Google firmware) rather than in ACPI mode as they are in
upstream coreboot.
Mitigate this by adding the required devicetree property so the
Atmel toushcreen driver will correctly attach without the use
of chromeos_laptop.
Test: build/boot peppy on 4.18+ kernel, verify touchscreen working
Change-Id: I05df8367886eef55b409590f75a68d98d4e5fbdf
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37915
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicolò
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
Previously, each Intel chipset had its own sleepstates.asl file.
However, this is no longer the case, so drop these comments.
Change-Id: I50aba6e74f41e2fa498375b5eb6b7e993d06bcac
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37855
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
|
|
Remove acpi_update_thermal_table local function.
Change-Id: I4857348088feb8eaf1dd7f553c4efb29da8943cf
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36212
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
|
|
It provides no useful information, so it might as well vanish.
Change-Id: I0df6f4639a16058486c2e2d40fe4067d65670731
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37856
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
|
|
Change-Id: I5791fddec8b2387df5979adbb1a0fa64c5dd23ea
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37522
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
|
|
Change-Id: I4dcdcb734e20830ac97d4a826de61017afc6ee67
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37688
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
|
|
Change-Id: If99c8ea1aa437f261e8ab3c8a164d01be8bc58e9
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33893
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
|
|
Update VBT using file extracted from VGA BIOS from stock
firmware image using intelvbttool, zero-padded to 0x11ff
bytes to make the Intel BMP editor happy.
Change-Id: I9f53e80305ec8de78a3d5c930224b394b5c8618a
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37732
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Change-Id: I9e71474bea61befd61900aff554f32f1bc782a77
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33699
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
|
|
Kconfig became stricter on what it accepts, so accomodate before
updating to a new release.
Change-Id: I92a9e9bf0d557a7532ba533cd7776c48f2488f91
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37156
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
This avoids a lot of if (CONFIG(ELOG_GSMI)) boilerplate.
Change-Id: I87d25c820daedeb33b3b474a6632a89ea80b0867
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36647
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Change-Id: I86260a374a3f60f16dc73573e7989f0a4ffec818
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36580
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
This patch creates a common instance of sleepstates.asl inside intel common
code (southbridge/intel/common/acpi) and asks all IA CPU/SOC code to
refer sleepstates.asl from common code block.
TEST=Able to build and boot Hatch and ICL DE system. Dump DSDT.asl to verify
S0/S3/S4/S5 entries after booting to OS.
Change-Id: Ie2132189f91211df74f8b5546da63ded4fdf687a
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36463
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Change-Id: I3d90e46ed391ce323436750c866a0afc3879e2e6
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36359
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Previously all boards using eSPI for the Chrome EC just called it
LPC as the code for the chrome EC is the same between the two
busses.
I'm adding a new Kconfig symbol to specify eSPI, so switch the
boards that actually use eSPI to that symbol and add the LPC
symbol to all the others.
The EC_GOOGLE_CHROMEEC_LPC symbol will no longer default
to enabled for x86 platforms, so one symbol or the other needs to be
specified for each platform.
BUG=b:140055300
TEST=Build tested only.
Change-Id: Icf242ca2b7d8b1470feda4e44b47a2cdc20680f2
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35153
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
The CONFIG_GBB_HWID can be generated automatically now so we can remove
the test-only HWIDs set in board config files.
BUG=b:140067412
TEST=Built few boards (kukui, cheza, octopus) and checked HWID:
futility gbb -g coreboot.rom
Change-Id: I4070f09d29c5601dff1587fed8c60714eb2558b7
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35635
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Change-Id: Icdbccb3af294dd97ba1835f034669198094a3661
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33528
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Change-Id: I3323d25b72dab2f9bc8a575ba41faf059ee1ffc4
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34933
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
|
|
This is LVDS bridge, I assume this was lost while upstreaming
or converting boards to variants.
Change-Id: I816a6b4035c4e935150cc77089c4224eee719c10
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35106
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
|
|
This provides stack guards with checking and common
entry into postcar.
The code in cpu/intel/car/romstage.c is candidate
for becoming architectural so function prototype
is moved to <arch/romstage.h>.
Change-Id: I4c5a9789e7cf3f7f49a4a33e21dac894320a9639
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34893
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Change-Id: I2ebeb393e4a5a4bfac8a37a877d067aca484ca2e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34927
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
When entry to romstage is via cpu/intel/car/romstage.c
BIST has not been passed down the path for sometime.
Change-Id: I345975c53014902269cee21fc393331d33a84dce
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34908
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
|
|
Build of the entire smm-class is skipped if we have
HAVE_SMI_HANDLER=n.
Change-Id: I10b4300ddd18b1673c404b45fd9642488ab3186c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34125
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Lance Zhao <lance.zhao@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Legacy Google mainboards (pre-Skylake) shipped with the
SMBIOS manufacturer set to GOOGLE, which many Linux drivers
rely on for application of DMI quirks. Set it as the default
to avoid having to do so for each board's config
Change-Id: I61b0217f3535852d7d6e24a1ac78075c20c0825a
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33027
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
|
|
Required for automatic onboard device detection in the next patch.
Change-Id: I3087de779faf8d006510c460b5372b22ae54b887
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32909
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
The gpio table is only used by depthcharge, and depthcharge rarely
has a need for the "recovery" gpio. On a few boards it does use the
gpio as a signal for confirming physical presence, so on that boards
we'll advertise the board as "presence".
All these strings probably should have been #defines to help avoid
typos (e.g., the "ec_in_rw" in stout seems questionable since everybody
else uses "EC in RW").
Cq-Depend: chromium:1580454
BUG=b:129471321
BRANCH=None
TEST=Local compile and flash (with corresponding changes to depthcharge)
to 2 systems, one with a "presence" gpio and another without. Confirmed
that both systems could enter dev mode.
Change-Id: Id6d62d9e48d3e6646cbc1277ea53f0ca95dd849e
Signed-off-by: Matt Delco <delco@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32718
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
|
|
The "write protect" GPIO's cached value is never actually
read after entering depthcharge. Ensure the value from
get_write_protect_state() is being transferred accurately,
so that we may read this GPIO value in depthcharge without
resampling.
The cached value of the "recovery" GPIO is read only on certain
boards which have a physical recovery switch. Correct some of
the values sent to boards which presumably never read the
previously incorrect value. Most of these inaccuracies are from
non-inverted values on ACTIVE_LOW GPIOs.
BUG=b:124141368, b:124192753, chromium:950273
TEST=make clean && make test-abuild
BRANCH=none
Change-Id: Ic17a98768703d7098480a9233b752fe5b201bd51
Signed-off-by: Joel Kitching <kitching@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32233
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
|
|
Change-Id: I23bc0191ca8fcd88364e5c08be7c90195019e399
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32012
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: David Guckian
|
|
Drop 'include <string.h>' when it is not used and
add it when it is missing.
Also extra lines removed, or added just before local includes.
Change-Id: Iccac4dbaa2dd4144fc347af36ecfc9747da3de20
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31966
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
|
|
Change-Id: I1341f90230f318ac81a4aea24872ff272adad1eb
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31856
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Use <arch/acpi.h> when appropriate.
Change-Id: I05a28d2c15565c21407101e611ee1984c5411ff0
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31781
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
|
|
This patch is a raw application of
find src/ -type f | xargs sed -i -e 's/IS_ENABLED\s*(CONFIG_/CONFIG(/g'
Change-Id: I6262d6d5c23cabe23c242b4f38d446b74fe16b88
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31774
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
|
|
The other DEFAULT_ entries are just immediate
constants.
Change-Id: Iebf4266810b8210cebabc814bba2776638d9b74d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31758
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
|
|
For Chrome OS (or vboot), The PRESERVE flags should be applied on
following sections:
RO_PRESERVE, RO_VPD, RW_PRESERVE, RW_ELOG, RW_NVRAM, RW_SMMSTORE,
RW_VPD, RO_FSG (b:116326638), SI_GBE (chromium:936768),
SI_PDR (chromium:936768)
With the new PRESERVE flag, we don't need RO_PRESERVE and RW_PRESERVE in
the future. But it's still no harm to use it if there are multiple
sections all needing to be preserved.
BUG=chromium:936768
TEST=Builds google/eve and google/kukui inside Chrome OS source tree.
Also boots successfully on eve and kukui devices.
Change-Id: I6664ae3d955001ed14374e2788d400ba5fb9b7f8
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31709
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
|
|
The vbt was extracted from the option rom found on stock images.
The vbt.bin is the same across all variants.
The VBT has a modified BDB block 43, the 'Backlight info block' such
that the inverter type for the panel in use is set to
2 (BDB_BACKLIGHT_TYPE_PWM) instead of 0 (BDB_BACKLIGHT_TYPE_NONE).
This only seems to matter on Windows, as without it changing the
backlight duty cycle does not work.
Change-Id: I82c72c561e1058e0b77d80baf330b64f7c6b08e3
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/30487
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Change-Id: I4ee3cc42302c44dc80ae1f285579a4d1775aec16
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/30199
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
|
|
All Lynx Point board select this, and none build without it.
Change-Id: I4b59b10ee985cff5a8e1442677d36b0be88cf437
Signed-off-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-on: https://review.coreboot.org/c/29992
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
|
|
The ASRock H81M-HDS doesn't implement a finalise handler. To fix
this, and reduce code duplication in the process, make a common
implementation. There should be no functional change to boards with
existing finalise handlers, since the code is identical among them and
the new, common implementation.
Tested on an ASRock H81M-HDS. The finalise handler works.
Change-Id: I13b581a2219288019a4e0c9e618db3ac7c3c15ab
Signed-off-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-on: https://review.coreboot.org/c/29975
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
|
|
Change-Id: Ifa5a3a22771ff2e0efa14fb765603fd5e0440d59
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/29894
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: David Guckian
|
|
Use acpigen_write_processor_cnot to implement notifications the CPU.
Generate PPKG in SSDT.
Change-Id: I126989e8737720f55f7ce113ff4e32bfe0f22620
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/29885
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Field 'OEMID' & "OEM Table ID" are related to DSDT table
not to mainboard.
So use macro to set them respectvely to "COREv4" and
"COREBOOT".
Change-Id: I060e07a730e721df4a86128ee89bfe168c69f31e
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/29790
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: David Guckian
|
|
DSDT revision is =1 for ACPI v1 and =2 for greater ACPI version.
This will cause the AML interpreter to use 32-bit integers and math
if the version is 1, and 64-bit if the version is >=2.
Current spec version is 2 for ACPI 6.2-a.
Change-Id: I77372882d5c77b7ed52dcdd88028403df6f6fa7f
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/29626
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Change-Id: I44f27405fc8ccbe54c7d19b70327da866390a156
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/28603
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
|
|
Change-Id: I89e03b6def5c78415bf73baba55941953a70d8de
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/29302
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
The function `acpi_fill_fadt()` is based on that of sb/intel/bd82x6x.
Tested on an ASRock H81M-HDS and a Google Peppy board, both using Linux
4.9 with `acpi=strict`. No ACPI errors or warnings appear in the kernel
log. System reset, poweroff, and S3 suspend/resume continue to work.
General improvements
--------------------
- `fadt->preferred_pm_profile` is set based on the value of
`CONFIG_SYSTEM_TYPE_LAPTOP` instead of being hardcoded.
- Constants are used instead of magic values in more locations.
- `fadt->gpe0_blk`, `fadt->gpe0_blk_len`, and `fadt->x_gpe0_blk` are set
appropriately depending on whether the system uses Lynx Point LP or
not.
- Boards can indicate docking support in the FADT via the devicetree.
Changes to existing Lynx Point boards
-------------------------------------
- `header->asl_compiler_revision` changes from 1 to 0.
- `fadt->model` is left at 0 instead of being set to 1. This field is
only needed for ACPI 1.0 compatibility.
- `fadt->flush_size` and `fadt->flush_stride` are set to 0. This is
because their values are ignored, since `ACPI_FADT_WBINVD` is set in
`fadt->flags`.
- `fadt->duty_offset` is set to 0 instead of 1. None of the existing
boards indicate support for changing the processor duty cycle (as
`fadt->duty_width` is set to 0), so `fadt->duty_offset` does not
currently need to be set.
- Access sizes of registers are set.
- On mb/intel/baskingridge, the pmbase is now read using the common
function `get_pmbase()` instead of `pci_read_config16(...)`.
- On mb/intel/baskingridge, the value of `fadt->x_gpe0_blk.bit_width`
changes from 64 to 128. The correct value should be 128 (bits), to
match `fadt->gpe0_blk_len`, which is set to 16 (bytes).
- On Lynx Point LP systems, the unused extended address
`fadt->x_gpe0_blk` sets its address space ID to be consistent with
other unused extended addresses. Such a change should not alter the
interpretation of the registers as being unused. Why not set them all
to zero? Simply because the existing practice, in both coreboot and
some other vendors' firmware, has them set in such a case.
A diff of the FADT from a Google Peppy board is below:
--- pre/facp.dsl 2018-10-30 20:14:52.676570798 +1300
+++ post/facp.dsl 2018-10-30 20:15:06.904381436 +1300
@@ -1,179 +1,179 @@
/*
* Intel ACPI Component Architecture
* AML/ASL+ Disassembler version 20180810 (64-bit version)
* Copyright (c) 2000 - 2018 Intel Corporation
*
- * Disassembly of facp.dat, Tue Oct 30 20:14:52 2018
+ * Disassembly of facp.dat, Tue Oct 30 20:15:06 2018
*
* ACPI Data Table [FACP]
*
* Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
*/
[000h 0000 4] Signature : "FACP" [Fixed ACPI Description Table (FADT)]
[004h 0004 4] Table Length : 000000F4
[008h 0008 1] Revision : 04
-[009h 0009 1] Checksum : 61
+[009h 0009 1] Checksum : 6E
[00Ah 0010 6] Oem ID : "CORE "
[010h 0016 8] Oem Table ID : "COREBOOT"
[018h 0024 4] Oem Revision : 00000000
[01Ch 0028 4] Asl Compiler ID : "CORE"
-[020h 0032 4] Asl Compiler Revision : 00000001
+[020h 0032 4] Asl Compiler Revision : 00000000
[024h 0036 4] FACS Address : 7BF46240
[028h 0040 4] DSDT Address : 7BF46280
-[02Ch 0044 1] Model : 01
+[02Ch 0044 1] Model : 00
[02Dh 0045 1] PM Profile : 02 [Mobile]
[02Eh 0046 2] SCI Interrupt : 0009
[030h 0048 4] SMI Command Port : 000000B2
[034h 0052 1] ACPI Enable Value : E1
[035h 0053 1] ACPI Disable Value : 1E
[036h 0054 1] S4BIOS Command : 00
[037h 0055 1] P-State Control : 00
[038h 0056 4] PM1A Event Block Address : 00001000
[03Ch 0060 4] PM1B Event Block Address : 00000000
[040h 0064 4] PM1A Control Block Address : 00001004
[044h 0068 4] PM1B Control Block Address : 00000000
[048h 0072 4] PM2 Control Block Address : 00001050
[04Ch 0076 4] PM Timer Block Address : 00001008
[050h 0080 4] GPE0 Block Address : 00001080
[054h 0084 4] GPE1 Block Address : 00000000
[058h 0088 1] PM1 Event Block Length : 04
[059h 0089 1] PM1 Control Block Length : 02
[05Ah 0090 1] PM2 Control Block Length : 01
[05Bh 0091 1] PM Timer Block Length : 04
[05Ch 0092 1] GPE0 Block Length : 20
[05Dh 0093 1] GPE1 Block Length : 00
[05Eh 0094 1] GPE1 Base Offset : 00
[05Fh 0095 1] _CST Support : 00
[060h 0096 2] C2 Latency : 0001
[062h 0098 2] C3 Latency : 0057
-[064h 0100 2] CPU Cache Size : 0400
-[066h 0102 2] Cache Flush Stride : 0010
-[068h 0104 1] Duty Cycle Offset : 01
+[064h 0100 2] CPU Cache Size : 0000
+[066h 0102 2] Cache Flush Stride : 0000
+[068h 0104 1] Duty Cycle Offset : 00
[069h 0105 1] Duty Cycle Width : 00
[06Ah 0106 1] RTC Day Alarm Index : 0D
[06Bh 0107 1] RTC Month Alarm Index : 00
[06Ch 0108 1] RTC Century Index : 00
[06Dh 0109 2] Boot Flags (decoded below) : 0003
Legacy Devices Supported (V2) : 1
8042 Present on ports 60/64 (V2) : 1
VGA Not Present (V4) : 0
MSI Not Supported (V4) : 0
PCIe ASPM Not Supported (V4) : 0
CMOS RTC Not Present (V5) : 0
[06Fh 0111 1] Reserved : 00
[070h 0112 4] Flags (decoded below) : 00008CAD
WBINVD instruction is operational (V1) : 1
WBINVD flushes all caches (V1) : 0
All CPUs support C1 (V1) : 1
C2 works on MP system (V1) : 1
Control Method Power Button (V1) : 0
Control Method Sleep Button (V1) : 1
RTC wake not in fixed reg space (V1) : 0
RTC can wake system from S4 (V1) : 1
32-bit PM Timer (V1) : 0
Docking Supported (V1) : 0
Reset Register Supported (V2) : 1
Sealed Case (V3) : 1
Headless - No Video (V3) : 0
Use native instr after SLP_TYPx (V3) : 0
PCIEXP_WAK Bits Supported (V4) : 0
Use Platform Timer (V4) : 1
RTC_STS valid on S4 wake (V4) : 0
Remote Power-on capable (V4) : 0
Use APIC Cluster Model (V4) : 0
Use APIC Physical Destination Mode (V4) : 0
Hardware Reduced (V5) : 0
Low Power S0 Idle (V5) : 0
[074h 0116 12] Reset Register : [Generic Address Structure]
[074h 0116 1] Space ID : 01 [SystemIO]
[075h 0117 1] Bit Width : 08
[076h 0118 1] Bit Offset : 00
-[077h 0119 1] Encoded Access Width : 00 [Undefined/Legacy]
+[077h 0119 1] Encoded Access Width : 01 [Byte Access:8]
[078h 0120 8] Address : 0000000000000CF9
[080h 0128 1] Value to cause reset : 06
[081h 0129 2] ARM Flags (decoded below) : 0000
PSCI Compliant : 0
Must use HVC for PSCI : 0
[083h 0131 1] FADT Minor Revision : 00
[084h 0132 8] FACS Address : 000000007BF46240
[08Ch 0140 8] DSDT Address : 000000007BF46280
[094h 0148 12] PM1A Event Block : [Generic Address Structure]
[094h 0148 1] Space ID : 01 [SystemIO]
[095h 0149 1] Bit Width : 20
[096h 0150 1] Bit Offset : 00
-[097h 0151 1] Encoded Access Width : 00 [Undefined/Legacy]
+[097h 0151 1] Encoded Access Width : 02 [Word Access:16]
[098h 0152 8] Address : 0000000000001000
[0A0h 0160 12] PM1B Event Block : [Generic Address Structure]
[0A0h 0160 1] Space ID : 01 [SystemIO]
[0A1h 0161 1] Bit Width : 00
[0A2h 0162 1] Bit Offset : 00
[0A3h 0163 1] Encoded Access Width : 00 [Undefined/Legacy]
[0A4h 0164 8] Address : 0000000000000000
[0ACh 0172 12] PM1A Control Block : [Generic Address Structure]
[0ACh 0172 1] Space ID : 01 [SystemIO]
[0ADh 0173 1] Bit Width : 10
[0AEh 0174 1] Bit Offset : 00
-[0AFh 0175 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0AFh 0175 1] Encoded Access Width : 02 [Word Access:16]
[0B0h 0176 8] Address : 0000000000001004
[0B8h 0184 12] PM1B Control Block : [Generic Address Structure]
[0B8h 0184 1] Space ID : 01 [SystemIO]
[0B9h 0185 1] Bit Width : 00
[0BAh 0186 1] Bit Offset : 00
[0BBh 0187 1] Encoded Access Width : 00 [Undefined/Legacy]
[0BCh 0188 8] Address : 0000000000000000
[0C4h 0196 12] PM2 Control Block : [Generic Address Structure]
[0C4h 0196 1] Space ID : 01 [SystemIO]
[0C5h 0197 1] Bit Width : 08
[0C6h 0198 1] Bit Offset : 00
-[0C7h 0199 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0C7h 0199 1] Encoded Access Width : 01 [Byte Access:8]
[0C8h 0200 8] Address : 0000000000001050
[0D0h 0208 12] PM Timer Block : [Generic Address Structure]
[0D0h 0208 1] Space ID : 01 [SystemIO]
[0D1h 0209 1] Bit Width : 20
[0D2h 0210 1] Bit Offset : 00
-[0D3h 0211 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0D3h 0211 1] Encoded Access Width : 03 [DWord Access:32]
[0D4h 0212 8] Address : 0000000000001008
[0DCh 0220 12] GPE0 Block : [Generic Address Structure]
-[0DCh 0220 1] Space ID : 00 [SystemMemory]
+[0DCh 0220 1] Space ID : 01 [SystemIO]
[0DDh 0221 1] Bit Width : 00
[0DEh 0222 1] Bit Offset : 00
[0DFh 0223 1] Encoded Access Width : 00 [Undefined/Legacy]
[0E0h 0224 8] Address : 0000000000000000
[0E8h 0232 12] GPE1 Block : [Generic Address Structure]
[0E8h 0232 1] Space ID : 01 [SystemIO]
[0E9h 0233 1] Bit Width : 00
[0EAh 0234 1] Bit Offset : 00
[0EBh 0235 1] Encoded Access Width : 00 [Undefined/Legacy]
[0ECh 0236 8] Address : 0000000000000000
Change-Id: I9638bb5ff998518eb750e3e7e85b51cdaf1f070e
Signed-off-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-on: https://review.coreboot.org/29387
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Change-Id: Ic9620cfa1630c7c085b6c244ca80dc023a181e30
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/29595
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
|
|
Change-Id: Ib3aafcc586b1631a75f214cfd19706108ad8ca93
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/29285
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
The function `acpi_fill_madt()` is identical among all the Lynx Point
boards and sb/intel/bd82x6x, so share a common function between them.
Earlier Intel platforms have similar implementations of this function.
The common implementation might only need minor alterations to support
them.
Tested on an ASRock H81M-HDS and Google Peppy (variant of Slippy). No
issues arose from this patch.
Change-Id: Ife9e3917febf43d8a92cac66b502e2dee8527556
Signed-off-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-on: https://review.coreboot.org/29388
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
|
|
The platform.asl file is copied from sb/intel/bd82x6x, and also matches
the contents deleted from each mainboard's platform.asl.
Tested on an ASRock H81M-HDS and a Google Peppy board (variant of
Slippy). No issues arose from this patch.
Change-Id: I539e401ce9af83070f69147526ca3b1c122f042c
Signed-off-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-on: https://review.coreboot.org/29386
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
|
|
This patch is based on a8a9f34e9b7b ("sb/intel/i82801{g,j}x:
Automatically generate ACPI PIRQ tables")
Tested on an ASRock H81M-HDS. The generated _PRT object looks correct,
and the system doesn't show any issue when running. The following
assignments occur:
ACPI_PIRQ_GEN: PCI: 00:02.0: pin=0 pirq=0
ACPI_PIRQ_GEN: PCI: 00:03.0: pin=0 pirq=0
ACPI_PIRQ_GEN: PCI: 00:14.0: pin=0 pirq=0
ACPI_PIRQ_GEN: PCI: 00:16.0: pin=0 pirq=0
ACPI_PIRQ_GEN: PCI: 00:1a.0: pin=0 pirq=0
ACPI_PIRQ_GEN: PCI: 00:1b.0: pin=0 pirq=6
ACPI_PIRQ_GEN: PCI: 00:1c.0: pin=0 pirq=0
ACPI_PIRQ_GEN: PCI: 00:1c.1: pin=1 pirq=1
ACPI_PIRQ_GEN: PCI: 00:1c.2: pin=2 pirq=2
ACPI_PIRQ_GEN: PCI: 00:1c.3: pin=3 pirq=3
ACPI_PIRQ_GEN: PCI: 00:1d.0: pin=0 pirq=7
ACPI_PIRQ_GEN: PCI: 00:1f.2: pin=1 pirq=3
ACPI_PIRQ_GEN: PCI: 00:1f.3: pin=2 pirq=2
Also tested on a Google Peppy board. The following assignments occur:
ACPI_PIRQ_GEN: PCI: 00:02.0: pin=0 pirq=0
ACPI_PIRQ_GEN: PCI: 00:03.0: pin=0 pirq=0
ACPI_PIRQ_GEN: PCI: 00:14.0: pin=0 pirq=2
ACPI_PIRQ_GEN: PCI: 00:1b.0: pin=0 pirq=6
ACPI_PIRQ_GEN: PCI: 00:1c.0: pin=0 pirq=0
ACPI_PIRQ_GEN: PCI: 00:1d.0: pin=0 pirq=3
ACPI_PIRQ_GEN: PCI: 00:1f.2: pin=0 pirq=6
ACPI_PIRQ_GEN: PCI: 00:1f.3: pin=1 pirq=2
ACPI_PIRQ_GEN: PCI: 00:1f.6: pin=2 pirq=1
A diff of the _PRT object for the Google Peppy board is below. The code
used in the diff has been modified for clarity, but the semantics remain
the same. To summarise the diff:
* The disabled PCIe root ports are no longer included.
* The LPC controller is no longer included, as it has no interrupt pin.
The pins for the remaining LPC devices are each one less. Perhaps the
original _PRT object was incorrect?
* The SDIO device is no longer included, as it is disabled.
* The Serial IO devices are no longer included, but that is due to a
separate issue I am having with this system (the devices don't show up
under Linux regardless of this patch). In short: their omission is not
a fault of this patch.
--- pre/_PRT
+++ post/_PRT
@@ -1,301 +1,157 @@
Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table
{
If (PICM)
{
- Return (Package (0x12)
+ Return (Package (0x09)
{
Package (0x04)
{
0x0002FFFF,
Zero,
Zero,
0x10
},
Package (0x04)
{
0x0003FFFF,
Zero,
Zero,
0x10
},
Package (0x04)
{
0x0014FFFF,
Zero,
Zero,
0x12
},
Package (0x04)
{
0x001BFFFF,
Zero,
Zero,
0x16
},
Package (0x04)
{
0x001CFFFF,
Zero,
Zero,
0x10
},
- Package (0x04)
- {
- 0x001CFFFF,
- One,
- Zero,
- 0x11
- },
-
- Package (0x04)
- {
- 0x001CFFFF,
- 0x02,
- Zero,
- 0x12
- },
-
- Package (0x04)
- {
- 0x001CFFFF,
- 0x03,
- Zero,
- 0x13
- },
-
Package (0x04)
{
0x001DFFFF,
Zero,
Zero,
0x13
},
Package (0x04)
{
0x001FFFFF,
Zero,
Zero,
0x16
},
Package (0x04)
{
0x001FFFFF,
One,
Zero,
0x12
},
Package (0x04)
{
0x001FFFFF,
0x02,
Zero,
0x11
- },
-
- Package (0x04)
- {
- 0x001FFFFF,
- 0x03,
- Zero,
- 0x10
- },
-
- Package (0x04)
- {
- 0x0015FFFF,
- Zero,
- Zero,
- 0x14
- },
-
- Package (0x04)
- {
- 0x0015FFFF,
- One,
- Zero,
- 0x15
- },
-
- Package (0x04)
- {
- 0x0015FFFF,
- 0x02,
- Zero,
- 0x15
- },
-
- Package (0x04)
- {
- 0x0015FFFF,
- 0x03,
- Zero,
- 0x15
- },
-
- Package (0x04)
- {
- 0x0017FFFF,
- Zero,
- Zero,
- 0x17
}
})
}
Else
{
- Return (Package (0x12)
+ Return (Package (0x09)
{
Package (0x04)
{
0x0002FFFF,
Zero,
^LPCB.LNKA,
Zero
},
Package (0x04)
{
0x0003FFFF,
Zero,
^LPCB.LNKA,
Zero
},
Package (0x04)
{
0x0014FFFF,
Zero,
^LPCB.LNKC,
Zero
},
Package (0x04)
{
0x001BFFFF,
Zero,
^LPCB.LNKG,
Zero
},
Package (0x04)
{
0x001CFFFF,
Zero,
^LPCB.LNKA,
Zero
},
- Package (0x04)
- {
- 0x001CFFFF,
- One,
- ^LPCB.LNKB,
- Zero
- },
-
- Package (0x04)
- {
- 0x001CFFFF,
- 0x02,
- ^LPCB.LNKC,
- Zero
- },
-
- Package (0x04)
- {
- 0x001CFFFF,
- 0x03,
- ^LPCB.LNKD,
- Zero
- },
-
Package (0x04)
{
0x001DFFFF,
Zero,
^LPCB.LNKD,
Zero
},
Package (0x04)
{
0x001FFFFF,
Zero,
^LPCB.LNKG,
Zero
},
Package (0x04)
{
0x001FFFFF,
One,
^LPCB.LNKC,
Zero
},
Package (0x04)
{
0x001FFFFF,
0x02,
^LPCB.LNKB,
Zero
- },
-
- Package (0x04)
- {
- 0x001FFFFF,
- 0x03,
- ^LPCB.LNKA,
- Zero
- },
-
- Package (0x04)
- {
- 0x0015FFFF,
- Zero,
- ^LPCB.LNKE,
- Zero
- },
-
- Package (0x04)
- {
- 0x0015FFFF,
- One,
- ^LPCB.LNKF,
- Zero
- },
-
- Package (0x04)
- {
- 0x0015FFFF,
- 0x02,
- ^LPCB.LNKF,
- Zero
- },
-
- Package (0x04)
- {
- 0x0015FFFF,
- 0x03,
- ^LPCB.LNKF,
- Zero
- },
-
- Package (0x04)
- {
- 0x0017FFFF,
- Zero,
- ^LPCB.LNKH,
- Zero
}
})
}
}
Change-Id: Id3f067cbf7c7d649fbbf774648d8ff928cb752a4
Signed-off-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-on: https://review.coreboot.org/29381
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
|
|
The assignment of header->checksum was in some cases done twice, or
unnecessarily split into two lines.
Change-Id: Ib0c0890d7589e6a24b11e9bda10e6969c7d73c56
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/28988
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
|
|
The helper function to get the board version from EC returns 0 on
failure. But 0 is also a valid board version. Update the helper function
to return -1 on failure and update the use-cases.
BUG=b:114001972,b:114677884,b:114677887
Change-Id: I93e8dbce2ff26e76504b132055985f53cbf07d31
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Tested-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/28576
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Jett Rink <jettrink@google.com>
|
|
Only for those that are x86 and also have a RW_LEGACY region.
The assumption is that all devices touched have 64k block sizes when
choosing size and alignment of the region.
Change-Id: I12addb137604f003d1296f34f555dae219330b18
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/28532
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Most FADT report using ACPIv3 FADT table. Using the get revision
function keeps the table versions in sync.
Change-Id: Ie554faf1be65c7034dd0836f0029cdc79eae1aed
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/28277
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
Change-Id: Ia38c6f8d978065090564d449cae11d54ddb96421
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/28064
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
|
|
There is no need to redefine option present in
southbridge/intel/common/firmware/Kconfig.
Change-Id: I9999440031b07006e2df11e00dfb9f3dbe04f832
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/28007
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Change-Id: I3108193c0e0b644cecb74ae0c7a7b54e24a75b58
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/28049
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
|
|
With commits 9987534 [southbridge/intel: Remove leftover TPM ACPI code]
and 66ce18c [soc/intel: Remove legacy static TPM asl code] removing
TPM ASL code from the southbridge's LPCB device, the LPC TPM chip driver
(drivers/pc80/tpm) must be added to devicetree in order to ensure the
new acpigen code is used to replace it.
Test: boot various google/samsung boards, verify SSDT created with
LPBC.TPM device and TPM visible to and usable by SeaBIOS and Linux
Change-Id: Iedaa01f26fb357914549bb3dda24b0bd6ef67480
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/27786
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
As per the ACPI specification, there are two types of power button
devices:
1. Fixed hardware power button
2. Generic hardware power button
Fixed hardware power button is added by the OSPM if POWER_BUTTON flag
is not set in FADT by the BIOS. This device has its programming model
in PM1x_EVT_BLK. All ACPI compliant OSes are expected to add this
power button device by default if the power button FADT flag is not
set.
On the other hand, generic hardware power button can be used by
platforms if fixed register space cannot be used for the power button
device. In order to support this, power button device object with HID
PNP0C0C is expected to be added to ACPI tables. Additionally,
POWER_BUTTON flag should be set to indicate the presence of control
method for power button.
Chrome EC mainboards implemented the generic hardware power button in
a broken manner i.e. power button object with HID PNP0C0C is added to
ACPI however none of the boards set POWER_BUTTON flag in FADT. This
results in Linux kernel adding both fixed hardware power button as
well as generic hardware power button to the list of devices present
on the system. Though this is mostly harmless, it is logically
incorrect and can confuse any userspace utilities scanning the ACPI
devices.
This change gets rid of the generic hardware power button from all
google mainboards and relies completely on the fixed hardware power
button.
BUG=b:110913245
TEST=Verified that fixed hardware power button still works correctly
on nautilus.
Change-Id: I733e69affc82ed77aa79c5eca6654aaa531476ca
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/27272
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Tested on Google peppy (Acer C720).
Change-Id: I6453c40bf4ebe4695684c1bd3a403d6def82814f
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/26835
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
|
|
* Remove 2nd software stack in pc80 drivers directory.
* Create TSPI interface for common usage.
* Refactor TSS / TIS code base.
* Add vendor tss (Cr50) directory.
* Change kconfig options for TPM to TPM1.
* Add user / board configuration with:
* MAINBOARD_HAS_*_TPM # * BUS driver
* MAINBOARD_HAS_TPM1 or MAINBOARD_HAS_TPM2
* Add kconfig TPM user selection (e.g. pluggable TPMs)
* Fix existing headers and function calls.
* Fix vboot for interface usage and antirollback mode.
Change-Id: I7ec277e82a3c20c62a0548a1a2b013e6ce8f5b3f
Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org>
Reviewed-on: https://review.coreboot.org/24903
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Change-Id: I24fd33887152c12b9db9742af475115b02b31ff2
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26622
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
|
|
Currently the throttle event handler method THRM is defined as an
extern on the intel bd82x6x and lynxpoint chipsets, then defined
again in the platform with thermal event handling. In newer versions
of IASL, this generates an error, as the method is defined in two
places. Simply removing the extern causes the call to it to fail on
platforms where it isn't actually defined, so add a preprocessor define
where it's implemented, and only call the method on those platforms.
This also requires moving the thermal handler, which now includes
the define to before the gnvs asl file.
TEST=Build before and after, make sure correct code is included.
Change-Id: I7af4a346496c1352ec20bda8acb338b5d277d99b
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/26123
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Currently the throttle event handler method THRT is defined as an extern,
then defined again in the platform with thermal event handling. In newer
versions of IASL, this generates an error, as the method is defined in
two places. Simply removing the extern causes the call to it to fail on
platforms where it isn't actually defined, so add a preprocessor define
where it's implemented, and only call the method on those platforms.
Change-Id: I6337c52edaf9350843848b31c5d87bbfca403930
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/26121
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
Use of device_t has been abandoned in ramstage.
Change-Id: I8e549e4222ae2ed6b9c46f81c5b5253e8b227ee8
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26086
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
It's very confusing trying to find the google platform names, because
they seem all unsorted in Kconfig. They're actually sorted according
to the variant name, but previously, that was impossible to tell.
- Add a comment to the top of variants in Kconfig.name
- Inset each variant name. If you start a prompt with whitespace,
it gets ignored, so after trying various ways to indent, the arrow
was the option I thought looked the best.
It now looks like this:
*** Beltino ***
-> Mccloud (Acer Chromebox CXI)
-> Monroe (LG Chromebase 22CV241 & 22CB25S)
-> Panther (ASUS Chromebox CN60)
-> Tricky (Dell Chromebox 3010)
-> Zako (HP Chromebox G1)
Butterfly (HP Pavilion Chromebook 14)
Chell (HP Chromebook 13 G1)
Cheza
*** Cyan ***
Change-Id: I35cb16b040651cd1bd0c4aef98494368ef5ca512
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/26020
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
|
|
Fix the values that were off by one.
This was discovered when using postcar stage that prints with
debuglevel BIOS_NEVER.
Change-Id: I73a077950ed0dc735d89c9747a8da0a25f30822d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/23186
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
Commit c09c2a4 [mb/google: Add Chromebook marketing names] added
marketing names for many ChromeOS devices; add some that were left out,
correct some errors, and try to format model names/numbers consistently
(or as consistently as the manufacturers allow).
Change-Id: Ia13858e2e6ba7d7e025f25fad33e6338250498e5
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/22520
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
It's sometimes hard to find the code name of a Chromebook. Add the
marketing names to Kconfig, since they are easily available.
Information (mostly) taken from:
https://www.chromium.org/chromium-os/developer-information-for-chrome-os-devices
Unknown boards (unreleased, etc.):
* Fizz
* Foster
* Nasher, Coral
* Purin
* Rotor
* Rowan
* Scarlet, Nefario
* Soraka
* Urara
* Veyron_Rialto
Baseboards:
* Glados
* Gru
* Jecht
* Kahlee
* Nyan
* Oak
* Poppy
* Rambi
* Zoombini
White label boards:
* Enguarde
* Heli
* Relm, Wizpig
TODO: How does this interact with the board_status code?
Change-Id: I20a36e23bd3eea8c526a0b3b53cd676cebf9cd86
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/22404
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
|
|
mainboard_ec_init implemented by all x86-based mainboards using
chromeec performed similar tasks for initializing and recording ec
events. Instead of duplicating this code across multiple boards,
provide a library function google_chromeec_events_init that can be
called by mainboard with appropriate inputs to perform the required
actions.
This change also adds a new structure google_chromeec_event_info to
allow mainboards to provide information required by the library
function to handle different event masks.
Also, google_chromeec_log_device_events and google_chromeec_log_events
no longer need to be exported.
Change-Id: I1cbc24e3e1a31aed35d8527f90ed16ed15ccaa86
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/21877
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
|
|
There have been discussions about removing this since it does not seem
to be used much and only creates troubles for boards without defaults,
not to mention that it was configurable on many boards that do not
even feature uart.
It is still possible to configure the baudrate through the Kconfig
option.
Change-Id: I71698d9b188eeac73670b18b757dff5fcea0df41
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19682
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
|
|
Change-Id: I8febb8d74e2463622cab0313c543ceebec71fdf4
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20705
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
Change-Id: I1f906c8c465108017bc4d08534653233078ef32d
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20343
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
|
|
Change-Id: Ie8347a3eccce51de3e938d0c3c170e59a9f74716
Signed-off-by: Ryan Salsamendi <rsalsamendi@hotmail.com>
Reviewed-on: https://review.coreboot.org/20442
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
The Chrome EC event for "thermal overload" was never implemented and
is being repurposed as the EC event mask is out of free bits.
Remove this from the boards that were enabling it.
BUG=b:36024430
TEST=build coreboot for affected boards
Change-Id: I6038389ad73cef8a57aec5041bbb9dea98ed2b6e
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/20424
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
The board dutifully registers an int15h handler and provides the
defaults to add a VGABIOS.
That should be good enough to initialize graphics through the VGABIOS
file.
Fixes build on Chrome OS configurations (at least until the Ada toolchain
situation is resolved over there).
Change-Id: I1d956b5a163b7cdf2bd467197fba95f16e5e8fa3
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/20218
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
|
|
Provide all gfx init methods as a Kconfig `choice`. This elimates the
option to select native gfx init along with running a Video BIOS. It's
been only theoretically useful in one corner case: Hybrid graphics
where only one controller is supported by native gfx init. Though I
suppose in that case it's fair to assume that one would use SeaBIOS to
run the VBIOS.
For the case that we want the payload to initialize graphics or no
pre-boot graphics at all, the new symbol NO_GFX_INIT was added to the
choice. If multiple options are available, the default is chosen as
follows:
* NO_GFX_INIT, if we add a Video BIOS and the payload is SeaBIOS,
* VGA_ROM_RUN, if we add a Video BIOS and the payload is not SeaBIOS,
* NATIVE_VGA_INIT, if we don't add a Video BIOS.
As a side effect, libgfxinit is now an independent choice.
Change-Id: I06bc65ecf3724f299f59888a97219fdbd3d2d08b
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/19814
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
MAINBOARD_FORCE_NATIVE_VGA_INIT is to be selected instead of the user
option MAINBOARD_DO_NATIVE_VGA_INIT. The distinction is necessary to
use the latter in a choice.
Change-Id: I689aa5cadea9e1091180fd38b1dc093c6938d69c
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/19813
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
Since dual-channel setups use same RAM/SPD for both channels,
populate spd_data[1] with same SPD data as spd_data[0],
allowing info for both channels to propogate into the
SBMIOS tables.
Clean up calculations using SPD length to avoid repetition.
Changes modeled after google/auron variants.
Change-Id: I7e14b35642a3fbaecaeb7d1d33b5a7c1405bac45
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/19981
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
|
|
Add capability and location data for USB ports/devices via
_PLD and _UPC ACPI methods, which is utilized by Windows and
required by macOS.
Each slippy variant has slightly different USB port config;
data for falco and leon to be added once available
Change-Id: Icc3b5b1161f62ac0b840380679acafeff363cf45
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/19967
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
Haswell, Broadwell, Baytrail, and Braswell ChromeOS devices'
FADT version were incorrectly set to 3, rather than the correct
ACPI_FADT_REV_ACPI_3_0. The incorrect value resulted in these
devices reporting compliance to ACPI 2.0, rather than ACPI 3.0.
This mirrors similar recent changes to SKL and APL SoCs.
Test: boot any affected device and check ACPI version reported
vai FADT header using OS-appropriate tools.
Change-Id: I689d2f848f4b8e5750742ea07f31162ee36ff64d
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/19498
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
|
|
The HDA verb for falco/wolf's internal mic was wrong, preventing the mic
from working properly in Windows and macOS (the Linux driver overrides
the verb table, so wasn't affected). Set the verb connector/jack bits
properly, to no connector / no jack detect, in order to fix.
Also, make (2) small non-functional fixes:
On falco, NID 0x1A was being disabled twice (instead of 0x1A and 0x1B
both being disabled - copy/paste error).
On wolf, NID 0x19 was set to an internal analog mic, where it should have
been disabled (again, copy/paste error).
Both these errors were introduced when consolidating/upstreaming
and were not present in the original Chromium sources.
Test: boot Windows [8/8.1/10] and verify mic functional with Realtek
drivers on both falco and wolf.
Change-Id: I9c343dda4762f0b1f814318c155e22c59d2da8db
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/19262
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
- remove old, buggy NGI code from falco/peppy variants
- remove superfluous INTEL_DP/INTEL_DDI configs, since already
selected by northbridge/haswell
- always use libgfxinit when use native init config selected
- enable NGI/libgfxinit for all slippy variants
The reset of the old Haswell NGI code will be cleaned up in
a subsequent patchset.
Test: select MAINBOARD_DO_NATIVE_VGA_INIT, observe panel init
using SeaBIOS and Tianocore payloads on peppy, wolf variants
Change-Id: Id5727cad7f714ffa57e77e2a25505e3c28f55237
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/18824
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
|
|
Some renamings force us to update our code:
* Scan_Ports() moved into a new package Display_Probing.
* Ports Digital[123] are called HDMI[123] now (finally!).
* `Configs_Type` became `Pipe_Configs`, `Config_Index` `Pipe_Index`.
Other noteworthy changes in libgfxinit:
* libgfxinit now knows about ports that share pins (e.g. HDMI1 and
DP1) and refuses to enable any of them if both are connected
(which is physically possible on certain ThinkPad docks).
* Major refactoring of the high-level GMA code.
Change-Id: I0ac376c6a3da997fa4a23054198819ca664b8bf0
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/18770
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
This patch attempts to finish the separation between CONFIG_VBOOT and
CONFIG_CHROMEOS by moving the remaining options and code (including
image generation code for things like FWID and GBB flags, which are
intrinsic to vboot itself) from src/vendorcode/google/chromeos to
src/vboot. Also taking this opportunity to namespace all VBOOT Kconfig
options, and clean up menuconfig visibility for them (i.e. some options
were visible even though they were tied to the hardware while others
were invisible even though it might make sense to change them).
CQ-DEPEND=CL:459088
Change-Id: I3e2e31150ebf5a96b6fe507ebeb53a41ecf88122
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/18984
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
The virtualized developer switch was invented five years ago and has
been used on every vboot system ever since. We shouldn't need to specify
it again and again for every new board. This patch flips the Kconfig
logic around and replaces CONFIG_VIRTUAL_DEV_SWITCH with
CONFIG_PHYSICAL_DEV_SWITCH, so that only a few ancient boards need to
set it and it fits better with CONFIG_PHYSICAL_REC_SWITCH. (Also set the
latter for Lumpy which seems to have been omitted incorrectly, and hide
it from menuconfig since it's a hardware parameter that shouldn't be
configurable.)
Since almost all our developer switches are virtual, it doesn't make
sense for every board to pass a non-existent or non-functional developer
mode switch in the coreboot tables, so let's get rid of that. It's also
dangerously confusing for many boards to define a get_developer_mode()
function that reads an actual pin (often from a debug header) which will
not be honored by coreboot because CONFIG_PHYSICAL_DEV_SWITCH isn't set.
Therefore, this patch removes all those non-functional instances of that
function. In the future, either the board has a physical dev switch and
must define it, or it doesn't and must not.
In a similar sense (and since I'm touching so many board configs
anyway), it's annoying that we have to keep selecting EC_SOFTWARE_SYNC.
Instead, it should just be assumed by default whenever a Chrome EC is
present in the system. This way, it can also still be overridden by
menuconfig.
CQ-DEPEND=CL:459701
Change-Id: If9cbaa7df530580a97f00ef238e3d9a8a86a4a7f
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/18980
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Instead of defining a separate LID device for mainboards using
chromeec, define EC_ENABLE_LID_SWITCH for these boards.
Change-Id: Iac58847c2055fa27c19d02b2dbda6813d6dec3ec
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/18964
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Move code common code from each variant's mainboard.asl into
common ACPI code for all variants (like google/auron). This also
adds the _PRW method for the LID0 device for falco and peppy, which
omitted the function when they were originally upstreamed.
See Chromium commit c8b41f7, falco: Add _PRW for LID0 ACPI Device
Change-Id: I7f5129340249a986f5996af37c01ccbde8d374e8
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/18368
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
Both HDMI and eDP work (simultaneously).
TESTED on Acer C720 (peppy).
Change-Id: Ifc4e3c187bcabd8965d9586237a52b440bfa7f20
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/17916
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins)
|
|
Change-Id: Ic22beaa47476d8c600e4081fc5ad7bc171e0f903
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17735
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Change-Id: Ifeef04b68760522ce7f230a51f5df354e6da6607
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17734
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Combine existing boards google/falco and google/peppy with new
ChromeOS devices leon and wolf, using their common reference board
(slippy) as a base.
Chromium sources used:
firmware-falco_peppy-4389.81.B d7703cac [falco: Add support for Samsung...]
firmware-leon-4389.61.B ea1bf55 [haswell: Enable 2x Refresh Mode]
firmware-wolf-4389.24.B 7c5a9c2 [Wolf: haswell: Add small delay before...]
Additionally, some minor cleanup/changes were made:
- I2C devices set to use ACPI (vs PCI) mode
- I2C device ACPI entries adjusted as per above
- I2C devices set to use level (vs edge) interrupt triggering
- XHCI finalization enabled in devicetree
- HDA verb entries use simplified macro entry format
Existing google/falco and google/peppy boards will be removed in a
subsequent commit.
Variant setup modeled after google/beltino
Change-Id: I087df5f98c1bb4ddd0ab24ee9ff786a9d38d87be
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/17621
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
|
