aboutsummaryrefslogtreecommitdiff
path: root/src/mainboard/google/slippy/variants/peppy
AgeCommit message (Collapse)Author
2019-12-19mb/{gizmosphere,google}: Remove unused <stdlib.h>Elyes HAOUAS
Change-Id: If99c8ea1aa437f261e8ab3c8a164d01be8bc58e9 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33893 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-08-18cpu/intel: Enter romstage without BISTKyösti Mälkki
When entry to romstage is via cpu/intel/car/romstage.c BIST has not been passed down the path for sometime. Change-Id: I345975c53014902269cee21fc393331d33a84dce Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34908 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-04-06src: Use include <delay.h> when appropriateElyes HAOUAS
Change-Id: I23bc0191ca8fcd88364e5c08be7c90195019e399 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32012 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: David Guckian
2019-03-06Remove DEFAULT_PCIEXBAR aliasKyösti Mälkki
The other DEFAULT_ entries are just immediate constants. Change-Id: Iebf4266810b8210cebabc814bba2776638d9b74d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31758 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-09-20ec/google/chromeec: Update google_chromeec_get_board_version prototypeKarthikeyan Ramasubramanian
The helper function to get the board version from EC returns 0 on failure. But 0 is also a valid board version. Update the helper function to return -1 on failure and update the use-cases. BUG=b:114001972,b:114677884,b:114677887 Change-Id: I93e8dbce2ff26e76504b132055985f53cbf07d31 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Tested-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/28576 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Jett Rink <jettrink@google.com>
2018-08-01mb/google,samsung/*: Add LPC TPM chip driver to devicetreeMatt DeVillier
With commits 9987534 [southbridge/intel: Remove leftover TPM ACPI code] and 66ce18c [soc/intel: Remove legacy static TPM asl code] removing TPM ASL code from the southbridge's LPCB device, the LPC TPM chip driver (drivers/pc80/tpm) must be added to devicetree in order to ensure the new acpigen code is used to replace it. Test: boot various google/samsung boards, verify SSDT created with LPBC.TPM device and TPM visible to and usable by SeaBIOS and Linux Change-Id: Iedaa01f26fb357914549bb3dda24b0bd6ef67480 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/27786 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-07-24Update files with no newline at the endMartin Roth
Change-Id: I8febb8d74e2463622cab0313c543ceebec71fdf4 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/20705 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-06-04google/slippy: populate PEI SPD data for all channelsMatt DeVillier
Since dual-channel setups use same RAM/SPD for both channels, populate spd_data[1] with same SPD data as spd_data[0], allowing info for both channels to propogate into the SBMIOS tables. Clean up calculations using SPD length to avoid repetition. Changes modeled after google/auron variants. Change-Id: I7e14b35642a3fbaecaeb7d1d33b5a7c1405bac45 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/19981 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-05-31google/slippy: add board-specific USB port infoMatt DeVillier
Add capability and location data for USB ports/devices via _PLD and _UPC ACPI methods, which is utilized by Windows and required by macOS. Each slippy variant has slightly different USB port config; data for falco and leon to be added once available Change-Id: Icc3b5b1161f62ac0b840380679acafeff363cf45 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/19967 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-04-14google/slippy: clean up NGI and move to libgfxinitMatt DeVillier
- remove old, buggy NGI code from falco/peppy variants - remove superfluous INTEL_DP/INTEL_DDI configs, since already selected by northbridge/haswell - always use libgfxinit when use native init config selected - enable NGI/libgfxinit for all slippy variants The reset of the old Haswell NGI code will be cleaned up in a subsequent patchset. Test: select MAINBOARD_DO_NATIVE_VGA_INIT, observe panel init using SeaBIOS and Tianocore payloads on peppy, wolf variants Change-Id: Id5727cad7f714ffa57e77e2a25505e3c28f55237 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/18824 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-02-20google/slippy: consolidate variants' common mainboard.asl codeMatt DeVillier
Move code common code from each variant's mainboard.asl into common ACPI code for all variants (like google/auron). This also adds the _PRW method for the LID0 device for falco and peppy, which omitted the function when they were originally upstreamed. See Chromium commit c8b41f7, falco: Add _PRW for LID0 ACPI Device Change-Id: I7f5129340249a986f5996af37c01ccbde8d374e8 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/18368 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-12-05Add/Combine Haswell Chromebooks using variant board schemeMatt DeVillier
Combine existing boards google/falco and google/peppy with new ChromeOS devices leon and wolf, using their common reference board (slippy) as a base. Chromium sources used: firmware-falco_peppy-4389.81.B d7703cac [falco: Add support for Samsung...] firmware-leon-4389.61.B ea1bf55 [haswell: Enable 2x Refresh Mode] firmware-wolf-4389.24.B 7c5a9c2 [Wolf: haswell: Add small delay before...] Additionally, some minor cleanup/changes were made: - I2C devices set to use ACPI (vs PCI) mode - I2C device ACPI entries adjusted as per above - I2C devices set to use level (vs edge) interrupt triggering - XHCI finalization enabled in devicetree - HDA verb entries use simplified macro entry format Existing google/falco and google/peppy boards will be removed in a subsequent commit. Variant setup modeled after google/beltino Change-Id: I087df5f98c1bb4ddd0ab24ee9ff786a9d38d87be Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/17621 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
generated by cgit v1.2.3 (git 2.39.1) at 2024-08-23 11:05:56 +0000