coreboot.git - my copy of coreboot

Age	Commit message (Collapse)	Author
2013-11-25	slippy: Add on-board devices and configure GPIO irq/wake	Duncan Laurie
	Add the onboard I2C devices for Slippy trackpad/lightsensor and generate SMBIOS Type41 tables for them. Add ACPI device for the trackpad to expose the interrupt map to the OS so it can be used. Configure interrupt GPIOs as PIRQ type and wake GPIOs as just standard input type. The wake GPIO is reconfigured as ACPI SCI in the specific device _DSW method. This prevents the wake GPIO from generating a flood of SCI at runtime. LTE_WAKE_L_Q and WLAN_WAKE_L_Q are left as ACPI SCI as these are not repurposed interrupt pins so they are not generated at runtime. SIM_DET and ALS_INT_L are set as input since we don't have an interrupt handler for them. tested on slippy with trackpad with additional kernel changes to chromeos_laptop.c to initialize devices. 1) Ensure trackpad interrupt is functional and that there is not a flood of ACPI SCI when trackpad does interrupt: 9: 1 0 0 0 IO-APIC-fasteoi acpi 37: 421 0 0 0 IO-APIC-fasteoi cyapa 2) Ensure that devices are exposed as wake capable: Device S-state Status Sysfs node TPAD S3 enabled pnp:00:00 TSCR S3 disabled pnp:00:01 3) Ensure that trackpad can wake from S3 by default, but that it does not cause an immediate wake when entering suspend. 4) Ensure that trackpad can be disabled as a wake source with echo TPAD > /proc/acpi/wakeup Change-Id: Id562d20b54eeefec56040b8f70ef238911312628 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/56622 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4190 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-11-24	slippy: Update interrupt routing	Duncan Laurie
	The SerialIO devices have specific requirements for PCI interrupt mode to use PIRQ{E,F,G,H} that are not being met. D21:F0 uses PIRQE, which must not be shared with other PCH D21:F1-F6 share PIRQF, which must not be shared with other PCH D23:F0 uses PIRQH, which must not be shared with other PCH - Fix D20IR -> D20IP typo - Remove D25/EHCI2 as it does not exist - Reorder other interrupts to clear PIRQE/PIRQF/PIRQH Check device interrupts in the kernel 0: IO-APIC-edge timer 1: IO-APIC-edge i8042 8: IO-APIC-edge rtc0 9: IO-APIC-fasteoi acpi 16: IO-APIC-fasteoi ath9k 18: IO-APIC-fasteoi i801_smbus 19: IO-APIC-fasteoi ehci_hcd:usb1 21: IO-APIC-fasteoi i2c-designware-pci--1, i2c-designware-pci--1 40: PCI-MSI-edge PCIe PME 41: PCI-MSI-edge i915 42: PCI-MSI-edge ahci 43: PCI-MSI-edge xhci_hcd 44: PCI-MSI-edge snd_hda_intel Change-Id: Id4c08d11d2860f270c6387138acdc7d3d83a85b5 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/56028 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4176 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-11-24	slippy: Initial mainboard commit	Duncan Laurie
	Change-Id: I33876b90902d4a08d760eb482b08ba41be6e3695 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/49531 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4147 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>