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2020-09-23treewide: rename GENERIC_SPD_BIN to HAVE_SPD_BIN_IN_CBFSMichael Niewöhner
The name GENERIC_SPD_BIN doesn't reflect anymore what that config is used for, so rename it to HAVE_SPD_BIN_IN_CBFS. Change-Id: I4004c48da205949e05101039abd4cf32666787df Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45147 Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-09-06mb: remove duplicated Make code for spd.bin generationMichael Niewöhner
Drop duplicated code for spd.bin generation that is provided globally in lib/Makefile.inc. For all affected boards it has been verified that the output binary functionally matches the original one. The changed execution order of Make instructions influenced the cbfs file order. Hence, the rom images can't be compared directly. Thus, the output files of the two timeless abuild runs have been compared. Further, it was verified that the final files in cbfs stay identical, by comparing the extracted cbfs of each board. The boards (possibly) needing modification could be found with something like this (with false positives, though): find src/mainboard -name Makefile.inc | \ xargs egrep 'SPD_BIN|SPD_DEPS' | cut -d: -f1 | sort -u Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Change-Id: Icd3ac0fd6c901228554115c6350d88bb49874587 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44774 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-09-04mb/*/Kconfig: Drop redundant 'select CPU_INTEL_HASWELL'Elyes HAOUAS
CPU_INTEL_HASWELL is already selected at nb/intel/haswell/Kconfig. Change-Id: I608286aae72bc740be642a72109472fb235f37bf Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44976 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-12haswell: Introduce ENABLE_DDR_2X_REFRESH Kconfig optionAngel Pons
This Kconfig symbol allows doubling the memory's refresh rate, assuming that the MRC actually cares about it. It is disabled by default except on the mainboards which explicitly enabled this setting in `pei_data`. Change-Id: I6318dad0350d1c506c67f9d117d0ae8dad871281 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43122 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
2020-06-19Kconfig: Escape variable to accommodate new Kconfig versionsPatrick Georgi
Kconfig 4.17 started using the $(..) syntax for environment variable expansion while we want to keep expansion to the build system. Older Kconfig versions (like ours) simply drop the escapes, not changing the behavior. While we could let Kconfig expand some of the variables, that only splits the handling in two places, making debugging harder and potentially messing with reproducible builds (e.g. when paths end up in configs), so escape them all. Change-Id: Ibc4087fdd76089352bd8dd0edb1351ec79ea4faa Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42481 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
2020-06-15haswell boards: Factor out MAX_CPUSAngel Pons
ULT only has 4 threads, but we are not changing it here to preserve binary reproducibility. Change-Id: I041c5dff2de514244f9c919c4c475cca979c34ce Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41842 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-31mb/google/slippy: Convert variants to use override devicetreeMatt DeVillier
Since the variants' devicetrees are almost identical, convert to using an overridetree setup for simplicity. Test: build all slippy variants, compare generated static.c to ensure resulting generated contents unchanged (although layout will) Change-Id: If237fad38a1bccfb8e51edfae3ecb75d05ade240 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39919 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-11-23Kconfig: comply to Linux 5.3's Kconfig language rulesPatrick Georgi
Kconfig became stricter on what it accepts, so accomodate before updating to a new release. Change-Id: I92a9e9bf0d557a7532ba533cd7776c48f2488f91 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37156 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2019-10-03mb/[google/intel]/*: Specify Chrome EC bus - LPC or ESPIMartin Roth
Previously all boards using eSPI for the Chrome EC just called it LPC as the code for the chrome EC is the same between the two busses. I'm adding a new Kconfig symbol to specify eSPI, so switch the boards that actually use eSPI to that symbol and add the LPC symbol to all the others. The EC_GOOGLE_CHROMEEC_LPC symbol will no longer default to enabled for x86 platforms, so one symbol or the other needs to be specified for each platform. BUG=b:140055300 TEST=Build tested only. Change-Id: Icf242ca2b7d8b1470feda4e44b47a2cdc20680f2 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35153 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-09-30mb: remove test-only HWIDsHung-Te Lin
The CONFIG_GBB_HWID can be generated automatically now so we can remove the test-only HWIDs set in board config files. BUG=b:140067412 TEST=Built few boards (kukui, cheza, octopus) and checked HWID: futility gbb -g coreboot.rom Change-Id: I4070f09d29c5601dff1587fed8c60714eb2558b7 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35635 Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-28google/leon: Add DRIVERS_I2C_RTD2132Kyösti Mälkki
This is LVDS bridge, I assume this was lost while upstreaming or converting boards to variants. Change-Id: I816a6b4035c4e935150cc77089c4224eee719c10 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35106 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2019-05-29mb/google/{misc}: set default SMBIOS manufacturerMatt DeVillier
Legacy Google mainboards (pre-Skylake) shipped with the SMBIOS manufacturer set to GOOGLE, which many Linux drivers rely on for application of DMI quirks. Set it as the default to avoid having to do so for each board's config Change-Id: I61b0217f3535852d7d6e24a1ac78075c20c0825a Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33027 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-01-06mb/google/slippy: Add a VBT for all variantsArthur Heymans
The vbt was extracted from the option rom found on stock images. The vbt.bin is the same across all variants. The VBT has a modified BDB block 43, the 'Backlight info block' such that the inverter type for the panel in use is set to 2 (BDB_BACKLIGHT_TYPE_PWM) instead of 0 (BDB_BACKLIGHT_TYPE_NONE). This only seems to matter on Windows, as without it changing the backlight duty cycle does not work. Change-Id: I82c72c561e1058e0b77d80baf330b64f7c6b08e3 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/30487 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-03sb/intel/lynxpoint: Move `HAVE_SMI_HANDLER` to southbridge KconfigTristan Corrick
All Lynx Point board select this, and none build without it. Change-Id: I4b59b10ee985cff5a8e1442677d36b0be88cf437 Signed-off-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-on: https://review.coreboot.org/c/29992 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-11-21nb/intel/haswell: Move MMCONF_BASE_ADDRESS to northbridge KconfigElyes HAOUAS
Change-Id: I44f27405fc8ccbe54c7d19b70327da866390a156 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/28603 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
2018-11-16mb/*/*/Kconfig: Use CONFIG_VARIANT_DIR for devicetreePeter Lemenkov
Change-Id: Ic9620cfa1630c7c085b6c244ca80dc023a181e30 Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/29595 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2018-08-13sb/intel/lynxpoint/Kconfig: Clean up redefined config optionsArthur Heymans
There is no need to redefine option present in southbridge/intel/common/firmware/Kconfig. Change-Id: I9999440031b07006e2df11e00dfb9f3dbe04f832 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/28007 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-04security/tpm: Unify the coreboot TPM software stackPhilipp Deppenwiese
* Remove 2nd software stack in pc80 drivers directory. * Create TSPI interface for common usage. * Refactor TSS / TIS code base. * Add vendor tss (Cr50) directory. * Change kconfig options for TPM to TPM1. * Add user / board configuration with: * MAINBOARD_HAS_*_TPM # * BUS driver * MAINBOARD_HAS_TPM1 or MAINBOARD_HAS_TPM2 * Add kconfig TPM user selection (e.g. pluggable TPMs) * Fix existing headers and function calls. * Fix vboot for interface usage and antirollback mode. Change-Id: I7ec277e82a3c20c62a0548a1a2b013e6ce8f5b3f Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: https://review.coreboot.org/24903 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-06-16google/slippy: Don't force native graphics initPatrick Georgi
The board dutifully registers an int15h handler and provides the defaults to add a VGABIOS. That should be good enough to initialize graphics through the VGABIOS file. Fixes build on Chrome OS configurations (at least until the Ada toolchain situation is resolved over there). Change-Id: I1d956b5a163b7cdf2bd467197fba95f16e5e8fa3 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/20218 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2017-06-08device/Kconfig: Put gfx init methods into a `choice`Nico Huber
Provide all gfx init methods as a Kconfig `choice`. This elimates the option to select native gfx init along with running a Video BIOS. It's been only theoretically useful in one corner case: Hybrid graphics where only one controller is supported by native gfx init. Though I suppose in that case it's fair to assume that one would use SeaBIOS to run the VBIOS. For the case that we want the payload to initialize graphics or no pre-boot graphics at all, the new symbol NO_GFX_INIT was added to the choice. If multiple options are available, the default is chosen as follows: * NO_GFX_INIT, if we add a Video BIOS and the payload is SeaBIOS, * VGA_ROM_RUN, if we add a Video BIOS and the payload is not SeaBIOS, * NATIVE_VGA_INIT, if we don't add a Video BIOS. As a side effect, libgfxinit is now an independent choice. Change-Id: I06bc65ecf3724f299f59888a97219fdbd3d2d08b Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/19814 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-06-08device/Kconfig: Introduce MAINBOARD_FORCE_NATIVE_VGA_INITNico Huber
MAINBOARD_FORCE_NATIVE_VGA_INIT is to be selected instead of the user option MAINBOARD_DO_NATIVE_VGA_INIT. The distinction is necessary to use the latter in a choice. Change-Id: I689aa5cadea9e1091180fd38b1dc093c6938d69c Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/19813 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-04-14google/slippy: clean up NGI and move to libgfxinitMatt DeVillier
- remove old, buggy NGI code from falco/peppy variants - remove superfluous INTEL_DP/INTEL_DDI configs, since already selected by northbridge/haswell - always use libgfxinit when use native init config selected - enable NGI/libgfxinit for all slippy variants The reset of the old Haswell NGI code will be cleaned up in a subsequent patchset. Test: select MAINBOARD_DO_NATIVE_VGA_INIT, observe panel init using SeaBIOS and Tianocore payloads on peppy, wolf variants Change-Id: Id5727cad7f714ffa57e77e2a25505e3c28f55237 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/18824 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-03-28vboot: Move remaining features out of vendorcode/google/chromeosJulius Werner
This patch attempts to finish the separation between CONFIG_VBOOT and CONFIG_CHROMEOS by moving the remaining options and code (including image generation code for things like FWID and GBB flags, which are intrinsic to vboot itself) from src/vendorcode/google/chromeos to src/vboot. Also taking this opportunity to namespace all VBOOT Kconfig options, and clean up menuconfig visibility for them (i.e. some options were visible even though they were tied to the hardware while others were invisible even though it might make sense to change them). CQ-DEPEND=CL:459088 Change-Id: I3e2e31150ebf5a96b6fe507ebeb53a41ecf88122 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/18984 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-28vboot: Assume EC_SOFTWARE_SYNC and VIRTUAL_DEV_SWITCH by defaultJulius Werner
The virtualized developer switch was invented five years ago and has been used on every vboot system ever since. We shouldn't need to specify it again and again for every new board. This patch flips the Kconfig logic around and replaces CONFIG_VIRTUAL_DEV_SWITCH with CONFIG_PHYSICAL_DEV_SWITCH, so that only a few ancient boards need to set it and it fits better with CONFIG_PHYSICAL_REC_SWITCH. (Also set the latter for Lumpy which seems to have been omitted incorrectly, and hide it from menuconfig since it's a hardware parameter that shouldn't be configurable.) Since almost all our developer switches are virtual, it doesn't make sense for every board to pass a non-existent or non-functional developer mode switch in the coreboot tables, so let's get rid of that. It's also dangerously confusing for many boards to define a get_developer_mode() function that reads an actual pin (often from a debug header) which will not be honored by coreboot because CONFIG_PHYSICAL_DEV_SWITCH isn't set. Therefore, this patch removes all those non-functional instances of that function. In the future, either the board has a physical dev switch and must define it, or it doesn't and must not. In a similar sense (and since I'm touching so many board configs anyway), it's annoying that we have to keep selecting EC_SOFTWARE_SYNC. Instead, it should just be assumed by default whenever a Chrome EC is present in the system. This way, it can also still be overridden by menuconfig. CQ-DEPEND=CL:459701 Change-Id: If9cbaa7df530580a97f00ef238e3d9a8a86a4a7f Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/18980 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-20mb/google/slippy: Hook up libgfxinitArthur Heymans
Both HDMI and eDP work (simultaneously). TESTED on Acer C720 (peppy). Change-Id: Ifc4e3c187bcabd8965d9586237a52b440bfa7f20 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/17916 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins)
2016-12-05Add/Combine Haswell Chromebooks using variant board schemeMatt DeVillier
Combine existing boards google/falco and google/peppy with new ChromeOS devices leon and wolf, using their common reference board (slippy) as a base. Chromium sources used: firmware-falco_peppy-4389.81.B d7703cac [falco: Add support for Samsung...] firmware-leon-4389.61.B ea1bf55 [haswell: Enable 2x Refresh Mode] firmware-wolf-4389.24.B 7c5a9c2 [Wolf: haswell: Add small delay before...] Additionally, some minor cleanup/changes were made: - I2C devices set to use ACPI (vs PCI) mode - I2C device ACPI entries adjusted as per above - I2C devices set to use level (vs edge) interrupt triggering - XHCI finalization enabled in devicetree - HDA verb entries use simplified macro entry format Existing google/falco and google/peppy boards will be removed in a subsequent commit. Variant setup modeled after google/beltino Change-Id: I087df5f98c1bb4ddd0ab24ee9ff786a9d38d87be Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/17621 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-07-27mainboard/google/slippy: remove unobtainable mainboardAaron Durbin
The slippy board was a proof of concept device that has never made it out in the wild. Moreover, I don't think any of these boards exist any longer. Change-Id: I24fb08d9be35b2367e7aa64520ce5778ab861535 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15902 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-02-12chromebooks: Define GBB hardware IDsPatrick Georgi
This makes the test IDs the default, taken from depthcharge master (board/*/fmap.dts, hwid property). Change-Id: I25793962ac16f451f204dbba6ede6a64c847cfd5 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/13634 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins)
2015-08-26ChromeOS mainboards: Move more Kconfig symbols under CHROMEOSMartin Roth
Move the CHROMEOS dependent symbols VIRTUAL_DEV_SWITCH and VBOOT_DYNAMIC_WORK_BUFFER under the CHROMEOS config options for the mainboards that use them. Change-Id: Iad126cf045cb3a312319037aff3c4b1f15f6529d Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: http://review.coreboot.org/11336 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2015-08-21ChromeOS: Fix Kconfig dependenciesMartin Roth
Add CHROMEOS dependencies to selects for the following Kconfig symbols: CHROMEOS_RAMOOPS_DYNAMIC CHROMEOS_RAMOOPS_NON_ACPI CHROMEOS_VBNV_CMOS CHROMEOS_VBNV_EC CHROMEOS_VBNV_FLASH EC_SOFTWARE_SYNC LID_SWITCH RETURN_FROM_VERSTAGE SEPARATE_VERSTAGE VBOOT_DISABLE_DEV_ON_RECOVERY VBOOT_EC_SLOW_UPDATE VBOOT_OPROM_MATTERS VBOOT_STARTS_IN_BOOTBLOCK WIPEOUT_SUPPORTED This gets rid of these sorts of Kconfig errors: warning: BOARD_SPECIFIC_OPTIONS selects CHROMEOS_VBNV_EC which has unmet direct dependencies (MAINBOARD_HAS_CHROMEOS && CHROMEOS) Note: These two boards would never actually have CHROMEOS enabled: intel/emeraldlake2 has MAINBOARD_HAS_CHROMEOS commented out google/peach_pit doesn't have MAINBOARD_HAS_CHROMEOS Change-Id: I51b4ee326f082c6a656a813ee5772e9c34f5c343 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: http://review.coreboot.org/11272 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-06-30Add Kconfig flag to specify if there's a lid switchPatrick Georgi
Not all devices have a lid switch, so we need to state this somehow. Since the alternative would be to extend get_lid_switch()'s semantics to become a tri-state (open, closed, N/A), do this through Kconfig. BRANCH=none BUG=chromium:446945 TEST=none Change-Id: Icc50f72535f256051a59925a178fb27b2e8f7e55 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: d20a1d1a22d64546a5d8761b18ab29732ec0b848 Original-Change-Id: Ie8ac401fbaad5b5a9f1dec2b67847c81f4cc94aa Original-Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/273850 Original-Reviewed-by: Stefan Reinauer <reinauer@chromium.org> Original-Tested-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Queue: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10692 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-06-24Kconfig: Get rid of obsolete symbolsMartin Roth
CAR_MIGRATION was removed in commit: cbf5bdfe - CBMEM: Always select CAR_MIGRATION ALT_CBFS_LOAD_PAYLOAD was removed in commit: cf6c9cc2 - Kill ALT_CBFS_LOAD_PAYLOAD MARK_GRAPHICS_MEM_WRCOMB was removed in commit: 30fe6120 - MTRR: Mark all prefetchable resources as WRCOMB. EXTERNAL_MRC_BLOB was removed in commit: 0aede118 - Drop unused EXTERNAL_MRC_BLOB CACHE_ROM is only in Google's codebase. LID_SWITCH is only in Google's codebase. DEFAULT_POST_DEVICE_LPC is only in Sage's codebase. ROMSTAGE_RTC_INIT is only in Sage's codebase, or was never used. HUDSON_NOT_LEGACY_FREE never existed as far as I can tell. MAINBOARD_DO_EDID never existed as far as I can tell. Change-Id: I636ea7584fb47885638dbcd9ccedfafb1ca2c640 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: http://review.coreboot.org/10616 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-05-27Move TPM code out of chromeosVladimir Serbinenko
This code is not specific to ChromeOS and is useful outside of it. Like with small modifications it can be used to disable TPM altogether. Change-Id: I8c6baf0a1f7c67141f30101a132ea039b0d09819 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/10269 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-05-19intel/haswell: Drop MONOTONIC_TIMER_MSRPatrick Georgi
The variable was set on all haswell boards, so we can do it like on broadwell where the MSR based timer is assumed to be around, too. Change-Id: Id48ad7454d4cf83c3b1616b64687cdcfee4baa10 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10256 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2015-04-30cpu/intel/haswell: remove dependency on socket_rpga989Matt DeVillier
Remove dependency of Haswell on cpu/intel/socket_rpga989 code, which is a carry-over from Sandy Bridge/Ivy Bridge and older coreboot conventions where features were structured around socket types. Add CPU-specific options to Kconfig and required subdirs to Makefile.inc which are curently included with socket_rpga989. TEST=successfully built and booted on google/panther Change-Id: Ic788e2928df107d11ea2d2eca7613490aaed395c Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: http://review.coreboot.org/10037 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-04-28boards: remove VBOOT_(REFCODE|RAMSTAGE|ROMSTAGE)_INDEXAaron Durbin
These options will need to just be selected in within the .config files. There's not need in duplicating all these options. Change-Id: I7b670bc59a3b35e39eee4faecaf4aa779d47a3bb Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9959 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-22mainboards: Add CHROMEOS_VBNV_* where appropriatePatrick Georgi
For boards with MAINBOARD_HAS_CHROMEOS, we should also state what kind of storage is available for vboot's non-volatile data. The flags are taken from the chromium repository and have no effect with CHROMEOS disabled. Change-Id: I1747ad26c8c7f6d4076740ec2800dbd52c5d6b3d Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/9952 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2014-12-06Remove IRQ_SLOT_COUNT on all boards without PIRQ table.Vladimir Serbinenko
This config is used only to generate PIRQ table. If no such table is supplied there is no need for config. Change-Id: I537d440f53019a6bf7f190446074e75e7420545a Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7566 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins)
2014-09-08Haswell/falco/peppy/slippy: continue to clean up FUI.Ronald G. Minnich
As a first step towards removing hardcodes from the FUI support, change the haswell call to i915_lightup to panel_lightup, and pass the intel_dp * as a parameter. Get rid of the scalar arguments and make them part of intel_dp. Get rid of file-scope variables and use the ones in the intel_dp struct. In falco, use functions that peppy uses. Drop slippy support for FUI, it's a dead board; if this is ok I'll remove the files next. And, incidentally, fix the broken RGBX constant and change it to BGRX. Change-Id: I46ef5a9ed8433382d042066ee3542af04cfc319a Signed-off-by: Ronald G. Minnich <rminnich@google.com> Reviewed-on: https://chromium-review.googlesource.com/174932 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Commit-Queue: Ronald Minnich <rminnich@chromium.org> Tested-by: Ronald Minnich <rminnich@chromium.org> (cherry picked from commit 1e1ed410b445c8e2b7411e163d9d6f61499dc3f6) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6833 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2014-09-05Consolidate intel vga int15 hooksVladimir Serbinenko
Change-Id: I9366dded98bf15f6da44ce893dd10698ba09fd55 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6820 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-07-05Intel Lynx Point boards: Kconfig: Add `HAVE_ME_BIN`Paul Menzel
Change-Id: Ib7d2a5c14675427fe9556a6b81ed5397f17937d8 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/6049 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-07-05Intel Lynx Point boards: Kconfig: Add `HAVE_IFD_BIN`Paul Menzel
Change-Id: I0ea09d75cb05687407fb152642578e19824d1c4c Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/6048 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-03Move ARCH_* from board/Kconfig to cpu or soc Kconfig.Furquan Shaikh
CONFIG_ARCH is a property of the cpu or soc rather than a property of the board. Hence, move ARCH_* from every single board to respective cpu or soc Kconfigs. Also update abuild to ignore ARCH_ from mainboards. Change-Id: I6ec1206de5a20601c32d001a384a47f46e6ce479 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: http://review.coreboot.org/5570 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-02-25Remove CACHE_ROM.Vladimir Serbinenko
With the recent improvement 3d6ffe76f8a505c2dff5d5c6146da3d63dad6e82, speedup by CACHE_ROM is reduced a lot. On the other hand this makes coreboot run out of MTRRs depending on system configuration, hence screwing up I/O access and cache coherency in worst cases. CACHE_ROM requires the user to sanity check their boot output because the feature is brittle. The working configuration is dependent on I/O hole size, ram size, and chipset. Because of this the current implementation can leave a system configured in an inconsistent state leading to unexpected results such as poor performance and/or inconsistent cache-coherency Remove this as a buggy feature until we figure out how to do it properly if necessary. Change-Id: I858d78a907bf042fcc21fdf7a2bf899e9f6b591d Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/5146 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-02-06MTRR: Mark all prefetchable resources as WRCOMB.Vladimir Serbinenko
Change-Id: I2ecfd9733b65b6160bc2232d22db7b16692a847f Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/5149 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-12-21SLIPPY: final changes for FUIRonald G. Minnich
The intel_ddi.c change I thought should be in but I don't see it. It just adds two functions back that we need. There are two new files for slippy annotated with comments about how it needs to evolve. That said, this code has been tested on 3 different panels. Both dev and non-dev usages work. physbase initialization to static value removed. Moved spin calls to intel_dp_* Change-Id: I0480af45c21c7dedcaff7e8be729f0eb554ec78a Signed-off-by: Ronald G. Minnich <rminnich@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/61136 Commit-Queue: Ronald G. Minnich <rminnich@chromium.org> Reviewed-by: Ronald G. Minnich <rminnich@chromium.org> Tested-by: Ronald G. Minnich <rminnich@chromium.org> Reviewed-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/4370 Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Tested-by: build bot (Jenkins)
2013-12-03haswell boards: Enable VIRTUAL_DEV_SWITCHDuncan Laurie
This config option was not enabled which was preventing the user from enabling developer mode from recovery mode. With this enabled we can disable the "dev mode by default" behavior and let people enable it by entering recovery mode. This will make the firmware behave like a typical chromeos device. Peppy is left in "default dev mode" until after bringup. 1) boot slippy in normal mode by default 2) enter recovery mode with servo button 3) Ctrl+D on USB keyboard to enter developer mode 4) boot slippy in developer mode Change-Id: I414c0d10dd0489e3c89798f75a2872a43297c8d8 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/57350 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4220 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-12-02Add option to disable ChromeOSKyösti Mälkki
Those building Chromebook firmware from coreboot git might be more interested in building without ChromeOS extras. Change-Id: I2f176d059fd45bf4eb02cc0f3f1dcc353095d0ce Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3977 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-11-26slippy/falco: Re-enable EC software syncDuncan Laurie
The EC was disabling flash commands and sysjump was not working properly. With those two fixed software sync works properly. Google Chrome EC MKBP driver ready, id 'slippy_no_version' Clearing the recovery request. EC hash:7fea29992ef72e3e64d8ffe522aa1dfa68dcb44a2da96a4c19530ea1a0bd22c4 EC-RW hash address, size are 0xffa1cfe8, 32. Hash = 727e79934d9394184da496cebc27f7275b9d2d91079bf125d8f977a1f8aa4cde Expected hash:727e79934d9394184da496cebc27f7275b9d2d91079bf125d8f977a1f8aa4cde EC-RW firmware address, size are 0xffad000c, 57180. VbEcSoftwareSync() - expected len = 57180 Computed hash of expected image:727e79934d9394184da496cebc27f7275b9d2d91079bf125d8f977a1f8aa4cde VbEcSoftwareSync() updating EC-RW... VbEcSoftwareSync() jumping to EC-RW VbEcSoftwareSync() in RW; done Change-Id: I63ca00d6c94854f2b395eb736ce20792da5f8de2 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/56821 Reviewed-on: http://review.coreboot.org/4208 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2013-11-25slippy: Minor vboot related fixesDuncan Laurie
- Disable EC software sync for now - Report correct EC active firmware mode - Force enable developer mode by default - Set up PCH generic decode regions in romstage - Pass the oprom_is_loaded flag into vboot handoff data Change-Id: Ib7ab35e6897c19455cbeecba88160ae830ea7984 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/51155 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4169 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-11-24haswell: enable monotonic timerAaron Durbin
For all the current haswell boards enable the monotonic timer. The ULT boards use the 24MHz MSR while the non-ULT boards use the local apic. Change-Id: I8b19f526a5a49e8467f296c566a2c4263bc5a863 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/49763 Reviewed-by: Stefan Reinauer <reinauer@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/4148 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-11-24slippy: Initial mainboard commitDuncan Laurie
Change-Id: I33876b90902d4a08d760eb482b08ba41be6e3695 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/49531 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4147 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
generated by cgit v1.2.3 (git 2.39.1) at 2024-07-03 02:23:50 +0000