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ABL generates memory training data whose size is ~80KiB. So increase the
RW_MRC_CACHE region size to accommodate that.
BUG=b:224618411
TEST=Build and boot to payload in Skyrim.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: Id2040026a1fe2b3f760724023e2e252e137b31c8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63033
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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Backlight GPIO was set to HIGH, when it should have been set LOW to
enable the backlight in the embedded display.
BUG=b:224618411
TEST=load on Skyrim proto1, observe backlight
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: Ife3335ca5a3c2517a6817fccf0544e5fcacb1f9d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63003
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Right now, the PSPP policy that controls if the PCIe lanes can be
dynamically downgraded to a lower speed to save some power needs to be
disabled in order for the link training to be successful. Once this
feature is working, PSPP will be reenabled.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I6ea602596acb8e5ea92076386e80102c3bc757af
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62924
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
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BUG=b:224618411
TEST=util/abuild/abuild -t GOOGLE_SKYRIM with and without APCB
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I71b30a5716f2e0d60d07a0ec29f98609c1f2a8b7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62877
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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Needed so i2c communication works.
BUG=b:224618411
TEST=build skyrim
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I8ec7c18cae509b5683cb73153fd6d3747cf9d753
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62874
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This will fix:
> [INFO ] Probing TPM I2C: tis_plat_irq_status() not implemented, wasting 20ms to wait on Cr50!
BUG=b:224618411
TEST=Compile skyrim
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I5add694506ad089adcc8961f101bf507bc39a522
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62873
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The one USB2 port on the XHCI2 controller should have the port ID 2.0,
since it's the first USB2 port on that XHCI controller.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I4a370132960939bccec4eb69a6590d0880b04137
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62713
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Configure PCIe Clk Source and Clk Request mapping. Configure GPIOs used
for WLAN. Mappping derived from Skyrim schematic.
BUG=b:214412172
TEST=Builds
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: I16e35b443f741d366589fefb7fd21863369d1ec2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62165
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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GPIO 32 was not allocated correctly, updating to reflect the native
function use of the pin
BUG=b:214412172
TEST=Builds
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: Idadd2a802b3244eba8ee83f80d8f10baebe4ca40
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62717
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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BUG=b:214415048
TEST=Builds
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: Ia6bb3f717b3d30fe5f166dfc958024e931a070c8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62626
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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BUG=b:214414301
TEST=builds
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: I6b12950843f3ee3b5abe4ef9c6bd5aba528cc4ea
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62164
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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Configure D2 I2C and Interrupt GPIOs during the early initialization.
Add devicetree configuration for D2 device and enable the required
config items.
BUG=b:214414776
TEST=Build
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: I57b6d0e9da9935596e54b8eab400440e518b4523
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62163
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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BUG=b:214413613
TEST=builds
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: If1177dda705738222ce7f6f42dceafb14d37c98c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62162
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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BUG=b:214417045
TEST=builds
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: I6de1e4877323e18ec9d95f182c7d3fccd51d4998
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62161
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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Add I2C peripheral reset configuration required during early init.
Enabled I2C generic and HID drivers.
BUG=b:214414677
TEST=Build
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: I06e564cf6eca844101d70ff865f3074b45a55d55
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62160
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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BUG=b:214414851
TEST=builds
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: Ic427f88fee7739b064a8836e07841c80c99212a3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62154
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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The USB port configuration was derived from the PPR and schematics.
This board has 6(some multi-purpose) ports.
Primary functions are:
2 USB-C ports
1 USB SS+ type A port
2 Cameras
1 Bluetooth transceiver
BUG=b:214413631
TEST=builds
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: Ie1b05f190f25dca1566e1023011cc70c2d32f461
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62153
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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BUG=b:214413631
TEST=builds
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: I9ca2c16d97e064b32400356e1de37f3f70155a07
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62152
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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BUG=b:214416935
TEST=builds
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: Icc71b114bf9d8f70ae38a876eedc9d1c3c02169c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62151
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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BUG=b:214414501
TEST=builds
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: I053909ab73c1aa053f35a505b37571ff23adde89
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62147
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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BUG=b:214415048
TEST=builds
BRANCH=none
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: Ida8d226f84726f2eb03b07618907b0ce3928bec5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62146
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Enable ESPI SCI events
BUG=b:214416630
TEST=builds
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: If47ba561f140eb474cad30e24b0a7c85cdd76203
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62149
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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BUG=b:214415408
TEST=builds
BRANCH=none
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: Icc52182294bb3402463a0a70a5c67779c60dfe32
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62045
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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BUG=b:214413613
TEST=builds
BRANCH=none
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: I15c7c482c4a5ddef22a221794b9ef03f9b7ffe05
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62046
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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BUG=b:214414033
TEST=builds
BRANCH=none
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: I034ab8a06842bee12060103b4a1bc4e3db69e42a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62145
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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BUG=b:214415401
TEST=builds
BRANCH=none
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: I045f76c366a1a72814536a2be984b7ad5a438a5a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62043
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add GPIO initialization and ACPI generation for tables
BUG=b:214415303
TEST=builds
BRANCH=none
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: I8f9c7d3f2fdbd5d791032637dbf97c18864ee9e7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62044
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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BUG=b:214415401
TEST=builds
BRANCH=none
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: I60b3b3cd50eea1253df2ae3e0aea83bb89e54702
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62042
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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BUG=b:214415401
TEST=builds
BRANCH=none
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: Ieeda9aa0c18b5befea67d2849bd4114da0c348a3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62041
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Skyrim is a new Google mainboard with AMD Sabrina SOC.
BUG=b:214413553
TEST=util/abuild/abuild -t GOOGLE_SKYRIM --clean
Change-Id: I008fea4aa163b8aa66e86735b29b3fdc4e08a327
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61565
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
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