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path: root/src/mainboard/google/sarien/variants
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2019-03-05mb/google/sarien/variants/arcada: Add GPIO H15 to enable BTCasper Chang
Follow b:123342945 to add GPIO H15(BT_RADIO_DIS#). BUG=b:123342945 TEST=Verified BT function on Arcada DVT1 system Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com> Change-Id: I260a2312d47385da3c7ec215267ff63ada04f2c5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/31705 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2019-03-01mb/google/sarien: ALC3204 HDA verb table pin config changeJoyce Toh
On Sarien, change pin config of 0x19 (headset mic) and 0x21(headset headphone) to change jack location so that naming does not use "Front" in the name."Front Headphone" --> "Headphone" so it matches naming on Arcada. BUG=b:126334749 TEST= verify with 'evtest' command that jack name is "HDA Intel PCH Headphone" not "HDA Intel PCH Front Headphone" Change-Id: I36ccf0c0a3952ab363fe6ee313fac8f0cce4dd61 Signed-off-by: Joyce Toh <joyce.toh@intel.com> Reviewed-on: https://review.coreboot.org/c/31624 Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-20mb/google/sarien/variants/sarien: Adjust TP/TS I2C CLK to meet specChris Zhou
After adjustment on Sarien EVT Touch Screen CLK (Elan): 389.7 KHz Touch Screen CLK (Melfas): 377.7 KHz Touch Pad CLK: 385 KHz BUG=b:122657195 BRANCH=master TEST=emerge-sarien coreboot chromeos-bootimage measure by scope with sarien. Signed-off-by: Chris Zhou <chris_zhou@compal.corp-partner.google.com> Change-Id: I53b60354e5a7a0ace8efb677775c0a9f8779061d Reviewed-on: https://review.coreboot.org/c/31476 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-18mb/google/sarien/variants/sarien: Update GPIO H3 for DVT1John Su
Follow b:123461432#5 to update GPIO H3(CNVI_EN#) for DVT1. Update setting GPIO H3 to output and low level. BUG=b:123461432 TEST=Built and tested on sarien system Change-Id: I6a56df9a7bf75f49133a646312ae5093c2652698 Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/31412 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2019-02-18mb/google/sarien/variants/sarien: Update thermal configuration for DPTFJohn Su
Follow thermal table (b:123383634 comment#1) for EVT1 tunning. BUG=b:123383634 TEST=Built and tested on sarien system Change-Id: I22908e4bf39aedb8cf31a9060084f6f36bff56ca Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/31170 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2019-02-18mb/google/sarien: Create VR config settingsRoy Mingi Park
Create VR settings configuration as per board design. BUG=N/A TEST=Build and boot up into sarien platform. Change-Id: Ic196fd80e5211bd5146158d4d340b52c850a4e62 Signed-off-by: Roy Mingi Park <roy.mingi.park@intel.com> Reviewed-on: https://review.coreboot.org/c/31404 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2019-02-18mb/google/sarien/variants/arcada: Update thermal configuration for DPTFCasper Chang
Update dptf for arcada EVT. BUG=b:123924662 TEST=Built and tested on arcada system Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com> Change-Id: Ieed8021b83776fdb6320ff89b57c8d2747667fd5 Reviewed-on: https://review.coreboot.org/c/31331 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2019-02-15mb/google/sarien/variants/sarien: Enable Elan touchscreenChris Zhou
Eanble Elan touch for sarien EVT build BUG=b:119763054 BRANCH=master TEST=Verify touchscreen on sarien works with this change. Signed-off-by: Chris Zhou <chris_zhou@compal.corp-partner.google.com> Change-Id: I790436338705fc9d68f714245e9b9bb518ddb30a Reviewed-on: https://review.coreboot.org/c/31413 Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-13mb/google/sarien: Support multiple touchscreen at same addressDuncan Laurie
The Sarien board may have different touchscreen devices that use the same I2C slave address but have different requirements such as needing a special driver or ACPI configuration. In order to support this the devicetree may be configured with multiple devices at the same address and at boot time the unused devices will be disabled. Because there is no GPIO for selecting the device that is present it can instead be selected with Kconfig, or by setting a VPD key to the HID of the touchscreen device that is present. The default for Sarien devices is to not enable a touchscreen for the OS. The touchscreen selection is currently limited to the Sarien variant but this also adds the touchscreen HID for Arcada to Kconfig so it would not complain about the key not being set. BUG=b:122019253 TEST=This was tested on a Sarien board by adding a second entry to the devicetree at the same address. Without this change the SSDT is not loaded by the kernel because of the address conflict. After this change no touchscreen is enabled by default, but one can be selected with Kconfig or by setting the 'touchscreen_hid' VPD key. Change-Id: I4da12b1de0c551bcd89325fe0d8c66c6ffeb7afc Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/31295 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-02-13mb/google/sarien/variants/sarien: Add GPIO H3 for DVT1John Su
Follow Northbay and intermal project to add GPIO H3(CNVI_EN#) for DVT1. BUG=b:123461432 TEST=Built and tested on sarien system Change-Id: I580a6e094d84a7bada534b14c2b65ecf4b9942b0 Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/31360 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2019-02-13mb/google/sarien/variants/sarien: Add GPIO H15 for DVT1John Su
Follow b:123342945 to add GPIO H15(BT_RADIO_DIS#) for DVT1. BUG=b:123342945 TEST=Built and tested on sarien system Change-Id: I0caf97f6a2a8abf2914667350c76300733ead1b8 Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/31330 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2019-01-31mb/google/sarien: Turn on ASPM L1.2 for Card ReaderLijian Zhao
Enable ASPM L1.2 support for embedded realtek card reader, after change the power consumption for SD controller from 5mW to less than 2mW. BUG=N/A TEST=Build and boot up on Arcada platform, check the PCI configuration on pcie root port offset 0x208 is 0x0f, and offset 0x168 on card reader is also 0x0f. Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Change-Id: I08d85ee332ceee8ed85cd816bc3e6c895528fdb0 Reviewed-on: https://review.coreboot.org/c/31145 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Roy Mingi Park <roy.mingi.park@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-30mainboard/{google,intel}: Remove SaGv hard codingRonak Kanabar
Remove hard coding for SaGv config in devicetree.cb and apply macro for SaGv config for CNL variants boards Change-Id: If007589d5c1368602928b1550ec8788e65f70c05 Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/31120 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2019-01-30mb/google/sarien/variants/arcada: Adjust TP/TS/H1 I2C CLK to meet specCasper Chang
After adjustment on Arcada EVT TouchScreen: 390 KHz TouchPad: 389 KHz H1: 389 KHz BUG=b:120584026, b:120584561 BRANCH=master TEST=emerge-sarien coreboot chromeos-bootimage measure by scope Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com> Change-Id: Ia6eb332e7a664b211a5025ad07e0d01bf7f8d5bb Reviewed-on: https://review.coreboot.org/c/31124 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
2019-01-28mb/google/sarien: Using HID over I2C to enable Melf TouchScreenChris Zhou
Current Melfas touchscreen driver cannot unregister ifself when connecting without Melfas touchscreen or connecting with other devices. And Melfas touchscreen FW can use I2C and HID over I2C driver, so switch to using HID over I2C driver. BUG=b:122710830 BRANCH=master TEST=Verify touchscreen on sarien works with this change. Signed-off-by: Chris Zhou <chris_zhou@compal.corp-partner.google.com> Change-Id: If04a2904a0f72a6c8363ab2c9865926c71cb5186 Reviewed-on: https://review.coreboot.org/c/31062 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
2019-01-24mb/google/sarien/variants: Set tcc offset valueSumeet Pawnikar
Set tcc offset value to 5 degree celsius for Sarien system. BRANCH=None BUG=b:122636962 TEST=Built and tested on Sarien system Change-Id: I06fbf6a0810028458bdd28d0d8a4e3b645f279ca Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/31037 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Naresh Solanki <naresh.solanki@intel.com>
2019-01-23mb/google/sarien: Replace B0D4 with TCPUSumeet Pawnikar
Replace B0D4 with TCPU for DPTF thermal sensor. This helps to maintain consistency between coreboot and UEFI BIOS. Change-Id: I024068c19160e1c08badef3d304ada14455c045f Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/31028 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-23mb/google/arcada: Add settings for noise mitgationCasper Chang
Enable acoustic noise mitgation for arcada platform, the slow slew rates are fast time dived by 2. BUG=none BRANCH=none TEST=none Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com> Change-Id: Ia838818a76a7f638b24146f3eb48493a4091c9cb Reviewed-on: https://review.coreboot.org/c/coreboot/+/31034 Reviewed-on: https://review.coreboot.org/c/31034 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
2019-01-18mb/google/sarien/variants: Add Thermal Sensors informationSumeet Pawnikar
Add available thermal sensors information for CPU throttling action. BRANCH=None BUG=b:120058043 TEST=Built and tested on Arcada system Change-Id: I748ca0ce43915c96d71e63fb03fc3d1a02adc56c Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/30919 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2019-01-18mb/google/sarien/variants/sarien: Adjust TP/TS/H1 I2C CLK to meet specDtrain Hsu
After adjustment on Sarien EVT TouchScreen: 380.7 KHz TouchPad: 379.3 KHz H1: 392.2 KHz BUG=b:122657195 BRANCH=master TEST=emerge-sarien coreboot chromeos-bootimage measure by scope Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: I0dd92b054d934b38a17898dc8ce9cc18bda1633f Reviewed-on: https://review.coreboot.org/c/30949 Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-16mb/google/sarien/variants/sarien: Set up tcc offset for sarienJohn Su
Change tcc offset from 15 to 3 for sarien. BUG=b:122636962 TEST=Match the result from TAT UI Change-Id: I1c5d144e92d1e6e9c81b3e6686805ccf744b7203 Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/30808 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-16mb/google/sarien: Enable Camarillo DeviceLijian Zhao
Whiskeylake processor have an internal device called Camarillo dedicated for thermal management support, turn it on so processor thermal driver can be loaded. BUG=N/A TEST=Boot up and run lspci on Sarien board, Bus 0 Device 4 Funcion 0 can be seen. Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Change-Id: I937960fde2704cddb1fe0058ab622f4b5de401d7 Reviewed-on: https://review.coreboot.org/c/30858 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-01-16mb/google/sarien: Set PL1 and PL2 valuesSumeet Pawnikar
Set PL1 and PL2 values to 25W and 51W respectively for processor power limits control. BRANCH=None BUG=b:122343940 TEST=Built and tested on Arcada system Change-Id: I4098f334ed5cb6c4a6f35f1a7b12809f34c23fa3 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/30908 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2019-01-08mb/google/sarien: Set minimum assertion width valuesDuncan Laurie
Explicitly configure the minimum assertion width values to ensure that they are set as expected and are not using unknown defaults. Change-Id: I9a88e5b6002137df6e572b84d0de8a69522938f9 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/30722 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
2019-01-08mb/google/sarien: Enable recovery mode GPIODuncan Laurie
Enable the active-low recovery mode GPIO now that new boards are available which have an external pull-up instead of a pull-down so it can be asserted properly by servo. This was tested on a Sarien system by holding the recovery button on the servo board and tapping the cold reset button and ensuring that it enters recovery mode. Change-Id: I3216580bc94de71b05bf9382f15d0c4d428cb9fa Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/30721 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
2019-01-07mb/google/sarien: Correct I2C bus clock for touchpadLijian Zhao
Elan touchpad require connected i2c clock to be running at 400Khz, with the modification can get 404Khz speed from Arcada EVT platform. BUG=b:119628524 TEST=Build and boot up on Arcada platform, measure the i2c clock is around 400Khz. Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Change-Id: If717cdd6b73394125df54d90f729ffb4ef37b087 Reviewed-on: https://review.coreboot.org/c/30653 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2019-01-07mb/google/sarien: Modify ELAN Touchpad i2c bus clkJohn Su
Modify ELAN touchpad bus i2c clk from 466Khz to 400Khz. BUG=b:119628524 BRANCH=master TEST=measure ELAN Touchpad CLK Change-Id: Ia8433c6ef320cea9a0145db4ba440d67ccd0f41e Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/30588 Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-04mb/google/sarien: Add settings for noise mitgationLijian Zhao
Enable acoustic noise mitgation for sarien platform, the slow slew rates are fast time dived by 8. Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Change-Id: I5d38a1e03af08f106e2422a319b34c3fb54bdf28 Reviewed-on: https://review.coreboot.org/c/30448 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2018-12-29mb/google/sarien: Adjust GPD3 pin terminationLijian Zhao
Internal pull up need to be enabled for GPD3 as power button pin for PCH according cannonlake pch EDS vol1 table 17-1. Without that pin will stay floating and hook up XDP can cause system shutdown as power buttone event will trigger. BUG=N/A TEST=Hook up XDP on sarien platform, able to boot up into OS and stay at power up state. Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Change-Id: Ibe21da5f4a0797a3d62b36899f023908b46c25bf Reviewed-on: https://review.coreboot.org/c/30374 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2018-12-21mb/google/sarien: Disable pcie interface for wwanLijian Zhao
WWAN chip support 3 interfaces as pci express, USB 2.0 and USB 3.0, the usgae of Sarien choose to only use USB interface but not over pci express, so totally disable pci express root port 12. BUG=b:1246720 TEST=Boot up into OS with WWAN attached, cold boot and warm boot 10 cyles can still device can be listed under lsusb. Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Change-Id: Ic4da393c0c0d903848111e1c037c2730c86afa7d Reviewed-on: https://review.coreboot.org/c/30350 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2018-12-19mb/google/sarien: Enable DMI/SATA power OptimizeLijian Zhao
Turn on power optimizer of PCH side DMI and SATA controller. BUG=N/A TEST=Build and boot up into sarien platoform, able to finish 100 cycles of s0ix. Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Change-Id: I41da2b4106d683945cdc296e2a77311176144f43 Reviewed-on: https://review.coreboot.org/c/30212 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Roy Mingi Park <roy.mingi.park@intel.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2018-12-19mb/google/sarien: Use meaningful SATA modeLijian Zhao
Define SATA mode to AHCI mode instead of 0, make devicetree more readable. BUG=N/A Change-Id: I903545d9487c1409f9008407fe5bee6aa4959b98 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/c/30095 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2018-12-19mb/google/sarien: Enable ELAN Touchpad and Disable ALPS TouchpadChris Zhou
Enable ELAN Touchpad and Disable ALPS Touchpad BUG=b:119628524 BRANCH=master TEST=ELAN Touchpad can work normally. Change-Id: I7839459a70768fa95ba4871b1915d2ea86419bbb Signed-off-by: Chris Zhou <chris_zhou@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/30194 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
2018-12-18mb/google/sarien/variants/arcada: Enable touchpad and touchscreenCasper Chang
Enable Elan touchpad and WACOM touchscreen BUG=b:119924134, b:120103010 BRANCH=master TEST=Verify touchpad and touchscreen on arcada work with this change. Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com> Change-Id: I3dcdb4eeeb32766e64553d9e69e6b7e2b5ba85aa Reviewed-on: https://review.coreboot.org/c/30146 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2018-12-11mb/google/sarien: Disable unused SATA portsLijian Zhao
Disable SATA port 0 and port 1 as that's not used as SATA on platform. BUG=N/A TEST=Build and boot up fine on google arcada board. Change-Id: I1b8801f7a0f9b7847b85d7c315fa0a2093b32f70 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/c/30091 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Roy Mingi Park <roy.mingi.park@intel.com> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
2018-12-11mb/google/sarien: Disable PCH Gigabit LANLijian Zhao
There's no LAN connection on Arcada board, so disable PCH GBE. BUG=N/A Change-Id: I07c66df50dbe9fefd95a67b5af9e3f61ce6a18aa Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/c/30096 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
2018-12-10mb/google/sarien: Update GPIOs for next buildDuncan Laurie
Update the GPIOs for the next board build. Mostly minor changes but the polarity change on GPP_E8/RECOVERY on sarien will result in it booting to recovery every time unless using new hardware. For this reason the recovery mode GPIO that is passed to vboot is commented out for sarien. It is only used for testing and currently it is useful to have an image that works on both board versions. Change-Id: I32d84f3010cb4d3968370a03f7e191b1710a50e8 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/30062 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-09mb/google/sarien: Enable LAN clock source usageLijian Zhao
FSP defined a special clock source usage 0x70 for PCH LAN device, update that to google sarien platform. BUG=b:120003760 TEST=Boot up into OS, ethernet able to be listed in ifconfig. Change-Id: I9f945be4f0ce15470ab53f44e60143f3fd0fddf8 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/c/30100 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2018-12-07mb/google/sarien: Enable ISH on arcada, disable on sarienDuncan Laurie
The Intel Sensor Hub was enabled on the wrong variant so this change moves the enable from sarien to arcada. Change-Id: If933623f7dbb45c4805fb61430465236eca19ee8 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/30070 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Li1 Feng <li1.feng@intel.com> Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-12-07mb/google/sarien: Set initial I2C bus rise/fall timesDuncan Laurie
Provide rise/fall times as measured on existing boards. This will need adjusted for new boards but provides a starting point that makes I2C clocks look reasonable. Tested by measuring I2C bus speed and rise/fall times with a scope. Change-Id: Ic18010f5efc41dcee8925d696767ba2c44e3df4b Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/30069 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
2018-12-06mb/google/sarien/variants/sarien: Enable melf touchscreenChris Zhou
BUG=b:119799550 BRANCH=master TEST=Verify touchscreen on sarien works with this change. Change-Id: I926c988c141628ae2d98206f9eb615d06357a366 Signed-off-by: Chris Zhou <chris_zhou@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/29830 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2018-12-05mb/google/sarien: Enable ISHJett Rink
Turn on the ISH in the device tree. BUG=b:120295222 Change-Id: I0ba08c245d050aebc6eb06055690c422ab9b51c6 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://review.coreboot.org/c/30034 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-04mb/google/sarien: Enable WWAN detection on ArcadaLijian Zhao
Set GPIO D22 low to get WWAN_PERST#_R asserted. BUG=N/A TEST=Boot up with Arcada board, check WWAN get detected as USB devices through lsusb command. Change-Id: Ie848cd19fdf3b6c4b6abeb5fa3f566e5e4e7e928 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/c/30030 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-04mb/google/sarien: Define USB devices for ACPIDuncan Laurie
Add the USB device information for the sarien/arcada variants. This includes the ACPI _PLD group definitions for the external ports that indicate which USB2 and USB3 ports share the same physical interface. Change-Id: I0b936127954ba09c61ccb871bfc62ee7d99da263 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/30000 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-12-04mb/google/sarien: Enable DPTFDuncan Laurie
Enable DPTF support for sarien/arcada boards. This is currently using placeholder values that are identical that will be updated after thermal tuning is done. Change-Id: I7d51c3b38068fc25927c8dafc0bd9069b29d77f5 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/29762 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-12-04mb/google/sarien: Enable WWAN detectionAmanda Huang
Set WWAN_GPIO_PERST#(GPP_D22) to low at bootblock stage to meet the logic output for WWAN_PERST#_R to high. BUG=120004153 TEST=Boot up Sarien board, check WWAN get detected as USB devices through lsusb. Change-Id: I16f1101c64dfd4dcb5e8342fdb925951f6f2f90b Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/30017 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2018-11-29mb/google/sarien: Add HD Audio verb tableLijian Zhao
Implement HD Audio verb table for RealTek ALC 3204/3254 codec on google sarien and arcada board. BUG=b:119058355,119054586 TEST=Confirm audio play back is working on Sarien and Arcada board. Change-Id: Icedbb510c7668d96c99c657091fc865f03bf7783 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/c/29484 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com>
2018-11-17mb/google/sarien: Set SMBIOS mainboard SKUDuncan Laurie
Setting sku_id() is not enough to get a value to show up in the SMBIOS tables, it also needs to be returned as a string for the table creation to consume. This change defines the smbios_mainboard_sku() function and returns a string constant of "sku#" as expected. Change-Id: I03013bab89d53d1eba969c6ffb7e95fcbb315a81 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/29649 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Trent Begin <tbegin@google.com>
2018-11-08mb/google/sarien: Set runtime IRQs to reset on PLTRSTDuncan Laurie
GPIOs that use GPI_APIC setting with DEEP can cause an IRQ storm after S3 resume. GPIOs that fire IRQs via IOAPIC need to get their logic reset over PLTRST to prevent IRQ strom after S3 resume. For sarien/arcada these are all runtime IRQs only, not wake capable. Change-Id: Iec3706a3b47b54abbacd06081910f389979c330f Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/29539 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-11-07mb/google/sarien: Add sku_id functionDuncan Laurie
This change adds a sku_id() function that returns a static value to differentiate the sarien and arcada boards. Change-Id: I1fecc675573a6aece7188aae9370733068d45dbf Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/29486 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-07mb/{intel/google}: Move CNVi ASL entry from static DSDT to dynamic SSDT ↵Subrata Banik
generation This changes uses drivers/intel/wifi chip for CNVi device to ensure that: 1. Correct device name shows in ACPI name space 2. Correct wake up shows in cat /proc/acpi/wakeup 3. Remove cnvi.asl from soc/intel/cannonlake Change-Id: Ic81de2dce6045ced913766790a40ed19119f5118 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/29399 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-11-05mb/google/sarien: Enable WWAN detectionLijian Zhao
WWAN start-up control requires RESET# assert after FULL_CARD_POWER_OFF# set to high more than 10 ms, so force RESET#(GPP_D21) to low at bootblock stage to match the sequence. BUG=N/A TEST=Boot up Sarien/Arcada board, check WWAN get detected as USB devices through lsusb. Change-Id: I36eb841a2e8f2b36771d20577314a7451fbee133 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/29430 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2018-11-02mb/google/sarien: Enable Wilco ECDuncan Laurie
The Sarien mainboard uses the newly added Wilco EC. - enable CONFIG_EC_GOOGLE_WILCO - add the device and host command ranges to the devicetree - have the mainboard SMI handlers call the EC handlers - add EC and SuperIO devices to the ACPI DSDT - call the early init hook for serial setup Change-Id: Idfc4a4af52a613de910ec313d657167918aa2619 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/29411 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-11-02mb/google/sarien: Add Arcada variantDuncan Laurie
Add a variant of the Sarien board called Arcada. This is currently very similar to Sarien with differences in PCIe, USB, and GPIO usage. Change-Id: I432d2ba99558e960d4e775c809cc8bf6aa1a56bf Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/29410 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-02mb/google/sarien: Add new mainboardDuncan Laurie
Sarien is a new board using Intel Whiskey Lake SOC. It also uses the newly added Wilco EC, enabled in a separate commit. Sarien is not a true reference board, it is just one variant of a very similar design. For that reason it is not considered the baseboard but rather a standalone variant. Change-Id: I2e38f617694ed2c2ef746ff8083f2bfd58cbc775 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/29409 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2025-01-07 16:36:50 +0000