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path: root/src/mainboard/google/sarien/chromeos.c
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2019-08-09soc/intel/{cnl,icl}: Use new power-failure-state APINico Huber
pmc_soc_restore_power_failure() is only called from SMM, so add `pmc.c` to the `smm` class. Once all platforms moved to the new API, it can be implemented in a central place, avoiding the weak- function trap. Change-Id: Ib13eac00002232d4377f683ad92b04a0907529f3 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34726 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-25mb/*/chromeos.c: Remove some ENV_RAMSTAGE and __SIMPLE_DEVICE__Kyösti Mälkki
Use explicit simple PCI config accessors here. Change-Id: Ifa3814fdd7795479ca5fdbfc4deb3fe8db9805f3 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34519 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-07-07soc/intel/cannonlake, mb/google/sarien: Get rid of unused dev paramFurquan Shaikh
This change gets rid of unused dev param to pmc_set_afterg3. BUG=b:136861224 Change-Id: Ic197d6fb8618db15601096f5815e82efc2b539c1 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34117 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2019-05-13mainboard: remove "recovery" gpio, selectively add "presence" gpio.Matt Delco
The gpio table is only used by depthcharge, and depthcharge rarely has a need for the "recovery" gpio. On a few boards it does use the gpio as a signal for confirming physical presence, so on that boards we'll advertise the board as "presence". All these strings probably should have been #defines to help avoid typos (e.g., the "ec_in_rw" in stout seems questionable since everybody else uses "EC in RW"). Cq-Depend: chromium:1580454 BUG=b:129471321 BRANCH=None TEST=Local compile and flash (with corresponding changes to depthcharge) to 2 systems, one with a "presence" gpio and another without. Confirmed that both systems could enter dev mode. Change-Id: Id6d62d9e48d3e6646cbc1277ea53f0ca95dd849e Signed-off-by: Matt Delco <delco@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32718 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-04-11chromeos: clean up "recovery" and "write protect" GPIOsJoel Kitching
The "write protect" GPIO's cached value is never actually read after entering depthcharge. Ensure the value from get_write_protect_state() is being transferred accurately, so that we may read this GPIO value in depthcharge without resampling. The cached value of the "recovery" GPIO is read only on certain boards which have a physical recovery switch. Correct some of the values sent to boards which presumably never read the previously incorrect value. Most of these inaccuracies are from non-inverted values on ACTIVE_LOW GPIOs. BUG=b:124141368, b:124192753, chromium:950273 TEST=make clean && make test-abuild BRANCH=none Change-Id: Ic17a98768703d7098480a9233b752fe5b201bd51 Signed-off-by: Joel Kitching <kitching@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32233 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-03-25mainboard/google/sarien: skip tpm check when !verstageJett Rink
The TPM driver isn't loaded in other stages but verstage so when we try to communicate with the TPM it fails. We don't need to communicate with it anyway since the TPM won't continue to tell us that recovery was requested, only the first query responds with the recovery request. BRANCH=none BUG=b:129150074,b:123360379 TEST=1)boot arcada without recovery and notice that the "tpm transaction failed" log lines are no longer present. 2) boot into recovery using the ESC refresh power key combination and verify that the recovery reason was "recovery button pressed" Change-Id: I13284483d069ed50b0d16b36d0120d006485f7f4 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32030 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Keith Short <keithshort@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2019-02-13coreboot: check Cr50 PM mode on normal bootKeith Short
Under some scenarios the key ladder on the Cr50 can get disabled. If this state is detected, trigger a reboot of the Cr50 to restore full TPM functionality. BUG=b:121463033 BRANCH=none TEST=Built coreboot on sarien and grunt platforms. TEST=Ran 'gsctool -a -m disable' and reboot. Verified coreboot sends VENDOR_CC_IMMEDIATE_RESET command to Cr50 and that the Cr50 resets and then the platform boots normally. TEST=Performed Cr50 rollback to 0.0.22 which does not support the VENDOR_CC_TPM_MODE command, confirmed that platform boots normally and the coreboot log captures the unsupported command. Tested-by: Keith Short <keithshort@chromium.org> Change-Id: I70e012efaf1079d43890e909bc6b5015bef6835a Signed-off-by: Keith Short <keithshort@chromium.org> Reviewed-on: https://review.coreboot.org/c/31260 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-02-13soc/intel/cannonlake: Don't use CAR_GLOBALArthur Heymans
All platforms using this code have NO_CAR_GLOBAL_MIGRATION. Change-Id: I72effa93e36156ad35b3e45db449d8d0d0cabf06 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/30514 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-01-25mb/google/sarien: Force power on after cr50 updateDuncan Laurie
By default this board is configured to not power up after an EC reset. However in the case of a cr50 firmware update that will reset the EC it will end up powered off. In order to have it stay powered up configure the board to power up. This will get reset to the configured default when it boots again. BUG=b:121380403 TEST=update cr50 firmware and reboot to ensure system boots and does not end up powered off. Change-Id: I85beae24b1bc56bb0813f1fd1305218f04b0c1c8 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/31058 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-24mb/google/sarien: Fix recovery mode detectionDuncan Laurie
In order to support the physical recovery GPIO on sarien it needs to enable the option VBOOT_PHYSICAL_REC_SWITCH and set the GPIO number in the coreboot table appropriately so that depthcharge can correctly determine the GPIO number. The same is done for the write protect GPIO in this table. Additionally since we are reading a recovery request from H1 it needs to cache the result since H1 will only return true on the first request. All subsequent queries to H1 will not indicate recovery. Add a CAR global here to keep track of the state and only read it from H1 the first time. BUG=b:121380403 TEST=test_that DUT firmware_DevMode Change-Id: Ia816a2e285d3c2c3769b25fc5d20147abbc71421 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/31043 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-17src/mainboard/google/sarien: query recovery mode from Cr50Keith Short
On the Sarien/Arcada platforms, the EC is not trusted to provide the state of the ESC+REFRESH+PWR recovery combination. On these platforms the Cr50 latches the state of REFRESH+PWR for use as the recovery mode key combination. BUG=b:122715254 BRANCH=none TEST=Verify recovery mode screen shown after pressing REFRESH+PWR Change-Id: If336e9d7016987be151ab30d5c037ead3a998fe0 Signed-off-by: Keith Short <keithshort@chromium.org> Reviewed-on: https://review.coreboot.org/c/30937 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2019-01-16buildsystem: Promote rules.h to default includeKyösti Mälkki
Does not fix 3rdparty/, *.S or *.ld or yet. Change-Id: I66b48013dd89540b35ab219d2b64bc13f5f19cda Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/17656 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-11-02mb/google/sarien: Add new mainboardDuncan Laurie
Sarien is a new board using Intel Whiskey Lake SOC. It also uses the newly added Wilco EC, enabled in a separate commit. Sarien is not a true reference board, it is just one variant of a very similar design. For that reason it is not considered the baseboard but rather a standalone variant. Change-Id: I2e38f617694ed2c2ef746ff8083f2bfd58cbc775 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/29409 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
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