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path: root/src/mainboard/google/samus/Makefile.inc
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2015-01-04samus: Move SPD related information to spd directoryDuncan Laurie
Put all the SPD related information in one place including the onboard SPD sources and the board specific parsing. BUG=chrome-os-partner:28234 TEST=Build and boot on samus Original-Change-Id: If5cd826ecc9cc856008b7c29aa3cfade5ae7f685 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/201082 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit f40e447cee84ebd04ab8a57250d0f56f508d52f2) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I9c10b08c3e640642e3c75696a233051bb34a2123 Reviewed-on: http://review.coreboot.org/8006 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-12-31samus: Combine mainboard patches to build soc/intel/broadwellDuncan Laurie
Combine four patches dependencies. These will not build individually, so combine them for coreboot.org upstream. samus: Move SPD handling to separate file The code to find the SPD data for the mainboard based on GPIOs is moved from romstage.c into spd.c. It relies on the updated pei_data structure from broadwell instead of the haswell interface. BUG=chrome-os-partner:28234 TEST=Build and boot on samus CQ-DEPEND=CL:199921 CQ-DEPEND=CL:199922 CQ-DEPEND=CL:199923 CQ-DEPEND=CL:199943 CQ-DEPEND=CL:*163751 Original-Change-Id: I5bd56f81884dae117b35a1ffa5fb6e804fd3cb9c Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/199920 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 0bd2de4ba5eb8ba5e9d43f8e82ce9ff7587eab62) Signed-off-by: Marc Jones <marc.jones@se-eng.com> samus: Move PEI data structure init to separate file This needs to be executed in both romstage and ramstage for the different PEI binary stages. It uses the broadwell interface now instead of haswell. BUG=chrome-os-partner:28234 TEST=Build and boot on samus CQ-DEPEND=CL:199920 CQ-DEPEND=CL:199922 CQ-DEPEND=CL:199923 CQ-DEPEND=CL:199943 CQ-DEPEND=CL:*163751 Original-Change-Id: Ida05bd17b9e54f08ed0e2767361c9301a2e97709 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/199921 (cherry picked from commit 89f98a27ea561ec63e716b1f6446d92822a6a5de) Signed-off-by: Marc Jones <marc.jones@se-eng.com> samus: Convert mainboard to use soc/intel/broadwell Switch from the haswell cpu/northbridge/southbridge interface to the soc/intel/broadwell interface. - Use new headers where appropriate - Remove code that is now done by the SOC generic code - Update GPIO map to drop LP specific handling - Update INT15 handlers, drop all but the boot display hook BUG=chrome-os-partner:28234 TEST=Build and boot on samus CQ-DEPEND=CL:199920 CQ-DEPEND=CL:199921 CQ-DEPEND=CL:199923 CQ-DEPEND=CL:199943 CQ-DEPEND=CL:*163751 Original-Change-Id: I56f3543612e89e2cdb4256b1bcd4279f5546b918 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/199922 (cherry picked from commit 715dbb06e9f79d1ec3647330311c45aa29362375) Signed-off-by: Marc Jones <marc.jones@se-eng.com> samus: Add some code to print basic info from SPD The handling of LPDDR is a bit messy in Intel platforms. There is no traditional SPD so instead one is created by hand from the provided datasheets. These have varying (and sometimes unexpected) geometry and it can be important during bringup to know what configuration is being passed to the memory training code. This could in theory be put in a more generic location, but for now this is the only board with LPDDR3 where I have found it valuable. BUG=chrome-os-partner:28234 TEST=Build and boot on samus, look for SPD details on the console. CQ-DEPEND=CL:199920 CQ-DEPEND=CL:199921 CQ-DEPEND=CL:199922 CQ-DEPEND=CL:199943 CQ-DEPEND=CL:*163751 Original-Change-Id: Ibce0187ceb77d37552ffa1b4a5935061d7019259 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/199923 (cherry picked from commit 3f36348dd7abc67048407f181065f1a99b3d0dab) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I1d19dffbd0b2e838d1946670a0bee9f8e121869d Reviewed-on: http://review.coreboot.org/7943 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-09-08samus: Fix up memory SPD informationDuncan Laurie
The LPDDR3 memory is x32 and dual rank with 14 row bits. In addition the memory is actually elpida, even though they are owned by micron it is confusing to label it as such. And the ram strap options were inverted from what I expected so the memory table needs to be updated. Change-Id: Ia29a23e8140d884fb84f940806f041b40562aab9 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/174121 Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 0d63d36b8035165f95db798ed40488519e622a65) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6828 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-08-29samus: Add coreboot boardDuncan Laurie
Add the coreboot board files for samus - Based on Bolt - GPIO setup based on 0.91 schematic - Support both memory types - No HDA verb table for this platform - Some GPIO interrupts are shared and need to be passed to OS Change-Id: I8dbd7639456c631a0115b03a493d94b5e2361ab5 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/171694 Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 249a74c628264e3d4ce754803ede31238404b4d5) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6775 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>