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path: root/src/mainboard/google/rush_ryu
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2015-04-06New mechanism to define SRAM/memory map with automatic bounds checkingJulius Werner
This patch creates a new mechanism to define the static memory layout (primarily in SRAM) for a given board, superseding the brittle mass of Kconfigs that we were using before. The core part is a memlayout.ld file in the mainboard directory (although boards are expected to just include the SoC default in most cases), which is the primary linker script for all stages (though not rmodules for now). It uses preprocessor macros from <memlayout.h> to form a different valid linker script for all stages while looking like a declarative, boilerplate-free map of memory addresses to the programmer. Linker asserts will automatically guarantee that the defined regions cannot overlap. Stages are defined with a maximum size that will be enforced by the linker. The file serves to both define and document the memory layout, so that the documentation cannot go missing or out of date. The mechanism is implemented for all boards in the ARM, ARM64 and MIPS architectures, and should be extended onto all systems using SRAM in the future. The CAR/XIP environment on x86 has very different requirements and the layout is generally not as static, so it will stay like it is and be unaffected by this patch (save for aligning some symbol names for consistency and sharing the new common ramstage linker script include). BUG=None TEST=Booted normally and in recovery mode, checked suspend/resume and the CBMEM console on Falco, Blaze (both normal and vboot2), Pinky and Pit. Compiled Ryu, Storm and Urara, manually compared the disassemblies with ToT and looked for red flags. Change-Id: Ifd2276417f2036cbe9c056f17e42f051bcd20e81 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: f1e2028e7ebceeb2d71ff366150a37564595e614 Original-Change-Id: I005506add4e8fcdb74db6d5e6cb2d4cb1bd3cda5 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/213370 Reviewed-on: http://review.coreboot.org/9283 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Tauner <stefan.tauner@gmx.at> Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-28ryu: Add padconfigs for volup and voldown buttonsFurquan Shaikh
Both buttons are active low. BUG=chrome-os-partner:32517 BRANCH=None TEST=Compiles successfully and volup and voldown button presses are detected in pseudo keyboard driver in depthcharge Change-Id: If217a75f95042af8a831e7109d9b1acb10c55823 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: c393e166a1ed0bc7920078aac6accf442abb5955 Original-Change-Id: I08f94972db53aa17a63f6e16cbaebe7af358cdc2 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/220687 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9104 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-28rush: ryu: remove mainboard_add_memory_ranges()Aaron Durbin
There's no need to add DMA ranges for these boards as that memory is allocated within dpethcharge now. Additionally, the DRAM_DMA_* Kconfig options were removed resulting in 0 values. BUG=None TEST=Built rush and ryu. BRANCH=None Change-Id: I597437960e4fddbf6d26f0b15ddeefc4557adc8b Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: f26b503d759b2bac902e58e928d7c625c1a6c575 Original-Change-Id: I52bb8f760a56226c75611f7981570a44d56f242e Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/219710 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9101 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-28tegra132/rush/ryu: Use CLK_RST_REG instead of &clk_rst->...Furquan Shaikh
BUG=chrome-os-partner:31821 BRANCH=None TEST=Built and booted to kernel prompt on ryu. Rush compiled successfully. Change-Id: I63ba55c53094c185d72dcb5c5d0d766461989806 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 4a9aa565244bae5659e458ea90064eb5b803d574 Original-Change-Id: I5b00fbcb8e414c67563f1ad548f84c281898f939 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/219392 Original-Reviewed-by: Tom Warren <twarren3959@gmail.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9100 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-28Ryu: Move I2C6 init to ramstageTom Warren
BUG=chrome-os-partner:31820 BRANCH=none TEST=Dumped Speaker Driver (AD SSM4567) regs on Ryu, looks good. Change-Id: I9b094e9d22726d67d41f2ce78088f361c73895fd Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 4c0bfb5f747f55009b7c2b2ba4b24d91443b1639 Original-Change-Id: Idd5b95cfec7d3ade7508393b81ab3049ce15a2fb Original-Signed-off-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/218950 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9095 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-28Ryu: Rewrite I2C6 mux initTom Warren
Do the absolute minimum needed to allow the DPAUX mux ctl write for I2C6. This leaves HOST1X off (reset and clock disabled) to avoid a conflict with any kernel display driver init. I2C6 init/enable will be moved to ramstage in the next CL. BUG=chrome-os-partner:31820 BRANCH=none TEST=Dumped Speaker Driver (AD SSM4567) regs on Ryu, looks good. Change-Id: I42106778a26c5a1d1483cc308b8314599c391539 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 24a9ebfda31c620b24e5c765dc950b87e3e5587b Original-Change-Id: I0760222f1d7ccee207ae9871aeed3e2ddbca3dca Original-Signed-off-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/218900 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9093 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-28ryu: use generic spin tableAaron Durbin
With the generic spin table support in place, use that. BUG=chrome-os-partner:32082 BRANCH=None TEST=Booted into kernel. Change-Id: I8644f8a81b24bf4e00f8fac1d1018f9db77c952f Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: b1a4fe27070a80c8448051ec0565120901378673 Original-Change-Id: Id0832a4553101a366f011099e0744f6630d91924 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/218656 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9086 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-28ryu: Get rid of coreboot setting up DMA areas for libpayloadFurquan Shaikh
BUG=chrome-os-partner:31634 BRANCH=None TEST=Compiles successfully and dma areas are setup fine by libpayload mmu Change-Id: I6d2d1dbcfc9bdeea94c89a9a3fce486203269642 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 0425e87f21bcb92861240d6437769a5b28e9929b Original-Change-Id: I1034a4dcf6c9ee56bee4ea5d18e91a8d51895429 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/217571 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9072 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-28ryu: remove bring_up_secondary_cpu from devicetreeAaron Durbin
Now that arm64 and tegra132 has cpu devicetree support stop using the bring_up_secondary_cpu option. BUG=chrome-os-partner:31761 BRANCH=None TEST=Built and brought up 2nd core. Change-Id: I3ffca6c1fa0932d8aafea30a160608b5593ae154 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: c45b22ce9fd0345c3e599fd814993db66e2b96cc Original-Change-Id: I210bea73f8249de15f99d0c062600e789184eefd Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/216928 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9059 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-27ryu: add cpus to device treeAaron Durbin
Add all the CPUs to the device tree. BUG=chrome-os-partner:31761 BRANCH=None TEST=Brought up 2nd core on ryu in kernel. Change-Id: I4cc51f30897e3bd6c1b275a95d5da34ce7ae320e Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 485de634a49d606dc6e7168f047eb9365e26415f Original-Change-Id: I682f23a9b68f49206aa99d55e800540d8d0f8900 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/216426 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9034 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-27ryu: remove call to soc_configure_i2c6pad()Aaron Durbin
This function is breaking display bring up in the kernel. While this functionality may be needed it's not until there is a necessity to beep and/or bring up the display in firmware. BUG=chrome-os-partner:31820 BRANCH=None TEST=Sean ran with this patch and the display indeed did come up. Change-Id: I5cf8a6c6e6941ee138991933215f96f5562382be Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 038bc1d53028409d0640c78fb62c7025ba12dcb9 Original-Change-Id: I833d66a0e63e04118b130b6803a7a3b68c802148 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/216421 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9031 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-27ryu: Remove old/unused BCT cfg filesTom Warren
These are not needed/were never really used. SDRAM init will now be done in sdram.c, not the BootROM. BUG=chrome-os-partner:29921 BUG=chrome-os-partner:31031 BRANCH=None TEST=Built rush_ryu AOK. Change-Id: Id046592415574badb97026224e1e525c174eece4 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: aab1045817125cb022c8e8b89b85ef14e581baa7 Original-Change-Id: I7d25de3e888bb24e4c6e6dea2726510c97fe1730 Original-Signed-off-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/215863 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9030 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-27ryu: fix power button polarityAaron Durbin
The power button signal is driven from the silego part. It's active high when the button is pressed. BUG=None BRANCH=None TEST=Booted with power button pressed. vboot saw the press and requested a shut down. Change-Id: Ifff1bd8d4340849e0c218812fd401b61c90c5743 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: b6bd7c0de38e1078b85f1671493c6d2948d43149 Original-Change-Id: If25ebce28c1ab5a363f3b4b5ab9fc24baebad56a Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/214847 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9028 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-27rush: use names for gpiosAaron Durbin
Instead of calling out the gpio index and port numbers use real names. It's semantically clearer and there's only one place to adjust the hardware values. BUG=chrome-os-partner:31106 BRANCH=None TEST=Built and booted. Change-Id: I4a0bc034fe4f648b73ebf6389d8669fe15db1d8f Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 5f2af2e32903b3df64f3f25a42fb42b0b629152c Original-Change-Id: I68c138b428abbd0c9bc60be0cfc70681528d7728 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/215542 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9027 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-27ryu: configure plld for display usageAaron Durbin
The kernel doesn't have the logic for bringing up the plld. Therefore, configure it in the firmware. The clock used is an interim value until the display controller sequencing is fully implemented. BUG=chrome-os-partner:31640 BRANCH=None TEST=Noted configured freq is close to requested. Also, no more plld errors observed from the kernel. Change-Id: I0788c83843699ec7cef52b3a219ebb9b0db9082f Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: b44956ec87e9083aebe589349cbe168f7f101d8b Original-Change-Id: I6f57d5c48630385d1814e7ef61898a2d49c8f747 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/214841 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9026 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-27ryu: bring up secondary coreAaron Durbin
Instruct the SoC to bring up the 2nd core. BUG=chrome-os-partner:31545 BRANCH=None TEST=Brought up 2nd core in Linux. Change-Id: I4b31ea5f1466c43abce273b2bfb6a4d06b7faa63 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 74c62e62a6790de65e303123abee2be1dfffbee3 Original-Change-Id: I5f5febc4719951188106041f73625231eafe1b08 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/214778 Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9022 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-27ryu: normalize board idAaron Durbin
Instead of relying on the encoding of gpio_get_in_tristate_values() normalize the ids. BUG=chrome-os-partner:31602 BRANCH=None TEST=Built and noted correct output w/ coresponding correct device tree selected in depthcharge. Change-Id: I6fc712aceb56d701725759503b9cfa1061ed25d7 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 1037d473f35613bf39a4b27a9c1ade718b852c0d Original-Change-Id: I7d5449bc14e776fd9faa86af0f80690c3d9ae92d Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/214840 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9004 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-27ryu: initialize LTE modemBen Chan
BUG=chrome-os-partner:30748 TEST=Verify that LTE modem appears on USB during kernel boots on Ryu. Change-Id: I5b73a632ab827abe9c064a097e04d2c9030f9b46 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 070538e60b384d17e17ba3544881ef642c3f33ba Original-Change-Id: I8ec1f94c9aec5b4895a01cdfd3b86f88cd6bb877 Original-Signed-off-by: Ben Chan <benchan@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/214020 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9002 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-27ryu: use named bus numbers instead of literalsAaron Durbin
Use the bus number enumerations from funit to make the pad names and bus numbers consistent and clearer. BUG=chrome-os-partner:31106 BRANCH=None TEST=Built and booted to kernel. Change-Id: If84ed825537f598c033dcacbcba759e0fe4e90ec Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: f4375a8e47f572d618044f65603fb9288832f936 Original-Change-Id: I817a56e879ecc96474128d624dc46c12ebc5c7a8 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/213492 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8997 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-27ryu: Add pad/funit init for i2c6 (audio codec, etc.)Tom Warren
BUG=none BRANCH=none TEST=built ryu, booted to recovery mode OK Ran TegraShell and could r/w I2C6 regs OK Change-Id: I7dca131ab5bd4dac50891937f792ac70b1bb532f Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 29591a97fbb8fc42143ff6c7838c9935834ca516 Original-Change-Id: Ic74e3518ab69ec7b1bc3bc4f637b7b38b85734c9 Original-Signed-off-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/212926 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/8993 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-26ryu: enable external usb 2.0 portAaron Durbin
BUG=chrome-os-partner:31293 BRANCH=None TEST=Able to get sporadic USB communication in depthcharge on ryu. Change-Id: I6bf6559d167a6ea94523d2500b54c1c7854330f4 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: e5412cfc149902298f2ebeb3030d8f09f27e5ee8 Original-Change-Id: Ic5402d18943c3cc8fb4556c47e587134633fbf72 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/212333 Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8939 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-26ryu: convert hardware initialization to funit APIAaron Durbin
Use the new funit API to do all the dirty work. BUG=chrome-os-partner:29981 BRANCH=None TEST=Built and ran through depthcharge and into recovery just like before. Change-Id: I8625a06dd847bd3dcfc3ce5a50a31d6aff0b860f Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: ebc04a174269ae072eda804e172fd24362f417d2 Original-Change-Id: Ief2d81c5569c33a90fc9458d741edef1dcbd8239 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/212152 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8930 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-26ryu: support for DMA regionAaron Durbin
Currently ryu needs a DMA region in order to communicate with USB devices. Therefore, add that region to the memory map. BUG=chrome-os-partner:31293 BRANCH=None TEST=With usb added am able to talk to a USB mass storage device albeit inconsistently. Change-Id: I7efaf2ba44cc94dc64af3f1cd916bdc5c7ff0795 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: e93389479518ee28dc3477da0c6e6e33fa8a47d1 Original-Change-Id: I6b5c052ccaafce30705349e07639dffbb994901f Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/212162 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8926 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-26t132: ryu: Correct how board id is retrievedJimmy Zhang
Two changes: 1. A44 ID straps use different gpio pins than nyan. 2. A44 uses tristate values instead two state values. BUG=none BRANCH=none TEST=Built and tested on A44 board. Change-Id: I6a36f6da0c9f6168780606ba76595c7a0af8e8bf Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 2eb0cae0e3396da1eaeaa72411c4b74300138a7b Original-Change-Id: Ia2a4309d3b63b0a94d79465dd727b01fae01e1b9 Original-Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/211753 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/8920 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-26ryu: Update BCT to Max Frequency 924MHzJimmy Zhang
Replace previous 528MHz BCT. This BCT contains four entries as below: 0: Samsung 1: Hynix 2: Micron 3: (spare) 528MHz Micron BUG=none BRANCH=none TEST=Built and tested on Micron LPDDR. Change-Id: Ibe9e299ac1dd4cabd390b2e78bbec6c0f3a3871b Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 3fcb3e82998c88220e87118efff0595ba3572e38 Original-Change-Id: I49e18ca8dc69f2ce9ded71f4f55c02a8b91f92b2 Original-Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/211479 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Reviewed-on: http://review.coreboot.org/8919 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-26ryu: convert mainboard initialization to use padconfig APIAaron Durbin
BUG=chrome-os-partner:29981 BRANCH=None TEST=Built and booted through depthcharge on ryu Change-Id: I79373a171922bffacb56f8ba2c0f8d40d0215963 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: d635c8b67658fa95ab2688eac926334849c286a2 Original-Change-Id: I129c17045db95732aa7d548ba6dde754937fdb08 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/211192 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8918 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-26tegra132: move common bootblock init into SoC codeAaron Durbin
The current 2 boards were setting up clocks and enabling peripherals that apply to the SoC generically. Therefore, move the common pieces into the SoC code. BUG=chrome-os-partner:31105 BRANCH=None TEST=Built and booted through depthcharge on ryu. Change-Id: I94ed4b5cc4fafee508d86eefe44cf3ba6f65dc3b Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 6dad573c8689b79bb4aa615811a10f44e7d8c809 Original-Change-Id: I6df1813f88362b8beaf1a716f4f92e42e4b73406 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/211191 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Reviewed-on: http://review.coreboot.org/8917 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-03-26ryu: configure EC I2C pads as open drainAaron Durbin
The I2C pads connected to the EC are pulled to 3.3V. Therefore the pads need to be configured as open drain. BUG=chrome-os-partner:29981 BRANCH=None TEST=Built and booted through depthcharge on ryu Change-Id: Ie5eadfe6aca78eb31fbca4e8d8117d1061acbbec Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 1530e7e7f500be47355eada56591ac2dbf1e9326 Original-Change-Id: Ia4ad2377d01296235fc7efbba72fa790016c04af Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/211135 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8916 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-03-26ryu: use EC proto v3 over i2cAaron Durbin
Ryu's EC talks proto v3 over i2c. Select the correct protocol. BUG=chrome-os-partner:31148 BRANCH=None TEST=Built and ran on ryu. Coreboot can speak to the EC now. Change-Id: Iaed0d2db3c3c93667d65beea98b9719bdbbbfe41 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: b71cad3bb1e9b64c48b6f2eeb7573c408a508fb3 Original-Change-Id: I50e192cd58f7a29103ab94afc002da18822d4080 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/211240 Original-Reviewed-by: Stefan Reinauer <reinauer@google.com> Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8915 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-26ryu: enable vboot firmware verificationAaron Durbin
Add the supporting Kconfig options and infrastructure for performing vboot firmware verification. BUG=chrome-os-partner:30784 BRANCH=None TEST=Built and ran on ryu into depthcharge noting vboot paths being taken. Change-Id: I1d803208cd5789bd73244b91beac6a5a4598ea70 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: a2e7d84725739843a1ed1868fcadebb60477a6dc Original-Change-Id: Ie4c8c3939990a12fc528423948b236230392eb7c Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/211134 Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8914 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2015-03-25tegra132: use pre-existing reset APIAaron Durbin
coreboot already has a reset API. Utilize it by selecting HAVE_HARD_RESET. The tegra132 boards have to provide the hard_reset() implementation as that involves board-specific bits. The tegra132 code then provides a cpu_reset() routine that just promotes that call to a hard_reset(). For the existing tegra132 boards remove the unnecessary files from the build. BUG=chrome-os-partner:30784 BRANCH=None TEST=Ensured hard_reset() does something on Ryu. Change-Id: I6d5aa928fec95b361175e35e0a26812829ffdfc3 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 31edd4ff7486ded87d2525cd360d48959b6aef7c Original-Change-Id: I1e1b014062dafb5d81fb9da40006c5405073a95d Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/211131 Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8911 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-25rush/ryu: restore full-speed clocks to TPM I2C and EC SPITom Warren
Now that there's a working udelay() in tegra132, upclock CAM_I2C and SPI1 to the same speeds as used on Nyan. BUG=chrome-os-partner:30998 BRANCH=rush_ryu TEST=Built Rush and tested, no nack errors seen. Change-Id: If1ee6d5c711252e294818d6263732bb34b2fe6f0 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 859c0d4fde2cf098cb829e96a5d6dec394bea600 Original-Change-Id: I58fd03ed3512c2498c793cfe30b0c302e4b0e3d4 Original-Signed-off-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/211043 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/8910 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-25ryu: Add 4 LPDDR3 SDRAM BCTsAaron Durbin
These are used by the LPDDR3 code in sdram.c. Based on the schematic and email, I've filled in 4 slots in sdram_configs.c. My A44 returns RAMCODE 0 (using only bits 1:0) for Samsung SDRAM. I haven't tested the other 2 types of RAM (Hynix and Micron). The 4th slot is a fallback slow Micron config. Previously existing configurations were dropped. BUG=chrome-os-partner:29921 BUG=chrome-os-partner:31031 BRANCH=None TEST=Built for rush and rush_ryu. Change-Id: I55a737db269fe5fac1565d58bd8f8afcbc5beecb Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 9a431466171a85a5c8151e7466eb5f77862e7b44 Original-Change-Id: If216096ffc9e9836b6d082ad0668640b3eec37b7 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Id: a45e7788dd78697ac5f48b6cc64108ca0e4912dd Original-Change-Id: Ib7e8b814eb6dadb9b366536721876a3eeba0d2c0 Original-Signed-off-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/216000 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/8976 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-25ryu: Add three more full LPDDR3 SDRAM BCTsJimmy Zhang
Add in the following BCTs to source code tree: Hynix 4GB 924MHz BCT Micron 4GB 924MHz BCT Samsung 4GB 924MHz BCT BUG=none BRANCH=none TEST=Built and tested Micron 924 bct on A44 board with Elpida memory chip. Change-Id: I59a5cc1133bf41a51f40a771ff0a7b7ef8d549fe Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 0a72f1b704928fad341bda460ecc349914ec612c Original-Change-Id: I9e5b54c3eb7ee4c4010b5aaf5dad030eba75108b Original-Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/210872 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Reviewed-on: http://review.coreboot.org/8904 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-25ryu: switch to padconfig API in romstageAaron Durbin
BUG=chrome-os-partner:29981 BRANCH=None TEST=Built. Change-Id: I84abb36d4b39b60837b68c24f5cacffb74c1a985 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 42a5d3a8a8c46b20361522bc5cb1c1faafaae0cc Original-Change-Id: Ib3ee8a14a34d0a2e73f3b912879eb65ac2d97c50 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/210900 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8975 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-25tegra132: introduce romstage_mainboard_init()Aaron Durbin
Instead of calling out with function names all the possible combinations of interface and device provide one call to the mainboard to configure all the necessary bits. BUG=chrome-os-partner:31104 BUG=chrome-os-partner:31105 BRANCH=None TEST=Built and ran on rush. Change-Id: Id7817e85065884d64f90ac514bf698bf539f2afe Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: f4f63f5965d403a32872d7b52c180694f5ef679d Original-Change-Id: Id27d9c2da4dccdff38c48dc5cdeb1a68cf23cbfc Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/210838 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8901 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2015-03-25ryu: Add mainboard_init_xxx functions to get it building againTom Warren
Rush has its EC on SPI, and Ryu has it on I2C, so need both mainboard_init_ec_spi and mainboard_init_ec_i2c in both builds, due to romstage.c being in the common tegra132 subdir. BUG=none BRANCH=rush_ryu TEST=Built both rush and rush_ryu images OK. Will try to boot on Ryu later. Change-Id: Iddbf9e9f6de7ba7244f9dd2e810fb6178937c85a Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 4d8b81717c366d19b43964bed3c4047598db4495 Original-Change-Id: I48d9530697d5669177ecd9ba3c34360197002003 Original-Signed-off-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/210595 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/8900 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-24ryu: use padconfig API in bootblockAaron Durbin
Switch over to the padconfig API for bootblock PAD configurations. Aside from support code, each entry is 4 bytes. The open coded calls were 12 bytes each. BUG=chrome-os-partner:29981 BRANCH=None TEST=Built for ryu. Change-Id: Iff981509f258c8fe7bbc2e24ce87bad0c43a55b8 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 8a7ee469124eeb6d05b978b5e68a2fc03b102f47 Original-Change-Id: I2d32d702da38bc0d87a1c159113bba32f4c03407 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/210837 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8879 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-24tegra132: add bootblock_mainboard_early_init()Aaron Durbin
Instead of hard coding certain pieces of a board in the common chipset code provide a way to initialize things early in the bootblock path. Add a bootblock_mainboard_early_init() function before console init to performany necessary mainboard initialization early in the bootblock. BUG=chrome-os-partner:31104 BUG=chrome-os-partner:31105 BUG=chrome-os-partner:29981 BRANCH=None TEST=built both on rush and ryu. rush still behaves the same. Change-Id: Idcf081eeffd189a4e2cbfeb8a4ac5dd0a3d1f838 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 4a523add6de03bea0d88e95b9dbb5e283c629400 Original-Change-Id: I7d93641dff3a961f120e8f0ec2d959182477ef87 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/210835 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8877 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-23Enable publishing of board ID where supportedVadim Bendebury
These boards are supposed to be able to determine the board ID at run time based on GPIO settings. BUG=chrome-os-partner:30489 TEST=verified that all boards build. Checked that storm proto0 reports board ID of 0 on the console Original-Change-Id: Iadd758a799d69e1e34579d7d495378856b64c45b Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/210119 (cherry picked from commit f4d41ddf906c1bf0d10da38011998fa0a630c332) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I0d5f94d3428157a70f0a9d711b57432e3f796733 Reviewed-on: http://review.coreboot.org/8722 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-03-23Include board ID calculations only when necessaryVadim Bendebury
For the majority of Chrome OS boards there is no need to include board ID calculation in any stage but ramstage, where the ID should be available for inclusion into the coreboot table. BUG=chrome-os-partner:30489 TEST=build only, no other tests yet Change-Id: I1451d52382bc48cc126d40267e0f61712f4a6d4b Original-Change-Id: Ib9c06698a399d31e79a9b14143343ba2ad46d0fb Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/210117 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> (cherry picked from commit 27dd40e85bfcd0a38f388bad4d79f5fbb77a7566) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/8720 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-03-23t132: Add support for tpm i2cFurquan Shaikh
Iniitialize I2C bus required for TPM operation. Problem observed was that if frequency is raised above 20KHz, TPM starts responding with NAKs either for address or for data. Need to look into that. BUG=None BRANCH=None TEST=Compiles successfully and TPM success messages seen while booting. Original-Change-Id: I9e1b4958d2ec010e31179df12a099277e6ce09e0 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/210001 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 01e87ae35431147f442e3f3e531537b8f0de1c9d) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I7dddc39d77f9a726fa51dd58ea9b7712c9a6fae2 Reviewed-on: http://review.coreboot.org/8715 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2015-03-13Use a common boardid.h instead of per board copiesVadim Bendebury
There is no point in duplicating boardid.h per board - they are all the same. Let's keep a single instance in the common include directory and let the linker report a problem if one tries using this function on a board where it is not supported. BUG=chrome-os-partner:30489 TEST=verified that coreboot builds fine for nyan_big and nyan_blaze. Original-Change-Id: Ifbe9c2287a1d828d4db74c637d1d02047ac4da25 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/209699 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit 589e6415faf18ca6aaf44da343dd33eadc8a53d3) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I8eef89cb822611a0050e5a50fc4b970eebd8d962 Reviewed-on: http://review.coreboot.org/8666 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-13ryu: Add TPS65913 regs/init for VDD_CPU 1.0VTom Warren
Other default slams should be added later to the init table once we know what the kernel touches. But for now, only VDD_CPU is needed. Also slipped in a minor name change in mainboard.c BRANCH=none BUG=none TEST=none, no HW here for me to test on yet Change-Id: Ifbe86192449ed0466085808a0a12a15a7b6a1795 Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-on: https://chromium-review.googlesource.com/208385 Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 53b332fb12cd685fbec265695333a70c4064524c) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/8645 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-03-13ryu: Add support for full LPDDR3 SDRAM BCT init via BootROMTom Warren
Once LPDDR3 init is supported in the ryu romstage, this can be reverted. Note that this 528MHz BCT has been pre-qualed by NVIDIA AE's, but will be updated as more tuning is done. BUG=none BRANCH=none TEST=Builds, BCT is in binary, but I have no HW here to test on Original-Change-Id: I315a9a5d56290bb5f51863b15053d2171db7b1e4 Original-Signed-off-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/208384 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit 660e40cb473d47ce763e79d6061367bf381a1c48) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I29ad31fc83f45ca8f92809a7dc252cf984c8c6fe Reviewed-on: http://review.coreboot.org/8643 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2015-03-05rush_ryu: Add new mainboardAaron Durbin
This is a clone of rush for the time being. All the incompatible bits can be moved later. Additional patches to follow. BUG=chrome-os-partner:30569 BRANCH=None TEST=Built coreboot for rush_ryu board Original-Change-Id: Iae56d016d0c328d83242b95f307fefaa8c68deec Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/207838 Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit cf2b88963743e40a35d841ef522172cb2448abbf) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I92a8b4d31fac4a25e3afa3b6e158e1dba0f80aab Reviewed-on: http://review.coreboot.org/8594 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
generated by cgit v1.2.3 (git 2.39.1) at 2024-07-17 19:14:38 +0000