Age | Commit message (Collapse) | Author | |
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2015-05-21 | Remove address from GPLv2 headers | Patrick Georgi | |
As per discussion with lawyers[tm], it's not a good idea to shorten the license header too much - not for legal reasons but because there are tools that look for them, and giving them a standard pattern simplifies things. However, we got confirmation that we don't have to update every file ever added to coreboot whenever the FSF gets a new lease, but can drop the address instead. util/kconfig is excluded because that's imported code that we may want to synchronize every now and then. $ find * -type f -exec sed -i "s:Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, *MA[, ]*02110-1301[, ]*USA:Foundation, Inc.:" {} + $ find * -type f -exec sed -i "s:Foundation, Inc., 51 Franklin Street, Suite 500, Boston, MA 02110-1335, USA:Foundation, Inc.:" {} + $ find * -type f -exec sed -i "s:Foundation, Inc., 59 Temple Place[-, ]*Suite 330, Boston, MA *02111-1307[, ]*USA:Foundation, Inc.:" {} + $ find * -type f -exec sed -i "s:Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.:Foundation, Inc.:" {} + $ find * -type f -a \! -name \*.patch \ -a \! -name \*_shipped \ -a \! -name LICENSE_GPL \ -a \! -name LGPL.txt \ -a \! -name COPYING \ -a \! -name DISCLAIMER \ -exec sed -i "/Foundation, Inc./ N;s:Foundation, Inc.* USA\.* *:Foundation, Inc. :;s:Foundation, Inc. $:Foundation, Inc.:" {} + Change-Id: Icc968a5a5f3a5df8d32b940f9cdb35350654bef9 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/9233 Tested-by: build bot (Jenkins) Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com> | |||
2015-03-27 | ryu: Remove old/unused BCT cfg files | Tom Warren | |
These are not needed/were never really used. SDRAM init will now be done in sdram.c, not the BootROM. BUG=chrome-os-partner:29921 BUG=chrome-os-partner:31031 BRANCH=None TEST=Built rush_ryu AOK. Change-Id: Id046592415574badb97026224e1e525c174eece4 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: aab1045817125cb022c8e8b89b85ef14e581baa7 Original-Change-Id: I7d25de3e888bb24e4c6e6dea2726510c97fe1730 Original-Signed-off-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/215863 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9030 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> | |||
2015-03-26 | ryu: Update BCT to Max Frequency 924MHz | Jimmy Zhang | |
Replace previous 528MHz BCT. This BCT contains four entries as below: 0: Samsung 1: Hynix 2: Micron 3: (spare) 528MHz Micron BUG=none BRANCH=none TEST=Built and tested on Micron LPDDR. Change-Id: Ibe9e299ac1dd4cabd390b2e78bbec6c0f3a3871b Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 3fcb3e82998c88220e87118efff0595ba3572e38 Original-Change-Id: I49e18ca8dc69f2ce9ded71f4f55c02a8b91f92b2 Original-Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/211479 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Reviewed-on: http://review.coreboot.org/8919 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> | |||
2015-03-25 | ryu: Add 4 LPDDR3 SDRAM BCTs | Aaron Durbin | |
These are used by the LPDDR3 code in sdram.c. Based on the schematic and email, I've filled in 4 slots in sdram_configs.c. My A44 returns RAMCODE 0 (using only bits 1:0) for Samsung SDRAM. I haven't tested the other 2 types of RAM (Hynix and Micron). The 4th slot is a fallback slow Micron config. Previously existing configurations were dropped. BUG=chrome-os-partner:29921 BUG=chrome-os-partner:31031 BRANCH=None TEST=Built for rush and rush_ryu. Change-Id: I55a737db269fe5fac1565d58bd8f8afcbc5beecb Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 9a431466171a85a5c8151e7466eb5f77862e7b44 Original-Change-Id: If216096ffc9e9836b6d082ad0668640b3eec37b7 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Id: a45e7788dd78697ac5f48b6cc64108ca0e4912dd Original-Change-Id: Ib7e8b814eb6dadb9b366536721876a3eeba0d2c0 Original-Signed-off-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/216000 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/8976 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> | |||
2015-03-25 | ryu: Add three more full LPDDR3 SDRAM BCTs | Jimmy Zhang | |
Add in the following BCTs to source code tree: Hynix 4GB 924MHz BCT Micron 4GB 924MHz BCT Samsung 4GB 924MHz BCT BUG=none BRANCH=none TEST=Built and tested Micron 924 bct on A44 board with Elpida memory chip. Change-Id: I59a5cc1133bf41a51f40a771ff0a7b7ef8d549fe Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 0a72f1b704928fad341bda460ecc349914ec612c Original-Change-Id: I9e5b54c3eb7ee4c4010b5aaf5dad030eba75108b Original-Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/210872 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Reviewed-on: http://review.coreboot.org/8904 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> | |||
2015-03-13 | ryu: Add support for full LPDDR3 SDRAM BCT init via BootROM | Tom Warren | |
Once LPDDR3 init is supported in the ryu romstage, this can be reverted. Note that this 528MHz BCT has been pre-qualed by NVIDIA AE's, but will be updated as more tuning is done. BUG=none BRANCH=none TEST=Builds, BCT is in binary, but I have no HW here to test on Original-Change-Id: I315a9a5d56290bb5f51863b15053d2171db7b1e4 Original-Signed-off-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/208384 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit 660e40cb473d47ce763e79d6061367bf381a1c48) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I29ad31fc83f45ca8f92809a7dc252cf984c8c6fe Reviewed-on: http://review.coreboot.org/8643 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> | |||
2015-03-05 | rush_ryu: Add new mainboard | Aaron Durbin | |
This is a clone of rush for the time being. All the incompatible bits can be moved later. Additional patches to follow. BUG=chrome-os-partner:30569 BRANCH=None TEST=Built coreboot for rush_ryu board Original-Change-Id: Iae56d016d0c328d83242b95f307fefaa8c68deec Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/207838 Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit cf2b88963743e40a35d841ef522172cb2448abbf) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I92a8b4d31fac4a25e3afa3b6e158e1dba0f80aab Reviewed-on: http://review.coreboot.org/8594 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com> |