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path: root/src/mainboard/google/rush_ryu/Kconfig
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2016-02-12chromebooks: Define GBB hardware IDsPatrick Georgi
This makes the test IDs the default, taken from depthcharge master (board/*/fmap.dts, hwid property). Change-Id: I25793962ac16f451f204dbba6ede6a64c847cfd5 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/13634 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins)
2016-02-09chromebooks: Configure Chrome EC board namesPatrick Georgi
For devices with Chrome EC, state the "board" name(s), so they're built as part of the image. A number of EC boards aren't supported in the Chrome EC master branch, they're brought along but commented out, waiting for a port to master in the Chrome EC code base. Change-Id: Ic6ab821de55cf9b4e8b48fe5ebc603adeb8bb28b Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/13548 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-11-07arm64: remove spin table supportAaron Durbin
As ARM Trusted Firmware is the only first class citizen for booting arm64 multi-processor in coreboot remove spintable support. If SoCs want to bring up MP then ATF needs to be ported and integrated. Change-Id: I1f38b8d8b0952eee50cc64440bfd010b1dd0bff4 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11908 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner <jwerner@chromium.org>
2015-10-31tree: drop last paragraph of GPL copyright headerPatrick Georgi
It encourages users from writing to the FSF without giving an address. Linux also prefers to drop that and their checkpatch.pl (that we imported) looks out for that. This is the result of util/scripts/no-fsf-addresses.sh with no further editing. Change-Id: Ie96faea295fe001911d77dbc51e9a6789558fbd6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/11888 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-08-26ChromeOS mainboards: Move more Kconfig symbols under CHROMEOSMartin Roth
Move the CHROMEOS dependent symbols VIRTUAL_DEV_SWITCH and VBOOT_DYNAMIC_WORK_BUFFER under the CHROMEOS config options for the mainboards that use them. Change-Id: Iad126cf045cb3a312319037aff3c4b1f15f6529d Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: http://review.coreboot.org/11336 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2015-08-26Google Kconfig: Add MAINBOARD_HAS_NATIVE_VGA_INIT in good placesMartin Roth
Add 'select MAINBOARD_HAS_NATIVE_VGA_INIT' which is just used as a gate symbol to display MAINBOARD_DO_NATIVE_VGA_INIT to the mainboards that are already selecting MAINBOARD_DO_NATIVE_VGA_INIT. Since MAINBOARD_HAS_NATIVE_VGA_INIT is not used in any code, this should not have any other effects. This fixes the warning: warning: (BOARD_SPECIFIC_OPTIONS) selects MAINBOARD_DO_NATIVE_VGA_INIT which has unmet direct dependencies (VENDOR_ASUS && BOARD_ASUS_KFSN4_DRE || MAINBOARD_HAS_NATIVE_VGA_INIT) Change-Id: I8ceee69ebae90dc32f55df58c2e80fe25397f049 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: http://review.coreboot.org/11301 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-08-21ChromeOS: Fix Kconfig dependenciesMartin Roth
Add CHROMEOS dependencies to selects for the following Kconfig symbols: CHROMEOS_RAMOOPS_DYNAMIC CHROMEOS_RAMOOPS_NON_ACPI CHROMEOS_VBNV_CMOS CHROMEOS_VBNV_EC CHROMEOS_VBNV_FLASH EC_SOFTWARE_SYNC LID_SWITCH RETURN_FROM_VERSTAGE SEPARATE_VERSTAGE VBOOT_DISABLE_DEV_ON_RECOVERY VBOOT_EC_SLOW_UPDATE VBOOT_OPROM_MATTERS VBOOT_STARTS_IN_BOOTBLOCK WIPEOUT_SUPPORTED This gets rid of these sorts of Kconfig errors: warning: BOARD_SPECIFIC_OPTIONS selects CHROMEOS_VBNV_EC which has unmet direct dependencies (MAINBOARD_HAS_CHROMEOS && CHROMEOS) Note: These two boards would never actually have CHROMEOS enabled: intel/emeraldlake2 has MAINBOARD_HAS_CHROMEOS commented out google/peach_pit doesn't have MAINBOARD_HAS_CHROMEOS Change-Id: I51b4ee326f082c6a656a813ee5772e9c34f5c343 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: http://review.coreboot.org/11272 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-05-21Remove address from GPLv2 headersPatrick Georgi
As per discussion with lawyers[tm], it's not a good idea to shorten the license header too much - not for legal reasons but because there are tools that look for them, and giving them a standard pattern simplifies things. However, we got confirmation that we don't have to update every file ever added to coreboot whenever the FSF gets a new lease, but can drop the address instead. util/kconfig is excluded because that's imported code that we may want to synchronize every now and then. $ find * -type f -exec sed -i "s:Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, *MA[, ]*02110-1301[, ]*USA:Foundation, Inc.:" {} + $ find * -type f -exec sed -i "s:Foundation, Inc., 51 Franklin Street, Suite 500, Boston, MA 02110-1335, USA:Foundation, Inc.:" {} + $ find * -type f -exec sed -i "s:Foundation, Inc., 59 Temple Place[-, ]*Suite 330, Boston, MA *02111-1307[, ]*USA:Foundation, Inc.:" {} + $ find * -type f -exec sed -i "s:Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.:Foundation, Inc.:" {} + $ find * -type f -a \! -name \*.patch \ -a \! -name \*_shipped \ -a \! -name LICENSE_GPL \ -a \! -name LGPL.txt \ -a \! -name COPYING \ -a \! -name DISCLAIMER \ -exec sed -i "/Foundation, Inc./ N;s:Foundation, Inc.* USA\.* *:Foundation, Inc. :;s:Foundation, Inc. $:Foundation, Inc.:" {} + Change-Id: Icc968a5a5f3a5df8d32b940f9cdb35350654bef9 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/9233 Tested-by: build bot (Jenkins) Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
2015-05-19Remove Kconfig variable that has no effectPatrick Georgi
MAINBOARD_HAS_BOOTBLOCK_INIT is only declared once and selected elsewhere (with no overlap), and never read. Remove it. Change-Id: Ica1f16182b556dbf4a3b747237af74bcc4c0608c Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10254 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2015-05-19arm64: Reorganize payload entry code and related KconfigsJulius Werner
Rename Kconfig options for secmon and spintable to be prefixed with ARM64_ instead of ARCH_, which seems to be the standard throughout the rest of coreboot (e.g. ARM_LPAE or X86_BOOTBLOCK_SIMPLE). I think this provides a clearer separation between generic options that are selected by the architecture (e.g. a hypothetical ARCH_HAS_FEATURE_X similar to some of the MAINBOARD_HAS_... we have) and options that only make sense in the context of a single architecture. Change-Id: I38c2efab833f252adbb7b61ef0af60ab25b768b0 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 5067e47bc03f04ad2dba044f022716e0fc62bb9e Original-Change-Id: I1b2038acc0d054716a3c580ce97ea8e9a45abfa2 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/270783 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/10242 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-28boards: remove VBOOT_(REFCODE|RAMSTAGE|ROMSTAGE)_INDEXAaron Durbin
These options will need to just be selected in within the .config files. There's not need in duplicating all these options. Change-Id: I7b670bc59a3b35e39eee4faecaf4aa779d47a3bb Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9959 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-22mainboards: Add CHROMEOS_VBNV_* where appropriatePatrick Georgi
For boards with MAINBOARD_HAS_CHROMEOS, we should also state what kind of storage is available for vboot's non-volatile data. The flags are taken from the chromium repository and have no effect with CHROMEOS disabled. Change-Id: I1747ad26c8c7f6d4076740ec2800dbd52c5d6b3d Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/9952 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-04-22google/*: Add MAINBOARD_HAS_CHROMEOS where appropriatePatrick Georgi
Some recently upstreamed boards are missing this flag Change-Id: I89d73970f23eed6ea127e620c38f9687b2f5b048 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/9949 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-04-22switch mainboards over to use BOARD_ID_AUTOStefan Reinauer
This patch switches the mainboards with board id straps to use BOARD_ID_AUTO instead of BOARD_ID_SUPPORT. On urara, which does not have those straps, the option is removed. (And re-added for urara derivatives through setting the config option BOARD_ID_MANUAL BRANCH=none BUG=chrome-os-partner:37593 TEST=emerg-nyan_big coreboot, emerge-urara coreboot, emerge-buranku coreboot Change-Id: I5ac4024c6f1f9b9d7a5179d88722c69b23b82bbd Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 22a470698f9c9ed275aa8150a5bb8d8cf368b050 Original-Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Change-Id: I48c291ad6f255a28c833bebc2638bfafa2782e74 Original-Reviewed-on: https://chromium-review.googlesource.com/262935 Original-Reviewed-by: Vadim Bendebury <vbendeb@google.com> Reviewed-on: http://review.coreboot.org/9906 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-14CBFS: Correct ROM_SIZE for ARM boards, use CBFS_SIZE for cbfstoolJulius Werner
Some projects (like ChromeOS) put more content than described by CBFS onto their image. For top-aligned images (read: x86), this has traditionally been achieved with a CBFS_SIZE Kconfig (which denotes the area actually managed by CBFS, as opposed to ROM_SIZE) that is used to calculate the CBFS entry start offset. On bottom-aligned boards, many define a fake (smaller) ROM_SIZE for only the CBFS part, which is not consistently done and can be an issue because ROM_SIZE is expected to be a power of two. This patch changes all non-x86 boards to describe their actual (physical) ROM size via one of the BOARD_ROMSIZE_KB_xxx options as a mainboard Kconfig select (which is the correct place to declare unchangeable physical properties of the board). It also changes the cbfstool create invocation to use CBFS_SIZE as the -s parameter for those architectures, which defaults to ROM_SIZE but gets overridden for special use cases like ChromeOS. This has the advantage that cbfstool has a consistent idea of where the area it is responsible for ends, which offers better bounds-checking and is needed for a subsequent fix. Also change the FMAP offset to default to right behind the (now consistently known) CBFS region for non-x86 boards, which has emerged as a de-facto standard on those architectures and allows us to reduce the amount of custom configuration. In the future, the nightmare that is ChromeOS's image build system could be redesigned to enforce this automatically, and also confirm that it doesn't overwrite any space used by CBFS (which is now consistently defined as the file size of coreboot.rom on non-x86). CQ-DEPEND=CL:231576,CL:231475 BRANCH=None BUG=chromium:422501 TEST=Built and booted on Veyron_Pinky. Change-Id: I89aa5b30e25679e074d4cb5eee4c08178892ada6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: e707c67c69599274b890d0686522880aa2e16d71 Original-Change-Id: I4fce5a56a8d72f4c4dd3a08c129025f1565351cc Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/229974 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9619 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-13ryu: Add and select DO_DSI_INIT config optionJimmy Zhang
Enable display supporting functions by select DO_DSI_INIT BUG=chrome-os-partner:34336 BRANCH=none TEST=build ryu and rush Change-Id: Ie0e03506702ddab03d7f3fd2528c67c02126c7be Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 7133dfcd1afa221be92c6398221cf210d9eddf17 Original-Change-Id: I3a9f93107333ebf83ff235eb1b1e02fc747df3c6 Original-Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/234272 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9585 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-10tegra132: Pass panel spec to lib_sysinfoJimmy Zhang
panel spec such as resoultion, bits per pixel are needed to pass to depthcharge/payload for displaying bitmap onto panel. Enable display code only if mainboard selects MAINBOARD_DO_NATIVE_VGA_INIT. Otherwise build breaks for boards that do not support display init yet. BRANCH=none BUG=chrome-os-partner:31936 TEST=Compiles for both rush and ryu. Display comes up for ryu in both normal and dev mode. Change-Id: I81b4d289699e7b0c2758ea1a009cbabaf8a2ce28 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: b9b42486f203d332f6068ccd6f4a1a982d327a6b Original-Change-Id: I5c8fde17d57e953582a1c1dc814be4c08e349847 Original-Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com> Original-Commit-Id: ce2883b21d3fbfd54eac3a355fb34ec70e9f31ad Original-Change-Id: Ib4a3c32f1ebf5c6ed71c96a24893dcdee7488b16 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: http://review.coreboot.org/9519 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-10gpio: decouple tristate gpio support from board IDDavid Hendricks
This deprecates TERTIARY_BOARD_ID. Instead, a board will set BOARD_ID_SUPPORT (the ones affected already do) which will set GENERIC_GPIO_SUPPORT and compile the generic GPIO library. The user is expected to handle the details of how the ID is encoded. BUG=none BRANCH=none TEST=Compiled for peppy, nyan*, storm, and pinky Change-Id: Iaf1cac6e90b6c931100e9d1b6735684fac86b8a8 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 93db63f419f596160ce2459eb70b3218cc83c09e Original-Change-Id: I687877e5bb89679d0133bed24e2480216c384a1c Original-Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/228322 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/9413 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-08ryu: Add vboot2 supportFurquan Shaikh
CQ-DEPEND=CL:221598, CL:*178568 BUG=chrome-os-partner:32684 BRANCH=None TEST=Compiles and boots to kernel prompt Original-Change-Id: If7c725333b45a92f951ab674c3e4bd6a51c180c2 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/221577 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit 9f5a6ae8cb6e7136ab0f0158a864dfc8ccf5c24f) Signed-off-by: Aaron Durbin <adurbin@chromium.org> Change-Id: If83dece2b4f2aa7d1457c723131efaa9b1169009 Reviewed-on: http://review.coreboot.org/9431 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2015-03-28ryu: use generic spin tableAaron Durbin
With the generic spin table support in place, use that. BUG=chrome-os-partner:32082 BRANCH=None TEST=Booted into kernel. Change-Id: I8644f8a81b24bf4e00f8fac1d1018f9db77c952f Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: b1a4fe27070a80c8448051ec0565120901378673 Original-Change-Id: Id0832a4553101a366f011099e0744f6630d91924 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/218656 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9086 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-28ryu: Get rid of coreboot setting up DMA areas for libpayloadFurquan Shaikh
BUG=chrome-os-partner:31634 BRANCH=None TEST=Compiles successfully and dma areas are setup fine by libpayload mmu Change-Id: I6d2d1dbcfc9bdeea94c89a9a3fce486203269642 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 0425e87f21bcb92861240d6437769a5b28e9929b Original-Change-Id: I1034a4dcf6c9ee56bee4ea5d18e91a8d51895429 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/217571 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9072 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-26ryu: support for DMA regionAaron Durbin
Currently ryu needs a DMA region in order to communicate with USB devices. Therefore, add that region to the memory map. BUG=chrome-os-partner:31293 BRANCH=None TEST=With usb added am able to talk to a USB mass storage device albeit inconsistently. Change-Id: I7efaf2ba44cc94dc64af3f1cd916bdc5c7ff0795 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: e93389479518ee28dc3477da0c6e6e33fa8a47d1 Original-Change-Id: I6b5c052ccaafce30705349e07639dffbb994901f Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/212162 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8926 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-26t132: ryu: Correct how board id is retrievedJimmy Zhang
Two changes: 1. A44 ID straps use different gpio pins than nyan. 2. A44 uses tristate values instead two state values. BUG=none BRANCH=none TEST=Built and tested on A44 board. Change-Id: I6a36f6da0c9f6168780606ba76595c7a0af8e8bf Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 2eb0cae0e3396da1eaeaa72411c4b74300138a7b Original-Change-Id: Ia2a4309d3b63b0a94d79465dd727b01fae01e1b9 Original-Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/211753 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/8920 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-26ryu: use EC proto v3 over i2cAaron Durbin
Ryu's EC talks proto v3 over i2c. Select the correct protocol. BUG=chrome-os-partner:31148 BRANCH=None TEST=Built and ran on ryu. Coreboot can speak to the EC now. Change-Id: Iaed0d2db3c3c93667d65beea98b9719bdbbbfe41 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: b71cad3bb1e9b64c48b6f2eeb7573c408a508fb3 Original-Change-Id: I50e192cd58f7a29103ab94afc002da18822d4080 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/211240 Original-Reviewed-by: Stefan Reinauer <reinauer@google.com> Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8915 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-03-26ryu: enable vboot firmware verificationAaron Durbin
Add the supporting Kconfig options and infrastructure for performing vboot firmware verification. BUG=chrome-os-partner:30784 BRANCH=None TEST=Built and ran on ryu into depthcharge noting vboot paths being taken. Change-Id: I1d803208cd5789bd73244b91beac6a5a4598ea70 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: a2e7d84725739843a1ed1868fcadebb60477a6dc Original-Change-Id: Ie4c8c3939990a12fc528423948b236230392eb7c Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/211134 Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8914 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
2015-03-23Enable publishing of board ID where supportedVadim Bendebury
These boards are supposed to be able to determine the board ID at run time based on GPIO settings. BUG=chrome-os-partner:30489 TEST=verified that all boards build. Checked that storm proto0 reports board ID of 0 on the console Original-Change-Id: Iadd758a799d69e1e34579d7d495378856b64c45b Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/210119 (cherry picked from commit f4d41ddf906c1bf0d10da38011998fa0a630c332) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I0d5f94d3428157a70f0a9d711b57432e3f796733 Reviewed-on: http://review.coreboot.org/8722 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-03-05rush_ryu: Add new mainboardAaron Durbin
This is a clone of rush for the time being. All the incompatible bits can be moved later. Additional patches to follow. BUG=chrome-os-partner:30569 BRANCH=None TEST=Built coreboot for rush_ryu board Original-Change-Id: Iae56d016d0c328d83242b95f307fefaa8c68deec Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/207838 Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit cf2b88963743e40a35d841ef522172cb2448abbf) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I92a8b4d31fac4a25e3afa3b6e158e1dba0f80aab Reviewed-on: http://review.coreboot.org/8594 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
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