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This patch creates a new variant screebo4es.
The new variant will support only ESx samples. The existing rex
variant will support the QS samples.
BUG=b:292280656
TEST=Able to build google/screebo4es board and boot on target
hardware.
Change-Id: If77b4a773bee3633008d39c1886b61869c9618de
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76668
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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BUG=b:290894460
TEST=`emerge-rex coreboot chromeos-bootimage`
then check variant name with image*.bin.
Signed-off-by: YH Lin <yueherngl@google.com>
Change-Id: I8f739485dbaab074f57eaa4dacc9f228a3f4aa14
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76667
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch increases the `tcc_offset` to reduce the TCC
(Thermal Control Circuit) activation temperature to avoid running
into abrupt power off during power cycle tests.
On Intel processors, the core frequency can be by an HW agent when
the current temperature reaches the TCC activation temperature.
The default TCC activation temperature is specified by MSR_IA32_TEMPERATURE_TARGET (which is 90°C for google/rex variants).
However, this patch adjusted the TCC by specifying an offset in
degrees C (i.e., using `tcc_offset` from variant override device tree).
Note: The bigger the TCC offset is, the lower the effective TCC activation temperature would be, to ensure that processors can be throttled earlier before the system critical overheats.
BUG=b:283008762
TEST=Able to perform power cycle on google/screebo w/o any crash/shutdown.
Change-Id: Ib19703877dbbfc26b2d9f538dda4f10c27cf872d
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76658
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
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Choose BOARD_GOOGLE_MODEL_REX while setting up the default config value
for variants created using google/rex model.
TEST=Able to build and boot google/rex.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I107f4e375b5c9e9c0fb80c4d396164c10c1fc1e7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76657
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
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This patch creates a new variant rex4es. The new variant will support ESx samples. The existing rex variant will support the QS samples.
BUG=b:290732344
TEST=Able to build google/rex4es board and boot on target hardware.
Change-Id: I25dd1f42ee812f47289da0c2ef7aa79d6f340d48
Signed-off-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76605
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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This patch creates a rex model so that other variants developed using
`rex` baseboard are easy to land without duplicating the config
selection.
So far, `rex0` and `rex_ec_ish` are developed using the `rex` model.
The plan is to extend the support for `rex4es` and `rex4es_ec_ish`
variants.
TEST=Able to build and boot google/rex.
Change-Id: Id4e8d1162da93b7266ee1108f870e89b6d884ab9
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76608
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
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Follow baseboard Rex to make GPIO changes
BUG=b:286187821
TEST=Ability to enable and disable WIFI function in OS.
Change-Id: I805ce859c42c7c0a9d117418a80555658f844e09
Signed-off-by: Wentao Qin <qinwentao@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76551
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
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This patch updates the Type-C USB2/3 port mapping to reflect the mux
connection change as mentioned in previous patch
commit ee3f796200bf3baf8a1906 (mb/google/rex/var/ovis: Fix mux
change as per schematics).
Here is the correct port mapping after considering the mux swap:
+--------------------------------+-------------+---------------+
| TCSS-USB Mapping | Port C0 | Port C1 | Port C2 |
+------------------+-------------+-------------+---------------+
| USB2-Port | 2 | 3 | 1 |
| USB3-Port | 0 | 2 | 1 |
+------------------+-------------+-------------+---------------+
BUG=b:289300284
TEST=Able to build and boot google/ovis to get display over Type-C1
and Type-C2 port.
Change-Id: I460004842dd8fcdc03fca6639d03e422259380ca
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76464
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change SD_CLKREQ_ODL from GPP_D19 to GPP_D18
BUG=b:291051683
BRANCH=none
TEST=emerge-rex coreboot
Change-Id: Ic102e42482328580c5334e6ff036b774f5002e00
Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76565
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Simon Zhou <zhouguohui@huaqin.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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Change i2c[0] parameter Thd:dat = 50ns;
Change i2c[1] parameter Thd:dat = 100ns;
BUG=b:287898252
BRANCH=none
TEST=Test success by EE.
Change-Id: Ibdbe4e17cf21c914b48fa6dc7d3eecf8218a2d8b
Signed-off-by: Zhongtian Wu <wuzhongtian@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76430
Reviewed-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch disables early EC sync to avoid an idle delay (~3sec)
without a provision to notify the user about some critical task
in progress.
Doing EC sync at later stage allows us to notify using graphical msg
on screen to make user aware of the WIP task.
BUG=b:279944831
TEST=Able to perform EC sync from depthcharge on google/rex.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I03ed40827c50e75ceaaf94e30d675014ebf22dac
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74837
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
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Change touchscreen reset_gpio GPP_C01 -> GPP_D07;
Change touchscreen enable_gpio GPP_C00 -> GPP_B17.
BUG=b:289425753
BRANCH=none
TEST=Test success by EE.
Change-Id: I7be6a2b4e87126b281f138c819d2a0a5b1af5821
Signed-off-by: Zhongtian Wu <wuzhongtian@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76429
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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Add karis supported memory parts in mem_parts_used.txt, generate
SPD id.
1. MICRON MT62F1G32D2DS-023 WT:B
2. HYNIX H9JCNNNBK3MLYR-N6E
3. HYNIX H58G56BK8BX068
4. SAMSUNG K3KL8L80CM-MGCT
BUG=b:291018417
TEST=Use part_id_gen to generate related settings
Change-Id: I87c2c4f59454dec84d29590ee91379c9fa60ddcf
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76443
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This configures GPIO IO Standby State of GPP_F00 - GPP_F05 as masked
for CNVi.
Meteor Lake rex platform does not wake up from low power state by
bluetooth keyboard and mouse properly. It is identified that IO Standby
State needs to be configured as masked to function properly for CNVi.
BUG=b:286803481
TEST=Make screebo suspend to s0ix state and press a key from
bluetooth keyboard. Check the platform wakes up properly from s0ix.
Change-Id: I7fd342e52fa0f9126eab4c857a5adc04c26e49c6
Signed-off-by: Wentao Qin <qinwentao@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76406
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch enables PCH to CPU energy report feature which can be used
by Intel Telemetry Driver.
BUG=b:269563588
TEST=Able to build and boot google/rex and perform below check to ensure
the energy reporting is correct
w/o this cl:
# lspci -s 00:14.2 -vvv | grep "Region 0"
Region 0: Memory at 957f8000 (64-bit, non-prefetchable) [size=16K]
# iotools mmio_read32 0x957f8068 #i.e., 104th offset
0xXXXX0000
w/ this cl:
#lspci -s 00:14.2 -vvv | grep "Region 0"
Region 0: Memory at 957f8000 (64-bit, non-prefetchable) [size=16K]
# iotools mmio_read32 0x957f8068 #i.e., 104th offset
0xXXXXfc004
Change-Id: I9bd4625ea311a05071878aaec68433a1ba018c0d
Signed-off-by: Sukumar Ghorai <sukumar.ghorai@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76353
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
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There is no PCH FIVR participant on MTL and we should remove it
in Rex.
TEST=compile ok and make sure there no TPCH device in acpi
BUG=b:290322310
Change-Id: Icf4be86da3f3cb9b1f0a3f2586b029a533c3e6a9
Signed-off-by: Kane Chen <kane.chen@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76402
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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for saving boot time, change ramstage compression from LZMA to LZ4.
Boot time saving is around 35ms (30-37ms) while SPI size impact is 230KB.
For detail, refer below.
Existing: LZMA(55.6 ms)
8:starting to load ramstage 894,519 (0)
15:starting LZMA decompress (ignore for x86) 903,556 (9,036)
16:finished LZMA decompress (ignore for x86) 949,997 (46,441)
9:finished loading ramstage 950,179 (182)
Changed: LZ4(17.8ms)
8:starting to load ramstage 900,876 (0)
17:starting LZ4 decompress (ignore for x86) 917,650 (16,774)
18:finished LZ4 decompress (ignore for x86) 918,690 (1,040)
9:finished loading ramstage 918,849 (158)
Size impact (73KB * 3 = 219KB)
fallback/ramstage 0x62940 stage 240281 LZ4 (405524 decompressed)
fallback/ramstage 0x62940 stage 165452 LZMA (405524 decompressed)
BUG=b:286930648
TEST= Boot to OS and check boot time
Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: I6610f405d287bff2eb4eee6f09026e3361405ded
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75769
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
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This configures GPIO IO Standby State of GPP_F00 - GPP_F05 as masked
for CNVi to function properly with the connected bluetooth devices and
wake up from low power state.
BUG=None
TEST=None
Change-Id: I977493fd95a99381279f5a3f5e679e4893369b8a
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76362
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com>
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This configures GPIO IO Standby State of GPP_F00 - GPP_F05 as masked
for CNVi.
Meteor Lake rex platform does not wake up from low power state by
bluetooth keyboard and mouse properly. It is identified that IO Standby
State needs to be configured as masked to function properly for CNVi.
BUG=None
TEST=Make rex platform suspend to s0ix state and press a key from
bluetooth keyboard. Check the platform wakes up properly from s0ix.
Change-Id: Ia98abde584699fa01acba47a9df4ef6332ac16fd
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76338
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The actual NVM size of camera module is 64KB; however, only 8KB is in
use to store data. This reduces the size of both NVM0 and NVM1 to 8KB
to minimize the time taken to read NVM and launch Camera preview.
BUG=NONE
TEST=Launch Chrome camera application and check the time taken to
read eeprom from camera service log and show camera preview. It takes
2 to 3 seconds to show camera preview while it takes 4 to 5 seconds
without the changes.
Before the changes:
06:21:04.204944Z OpenDevice(): camera_id = 1
06:21:07.297584Z Read camera eeprom from eeprom
06:21:08.763491Z Read camera eeprom from nvmem
After the changes:
21:37:23.923676Z OpenDevice(): camera_id = 1
21:37:24.386020Z Read camera eeprom from eeprom
21:37:24.574515Z Read camera eeprom from nvmem
Change-Id: I0e2272b3307fea60ea7406fc6899ae2cb0134fa3
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76189
Reviewed-by: Kiran2 Kumar <kiran2.kumar@intel.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
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This patch skips reading the MEM_CH_SEL GPIO aka GPP_E13 to determine
the memory channel configuration. The signal behavior is not proper,
hence limiting the DIMM capacity to half (only MC0 is enabled).
This patch always reports the full memory capacity as in dual channel
(both MC0 and MC1 enabled).
This change is necessary to ensure that the system reports the correct
memory capacity, even if the MEM_CH_SEL GPIO is not working properly.
BUG=b:290174538
TEST=Able to detect 32GB memory capacity while booting google/ovis.
Without this patch:
localhost ~ # cat /proc/meminfo
MemTotal: 16183080 kB
With this patch:
localhost ~ # cat /proc/meminfo
MemTotal: 32673664 kB
Change-Id: I6c3fa941abb044b79b13785f7b65d09957f0487d
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76359
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
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This CL corrects the trigger for HID over SPI from Level to Edge.
BUG:None
TEST:Tested with I2C and SPI
Change-Id: I78937af22df22d80a702477b6790a7aa40d782a4
Signed-off-by: Eran Mitrani <mitrani@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76116
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
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Set tcc_offset value to 20 in chipset for Thermal Control
Circuit (TCC) activation feature for meteorlake silicon.
Also, remove tcc_offset default value from rex baseboard
and variants.
BUG=b:270664854
BRANCH=None
TEST=Build FW and test on rex board
Change-Id: Ieec1b7e0873eef46a56e612ed1d9445019b1f4a9
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76232
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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Change i2c[3] parameter to meet below timing:
t-HIGH > 600ns;
900ns > Thd:dat > 300ns.
BUG=b:286030723
BRANCH=none
TEST=Test success by EE.
Change-Id: I4b2d958a5a0d41e2cfa1087f5cb94cc83bbb1739
Signed-off-by: Zhongtian Wu <wuzhongtian@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76169
Reviewed-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Set tcc_offset value to 10 in devicetree for Thermal Control
Circuit (TCC) activation feature for ovis.
BUG=b:270664854
TEST=Build and boot google/ovis.
Change-Id: I0ef626f6cc460f1b460297804b97038705efaf4c
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76230
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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This patch adds a power limit for Ovis with 28W Intel Meteor Lake
silicon.
Reference: Intel MTL-UH_Power_Map_Rev1p2, doc: 640982
BUG=b:289854108
TEST=Able to boot google/ovis with power limit being overridden as
appropriate to 28W.
Change-Id: I312c70720fd89261c53d5bd4f45236e829d6c790
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76229
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
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Currently, boards with ES2 silicon are unable to boot with crashlog
enabled because crashlog driver is unable to handle invalid data.
Temporarily disable the crashlog to unblock development until the issue
is fixed.
BUG=b:289749310
TEST=Able to boot to the OS on Screebo
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: Ic63cf9cf5bfa2c92d8f2c5b13df2f23dc118b389
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76231
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
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Change i2c[0] parameter to meet touchscreen timing.
Thd:dat > 100ns.
BUG=b:287898252
BRANCH=none
TEST=Test success by EE.
Change-Id: I30e7c87d788f7f144276c45e8475af65f1f132ae
Signed-off-by: Zhongtian Wu <wuzhongtian@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76190
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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This patch enables BT offload feature for soundwire audio over SSP1.
BT mode is selected via FW_CONFIG and corresponding VGPIOs are
programmed.
BUG=b:275538390
TEST=build and verify BT offload on rex soundwire audio
Change-Id: I99df78787d9f54c91bcedf6f70352890a715cdb3
Signed-off-by: Uday M Bhat <uday.m.bhat@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75924
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
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This configures the SoC to flip the orientation of the AUX pins to
follow the orientation of the cable when using the kb8010 retimer. This
is necessary when there is no external retimer/mux or the retimer/mux
does not implement the flip. The kb8010 retimer does not support this
feature, so let the SoC do the flip.
BUG=b:267589112
TEST=verified DP-ALT mode works in both cable orientations on rex with
reworked kb8010 DB by flykt@
Change-Id: Iad093e27617b80f8301008deb00b57fb9b3a48ba
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76137
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
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This patch performs below operations to enable LAN0.
- Complete the LAN PEREST power sequencing
- Program the SRC_CLKREQ (GPP_D20) with correctly.
- Add overridetree.cb entry to configure the LAN0 device.
BUG=b:289395519
TEST=Able to boot google/ovis with LAN0 being enabled.
Change-Id: I91b0a76395ade4459cf8705c333728a71f95df14
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76213
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch performs below operations to enable LAN1.
- Add overridetree.cb entry to configure the LAN device.
- Complete the LAN1/SD PEREST power sequencing
BUG=b:289395519
TEST=Able to boot google/ovis with LAN1 being enabled.
Change-Id: Ifb67cb8e6fc03e3ff14b1b3d8382322fd0b3aeff
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76212
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch configures GPP_V12 aka SOC_SLP_LAN_L properly as per the
Ovis schematics dated June'23 to ensure LAN port is not in sleep.
BUG=b:289395519
TEST=Able to measure SLP_LAN PIN and confirm it's deasserted.
Change-Id: I1fe8715862823149c8a1f05e3e4463a615fbbbce
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76211
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch configures GPP_C10 aka EN_LAN_RAILS properly as per the Ovis
schematics dated June'23 to ensure LAN ports having power.
BUG=b:289395519
TEST=Able to measure LAN port power is enabled with this CL.
Change-Id: I3f4d611313325dba66905e0c8ef391765a1fe7a7
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76210
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
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This patch updates the mux connection to reflect the Ovis schematics
dated June to ensure Type-C1 is able to work in DP-ALT mode.
BUG=b:289300284
TEST=Able to get display over Type-C1 port.
Change-Id: I223eb3a96e6a1b3abb4168fcf59c0df04c1b4498
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76149
Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
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BUG=b:262501347
TEST=Boot on Ovis board.
Change-Id: I43aac857e3ec7989c9ab5201cd8f24a7c877e76b
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76151
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
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The SOC/IOE SRAM device is used to store crash logs. Previously, the
crashlog enablement was hardcoded in the baseboard.common module.
This commit moves the crashlog enablement logic to the baseboard
module, so that it can be enabled or disabled based on the specific
baseboard.
Additionally, the SOC/IOE SRAM is now enabled by default in the
baseboard devicetree.cb file. This prevents the system from hanging
if the SOC/IOE SRAM device is not present.
BUG=b:262501347
TEST=Able to build and boot google/screebo with this patch.
w/o this patch:
[ERROR] SOC SRAM device not found!
[ERROR] IOE SRAM base not valid
Change-Id: I02d581e5b62cfa114a3761a9704ad9f24dead8aa
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76134
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
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This patch enables SaGv with fixed frequency and gears for Ovis.
Restrict memory speed to 6400 MTS as per board design.
BUG=b:282164577
TEST=Verified the settings on google/ovis using debug FSP logs
Change-Id: Ia9703344a8ae9d2ba44a16c62afab820fd8e2177
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76138
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Set tcc_offset value to 20 in devicetree for Thermal Control
Circuit (TCC) activation feature for rex variants.
BUG=b:270664854
BRANCH=None
TEST=Build FW and test on rex board
Change-Id: I0567b6240fcb53f38158c381b700169475cf3795
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76110
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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Enable crashlog for rex. Select config options SOC_INTEL_CRASHLOG,
and SOC_INTEL_IOE_DIE_SUPPORT. Also enable ioe_shared_sram and
pmc_shared_sram devices.
BUG=b:262501347
TEST=Able to trigger Crashlog, BERT table gets generated and decodes
as expected.
Change-Id: I3d3a9fb41d1293f021ad9de9b29c756cb7559373
Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74770
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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This patch avoids random hang issue observed after booted to OS on LPDD5/x platforms due to CLK not tuned properly in SAGV point 0, 2133MT/s.
As per Intel doc 769410 the expected work around is to change SAGV
point 0 from 2133 G4 to 3200 G4.
BUG=b:287170545
TEST=Able to perform 500 power cycles on google/rex without any hang.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I02a9cadc075f396549703d7a008382e76268f865
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76076
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Configures ISH related GPIO's based on FW_CONFIG obtained from CBI.
BUG=b:280329972,b:283023296
TEST= Set bit 21 of FW_CONFIG with CBI
Boot rex board
Check that ISH is enabled, loaded, and functional
Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com>
Change-Id: I3f0f9a7c8318fa9ae59b6f613eafdacbfa07c749
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75525
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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Rename shared SRAM aliases for IOE and PMC to make them more readable.
pci device 13.3 is IOE shared sram, renamed to ioe_shared_sram.
pci device 14.2 is PMC shared sram, renamed to pmc_shared_sram.
Rename them in SOC code as well as mainboard to make sure the patch
builds for the relevant boards.
BUG=b:262501347
TEST=Able to build.
Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati@intel.com>
Change-Id: I02a8cacc075f396549703d7a008382e76258f865
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75999
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The CNVi PCI device is required for the system to boot properly.
By ensuring that this device is enabled, we can prevent the below
error message from appearing and ensure that the system boots successfully.
BUG=b:274421383
TEST=Able to build and boot google/ovis without any error.
w/o this patch:
[ERROR] CNVi WiFi is enabled without CNVi being enabled
[ERROR] CNVi BT is enabled without CNVi being enabled
Change-Id: I4dbae14f0cfccf96a33437a0e2fdefb508209354
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76001
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
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Pre-boot display is not POR for google/rex hence disable the config
ENABLE_TCSS_DISPLAY_DETECTION.
BUG=b:247670186
TEST=Build and boot to google/rex and make sure that display over TCSS
works in the OS
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: Ib55e251a4620c7a375ee2f27763154c39207236e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75927
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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Since GPP_C03/GPP_04 are floating in HW design, we set HBR smbus pin
as NC, in case it prevents ese and cse from entering suspend.
BUG=b:283053968
TEST=Verified on screebo non-TBT SKU, suspend and resume works.
Change-Id: I401db32f0286de61ce3ab6c61de9528ec76cb51d
Signed-off-by: Simon Zhou <zhouguohui@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75643
Reviewed-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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USB type-A port with same PLD.token information as USB type-C port,
causes conflict while generating ACPI code for the EC CONN device.
Use a different PLD.token number for type-A port to fix the issue.
BUG=b:286328285
TEST=check ACPI can have right USB port in EC CON.
before patch:
Package (0x02)
{
"usb2-port",
\_SB.PCI0.XHCI.RHUB.HS01
},
Package (0x02)
{
"usb3-port",
\_SB.PCI0.TXHC.RHUB.SS01
},
after patch:
Package (0x02)
{
"usb2-port",
\_SB.PCI0.XHCI.RHUB.HS01
},
Package (0x02)
{
"usb3-port",
\_SB.PCI0.TXHC.RHUB.SS03
},
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: If3e76c11dd6808eee4c9c2f3f71604a60379b5a5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75911
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
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Ovis uses MTL-H.
BUG=b:274421383
TEST=util/abuild/abuild -p none -t google/rex -x -a -b ovis
TEST=cros build-packages --board ovis chromeos-bootimage
Change-Id: I284c72b902490187d0b15e4fc81650af1cfa16d7
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75887
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch renames config `SOC_INTEL_METEORLAKE_U_P` to
`SOC_INTEL_METEORLAKE_U_H` as per Intel Meteor Lake Processor EDS
version 1.3.1 (doc number: 640228).
With new branding, the MTL-U/H-Processor Line offered in a 1-chip platform that includes the Compute, SOC, GT, and IOE tile on the
same package.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I032be650bbfef0bf0ef86bb37417b1d854303501
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75931
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
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Configure I2C0/1/3/4 timing in devicetree to ensure I2C devices
meet timing requirement. Note that I2C5 timing will be updated
separately when the tuning done
BUG=b:280559903
TEST=Build and check I2C devices timing meet spec.
| | I2C0-Codec | I2C0-WFC | I2C1 | I2C3 | I2C4 |
|-------------|------------|----------|--------|-------|---------|
| FSMB(KHz) | 347 | 343.2 | 389.3 | 393.7 | 381.9 |
| TLOW(us) | 2.1 | 2.093 | 1.895 | 1.902 | 1.953 |
| THIGH(us) | 0.647 | 0.628 | 0.602 | 0.62 | 0.612 |
| THD:STA(us) | 0.633 | 0.64 | 0.601 | 0.6 | 0.601 |
| TSU:STA(us) | 0.617 | 0.621 | 0.619 | 0.659 | 0.61 |
| TSU:STO(us) | 0.656 | 0.647 | 0.667 | 0.727 | 0.634 |
| TBUF(us) | 86.15 | >14.088 | >9.833 | >8 | >10.366 |
Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Change-Id: I5421e4fe68e856bbe9f19544954a94670c895a47
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75150
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
|
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Remove rp2 and add rp1/rp3 for screebo
BUG=b:286187816
BRANCH=none
TEST=emerge-rex coreboot and verify TBT works.
Change-Id: I1013d26c705f2a3f9378d944bd863d94f319d36c
Signed-off-by: Rui Zhou <zhourui@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75832
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Simon Zhou <zhouguohui@huaqin.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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Enable DDI on ports 1 to 4 for Type-C DisplayPort.
BUG=b:274421383
TEST=util/abuild/abuild -p none -t google/rex -x -a -b ovis
Change-Id: I40f967b12b11c10a1a9329bfb42ebec5a8d7738f
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75579
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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This configures the SoC to flip the orientation of the AUX pins to
follow the orientation of the cable when using the anx7452 retimer. This
is necessary when there is no external retimer/mux or the retimer/mux
does not implement the flip. The anx7452 retimer does not appear to
support this feature, so let the SoC do the flip.
BUG=b:267589042,b:281006910
TEST=verified DP-ALT mode works on rex using both cable orientations
Change-Id: Ibb9f442d2afd81fb5dde4bca97c15457837f9f4a
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75827
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
|
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TCSS and TBT use the same lane on schematic. Update the port start
from 0 to match the Intel schematic. You can better follow the it
without convert the port number.
Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: Ic6631dcbbd9f6c79c756b015425e2da778eb395e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75892
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
|
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This patch enables BT offload feature on Rex over SSP1.
BT mode is selected via FW_CONFIG and corresponding VGPIOs are
programmed.
BUG=b:275538390
TEST=Verified audio playback using BT speaker/headset in I2S mode on google/rex.
Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Change-Id: I46e9702add37464122ffc78826ebf8a6c5b5b07c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72881
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This patch enables adding variant specific ASL code
TEST=Kernel driver is able to communicate with device
Signed-off-by: Eran Mitrani <mitrani@google.com>
Change-Id: I231482d56dd4afa150766c07cfde105158e5e124
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74886
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
|
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Add driver to support ELAN touchscreen using SPI for rex
* See "HID Over SPI Protocol Specification" section 5.2 - ACPI enum
* https://www.microsoft.com/en-us/download/details.aspx?id=103325
BUG=b:278783755
TEST=Kernel driver is able to communicate with device. Also tested
S0ix, ran 'suspend_stress_test -c 1' - no issues in suspend/resume.
Signed-off-by: Eran Mitrani <mitrani@google.com>
Change-Id: Id51d385ce350cef23da4184b044c74569f4dd3f0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74885
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
|
|
Add default Intel DPTF.
BUG=b:274421383
TEST=util/abuild/abuild -p none -t google/rex -x -a -b ovis
Change-Id: Ib023f6d6d184f6935a6a454250755502a46b707f
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75580
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
|
|
+-------------+----------------+------------+---------------------------------+
| PCH USB 2.0 | Connector Type | OC Mapping | Remarks |
+-------------+----------------+------------+---------------------------------+
| 1 | Type-C | OC_0 | Type C port - TCP1 |
| 2 | Type-C | OC_0 | Type C port - TCP0 |
| 3 | Type-C | OC_0 | Type C port - TCP2 |
| 4 | Type-A | OC_3 | USB3.2 Gen2x1 Type-A Port – TAP0|
| 7 | Type-A | OC_3 | TAP1 |
| 8 | Type-A | OC_3 | TAP2 |
| 9 | Type-A | OC_3 | TAP3 |
+-------------+----------------+------------+---------------------------------+
+---------------------+-------------------+------------+---------+
| PCH USB 3.1 Gen 2x1 | Connector Details | OC Mapping | Remarks |
+---------------------+-------------------+------------+---------+
| 1 | Type-A | OC_3 | TAP0 |
| 2 | Type-A | OC_3 | TAP1 |
+---------------------+-------------------+------------+---------+
+------+-------------------+------------+-----------------------------+
| TCPx | Connector Details | OC Mapping | Remarks |
+------+-------------------+------------+-----------------------------+
| 1 | Type C port 0 | OC_0 | To onboard Type-C connector |
| 2 | Type C port 1 | OC_0 | To onboard Type-C connector |
| 3 | Type C port 2 | OC_0 | To onboard Type-C connector |
+------+-------------------+------------+-----------------------------+
BUG=b:274421383
TEST=util/abuild/abuild -p none -t google/rex -x -a -b ovis
Change-Id: Icc81f12ec6cc4af37bcc1fcf3164cbfa5612a443
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75578
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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Enable ILI2901 and eKTH7B18 touchscreen for Google Screebo.
BUG=b:278167967
BRANCH=none
TEST=Build and boot to Google Screebo. Verify touchscreen works.
Change-Id: I57d55c5f2621d6fafd53b19d12ecad20271cdbb1
Signed-off-by: Zhongtian Wu <wuzhongtian@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75692
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Rui Zhou <zhourui@huaqin.corp-partner.google.com>
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BUG=b:274421383
TEST=util/abuild/abuild -p none -t google/rex -x -a -b ovis
Change-Id: I6f3fa6543a4cec8c2562196105f17fbc7831bab7
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75577
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
|
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BUG=b:274421383
TEST=util/abuild/abuild -p none -t google/rex -x -a -b ovis
Change-Id: I3795313e784595ac02ee2a38f466bcb9e613a6a4
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75576
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Jan Dabros <dabros@google.com>
|
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BUG=b:274421383
TEST=util/abuild/abuild -p none -t google/rex -x -a -b ovis
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Change-Id: I1644b1d8f49accbb2ea68e236534df80a5151360
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75503
Reviewed-by: Jan Dabros <dabros@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
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Based on Platform Mapping Document for Ovis (go/ovis_mapping_doc)
state for June 6, 2023 (Rev 0.3)
BUG=b:274421383
TEST=util/abuild/abuild -p none -t google/rex -x -a -b ovis
Change-Id: Iae3ca243a245928e8ec3d48877cf578843922fc7
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75502
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add new GFX devices for DDI and TCP with custom _PLD to describe the
corresponding ports.
BUG=b:277629750
TEST=emerge-rex coreboot
Signed-off-by: Won Chung <wonchung@google.com>
Change-Id: I193b95e8bd8ae538c4f25fbe772b174ef455d744
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74367
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
|
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BUG=b:274421383
TEST=util/abuild/abuild -p none -t google/rex -x -a -b ovis
Change-Id: Ic555fac846ebf1e9dad81b5847334c03d6804b5b
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75501
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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BUG=b:274421383
TEST=util/abuild/abuild -p none -t google/rex -x -a ; Make sure
GOOGLE_OVIS built successfully
Change-Id: I5c8f290cfdcb4d47c0e5e9d72c1e34073b957681
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75385
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Touchscreen may either use I2C1 or SPI0.
FW_CONFIG.TOUCHSCREEN is set to determine which is used.
This CL adds a probe to enable I2C1.
BUG=b:278783755
TEST=Tested on rex, confimed i2c1 is disabled when
TOUCHSCREEN != TOUCHSCREEN_I2C
Signed-off-by: Eran Mitrani <mitrani@google.com>
Change-Id: I0bee176298fddd2aee35cf084db037a3ce7672f7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75565
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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BUG=b:278783755
Signed-off-by: Eran Mitrani <mitrani@google.com>
Change-Id: I2a6de778c7ab30a9946e100cb70c092ba98496e3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74944
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Enable ISH based on FW_CONFIG obtained from EC CBI. This is useful in
case device is a tablet and motion sensors are handled by ISH instead
of EC.
BUG=b:280329972,b:283023296
TEST= Set bit 21 of FW_CONFIG with CBI
Boot rex board
Check that ISH is enabled and loaded
Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com>
Change-Id: Ibe0e1b8ce2c9b08ac6b1e6fef9bd19afc9b4f59f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75039
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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Fix for the "Onboard Keyboard and Type-C ports are not working after
resuming from powerd_dbus_suspend" issue. This issue was caused since
FSP 3165 FSP was fixed and started skipping GpioConfigureIoStandbyState
programming when GpioOverride UPD is enabled.
This patch moves the IO Standby State programming that FSP was doing to
coreboot.
BUG=b:284264580
TEST=Boot to OS, compare gpio pins, verify keyboard / Type-C
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: If96c1e71fdde784a55fe079875915ffa5a4f548a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75555
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add devicetree config for ALC1019_ALC5682I_I2S
BUG=b:278169268
TEST=emerge-rex coreboot and verified on screebo
Change-Id: I2814cc76aff43daf0353cfef41592591bbe3d213
Signed-off-by: Rui Zhou <zhourui@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75575
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Simon Zhou <zhouguohui@huaqin.corp-partner.google.com>
Reviewed-by: Mac Chiang <mac.chiang@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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Google/Rex is built with Intel Meteor Lake-U SoC, so select it.
Currently, there is no functional difference, but in the future FSP
UPD parameters can be overridden properly.
BUG=b:276697173
TEST=Able to build and boot google/rex.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I4c233e0a8ce58998dc1a0379662e386f9b3d0073
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75612
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Create the karis variant of the rex0 reference board by copying
the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.5.0.)
BUG=b:285195072
TEST=util/abuild/abuild -p none -t google/rex -x -a
make sure the build includes GOOGLE_KARIS
Change-Id: I16d8b43390401789b87a6233238e37f32a17b46b
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75551
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
|
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This patch adds FW_CONFIG to accommodate different Screebo BOM
components across various SKUs.
1. DB_CONFIG for DB_TPEC/DB_TBT/DB_UNKOWN
2. AUDIO for ALC1019_ALC5682I_I2S/AUDIO_UNKNOWN
BUG=b:278169268
TEST=build pass
Change-Id: I928aae61d4936509a7b68f4041c0cd72f298e83d
Signed-off-by: Simon Zhou <zhouguohui@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75573
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: YH Lin <yueherngl@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Mac Chiang <mac.chiang@intel.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
|
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Enabling MIPI UCAM for screebo project
BUG=b:277883010
TEST=none
Signed-off-by: jason.z.chen <jason.z.chen@intel.corp-partner.google.com>
Change-Id: Id06e5c162d911a4bd78190757c25e7f760160a8f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75157
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Haikun Zhou <zhouhaikun5@huaqin.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
|
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Set tcc_offset value to 20 in devicetree for Thermal Control Circuit
(TCC) activation feature for proto phase.
BUG=b:282865187
BRANCH=None
TEST=Build FW and test on Screebo board
Change-Id: I3a929aa20a700376d2a0a150911fed34e67f78eb
Signed-off-by: Wentao Qin <qinwentao@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75360
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Haikun Zhou <zhouhaikun5@huaqin.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Move I2S config from common to board.
BUG=none
TEST=Build google/rex
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: I51ca902e9b0077d5d5cc9c3507d26301a0f61bc2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75513
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Enable drivers for SoundWire codecs and define the topology in
the devicetree for the rex0 variant with the SoundWire daughter
board connected.
+------------------+ +--------------------+
| | | Headphone Codec |
| Intel Meteor Lake| +--->|Cirrus Logic CS42L42|
| SoundWire | | | ID 0 |
| Controller | | +--------------------+
| | |
| Link 0 +----+ +-------------------+
| | | Left Speaker Amp |
| Link 1 | +--->| Maxim MAX98363 |
| | | | ID 0 |
| Link 2 +----| +-------------------+
| | |
| Link 3 | | +-------------------+
| | | | Right Speaker Amp |
+------------------+ +--->| Maxim MAX98363 |
| ID 1 |
+-------------------+
This was tested by booting the firmware and dumping the SSDT table
to ensure that all SoundWire ACPI devices are created as expected with
the properties that are defined in coreboot under \_SB.PCI0:
HDAS - Intel Meteor Lake HDA PCI device
HDAS.SNDW - Intel Meteor Lake SoundWire Controller
HDAS.SNDW.SW00 - Cirrus Logic CS42L42 - Headphone Codec
HDAS.SNDW.SW20 - Maxim MAX98363 - Left Speaker Amp
HDAS.SNDW.SW21 - Maxim MAX98363 - Right Speaker Amp
BUG=b:269497731
TEST=Verified SSDT for SNDW in the OS. Playback and recording are also
validated on google/rex.
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: I3e11dc642ff686ba7da23ed76332f7f10e60fade
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73280
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
BUG=b:283477280
TEST=Able to build and boot google/rex as per Proto 2 schematics
dated 05/16.
+-----------------+------------------------------------+---------------------------+--------+
| GPIO | In Proto 1 | In Proto 2 | Impact |
+-----------------+------------------------------------+---------------------------+--------+
| GPP_C01 | SOC_TCHSCR_RST_L | SOC_TCHSCR_RST_R_L | N |
+-----------------+------------------------------------+---------------------------+--------+
| GPP_D19 | NC | EC_SOC_REC_SWITCH_ODL | Y |
+-----------------+------------------------------------+---------------------------+--------+
| GPP_E04 | HPS_INT_L | SOC_PEN_DETECT | N |
+-----------------+------------------------------------+---------------------------+--------+
| GPP_E17 | EN_HPS_PWR | EN_PP3300_SPARE_X | N |
+-----------------+------------------------------------+---------------------------+--------+
| GPP_F13 | GSPI1_SOC_MISO | GSPI1_SOC_MISO_R | N |
+-----------------+------------------------------------+---------------------------+--------+
| GPP_F21 | GPIO_F21_SPI_CS_L | SPI_SOC_CS_UWB_L_STRAP | N |
+-----------------+------------------------------------+---------------------------+--------+
| GPP_H00 | GPIO_H00_SPI_CLK_R | SPI_SOC_CLK_UWB_STRAP_R | N |
+-----------------+------------------------------------+---------------------------+--------+
| GPP_H01 | GPIO_H01_SPI_MOSI_R | SPI_SOC_DO_UWB_DI_STRAP_R | N |
+-----------------+------------------------------------+---------------------------+--------+
| GPP_H02 | GPIO_H02_SPI_MISO | SPI_SOC_DI_UWB_DO_STRAP | N |
+-----------------+------------------------------------+---------------------------+--------+
| GPP_S00 | UNNAMED_8_METEORLAKEU_I137_GPPS00 | SDW_HP_CLK_WLAN_PCM_CLK | N |
+-----------------+------------------------------------+---------------------------+--------+
| GPP_S01 | UNNAMED_8_METEORLAKEU_I137_GPPS01 | SDW_HP_DATA_WLAN_PCM_SYNC | N |
+-----------------+------------------------------------+---------------------------+--------+
| GPP_S02 | UNNAMED_8_METEORLAKEU_I137_GPPS02 | DMIC_SOC_CLK0_WLAN_PCM_OUT| N |
+-----------------+------------------------------------+---------------------------+--------+
| GPP_S03 | UNNAMED_8_METEORLAKEU_I137_GPPS03 | DMIC_SOC_DATA0_WLAN_PCM_IN| N |
+-----------------+------------------------------------+---------------------------+--------+
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I4a8c43b0f845d3446188b7c926e482f91e5b45aa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75407
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
|
|
This patch adds two new chromeos_*.fmd files for release and debug FSP
builds targeting rex_ec_ish.
`rex_ec_ish` variant would pack ISH firmware into the CSE boot partition
hence, the blob size is expected to increase. Creates separate flash map
layout to ensure ISH work is not impacting on the regular `rex0` project
SPI flash usage.
BUG=b:284254353
TEST=Able to build google/rex_ish_ec board and boot on target hardware.
Change-Id: Ife4663d3ccf80a928646eadaac4c9ab49ad29055
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75471
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: YH Lin <yueherngl@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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This patch creates a new variant to support the ISH enablement using
Rex platform.The idea here is to leverage the `rex0` code as much as
possible and add specific support for ISH enablement as per the hardware
schematic differences.
BUG=b:284254353
TEST=Able to build google/rex_ish_ec board and boot on target hardware.
Change-Id: I625fd0b31aed998f4e8f2d139827bc212ee8a90b
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75470
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: YH Lin <yueherngl@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
|
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Add support of variant_devtree_update() function to override
devtree settings for variant boards. Also, add CPU power limit
values for rex baseboard.
BRANCH=None
BUG=b:270664854
TEST=Built and verified power limit values as below log message
for 15W SKU on Rex board.
Overriding power limits PL1 (mW) (10000, 15000) PL2 (mW)
(57000, 57000) PL4 (W) (114)
Change-Id: If46445157358e3e0f227e26a35b4303fc9189a4b
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74754
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Harsha B R <harsha.b.r@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
|
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Restrict memory speed to 6400 MTS as per board design.
BUG=b:282164577
TEST=Verified the settings on google/rex using debug FSP logs.
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: I3dec383c7c585b80a73089f3403011c5cda61f65
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75291
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
|
|
Enable touchpad for Google Screebo.
BUG=b:278160238
BRANCH=none
TEST=Build and boot to Google Screebo. Verify touchpad works.
Change-Id: Ib83e5ef5ca497592f5a26aa1e85d793d06d9dd7f
Signed-off-by: Zhongtian Wu <wuzhongtian@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75412
Reviewed-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
|
|
This patch overrides `SaGv` FSP-M UPD to enable SaGv feature to be
able to train memory (DIMM) at different frequencies.
On all latest Intel based platforms SaGv is expected to be enabled
to support dynamic switching of memory operating frequency.
BUG=b:267879107
TEST=Able to verify SaGv is enabled with 3 work point (0, 1 and 2)
and MRC retraining takes around ~20ms extra compared to SaGv being
disabled.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ic680bfeab4dd285c0d3916ba5e917cc12bae3284
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73534
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
SKU1A C0 has no redriver, so enable SBU muxing in the SoC.
BUG=b:283044004
BRANCH=none
TEST=Voltages are correct on the C0 and C1 AUX bias pins
Change-Id: I18b4ade2c60c270855fb2e733a9201539e08d8ba
Signed-off-by: mike <mike5@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75381
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
|
|
Enabling BT for screebo project
BUG=b:278169273
TEST=Check whether BT can connect to Bluetooth device
Signed-off-by: qinwentao <qinwentao@huaqin.corp-partner.google.com>
Change-Id: I0ecd62abfbe751e1036948b1490844e7e63d7f0d
Signed-off-by: qinwentao <qinwentao@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75352
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
|
|
BUG=b:282912666
TEST=set and unset bit20 in HW_CONFIG and check if VPU(0b.0)
is enabled when bit20 is set, and disabled when cleared
Signed-off-by: Eran Mitrani <mitrani@google.com>
Change-Id: Iee6a9026a4d210407350bfb7ecc8a058e7ff5c24
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75303
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
|
|
TEST=set the corresponding cbi bit, and saw SPI0 under sysfs
BUG=b:278783755
Signed-off-by: Eran Mitrani <mitrani@google.com>
Change-Id: I7099cde14cff90ad63e9164769f9913a8284a805
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74888
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
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BUG=b:278156430
TEST=verify the fingerprint on screebo
Change-Id: I986e470b28145f7b17427e794055929a4283c721
Signed-off-by: Simon Zhou <zhouguohui@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75287
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dolan Liu <liuyong5@huaqin.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
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This patch enables stylus support by configuring the "GPP_D08" irqs for
rex SoC. This allows the SoC to detect a stylus device, when in use.
However stylus is not a wake up source for the rex.
BUG=b:282256460
Test=Stylus is detected on proto1 device.
Signed-off-by: Dinesh Gehlot <digehlot@google.com>
Change-Id: I84a71aa664698e105b738f8680d0a4751ca1fc72
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71820
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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This patch adds support for variant specific chip config update similar
to commit 061a93f93d2 ("mb/google/brya: Add variant specific soc chip config update").
Signed-off-by: Anil Kumar <anil.kumar.k@intel.com>
Change-Id: I60a4042cba608fd527527af9340ec0215f3086ca
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75046
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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add initial devicetree config for screebo
BUG=b:276814951
TEST=emerge-rex coreboot
Change-Id: Ie64d0e50ec22b3e363597af64eb723ef1f86dfa8
Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74972
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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BUG=b:278022971
TEST=verified on screebo
Change-Id: I16f1d66ca7f885120358eb2a2d3c6fb111319f11
Signed-off-by: Simon Zhou <zhouguohui@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75173
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This signal isn't functionally being used and is causing leakage
during suspend. Set it to NC.
BUG=b:279762779
TEST=builds. WWAN functional.
Change-Id: I93f2b0a781e250678280b57e4ab1d80ef27ff460
Signed-off-by: Tarun Tuli <taruntuli@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75053
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
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Denote the correct value of ACPI _PLD for USB ports.
The horizontal position of port C0 is incorrectly labelled.
+----------------+
| |
| Screen |
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+----------------+
C0 | | A0
| | C1
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+----------------+
BUG=b:216490477
TEST=emerg-rex coreboot
Signed-off-by: Won Chung <wonchung@google.com>
Change-Id: Id9ed435ca0af131e3bb4538701fc97d78146899f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74366
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add DDR DQ map config for screebo
BUG=b:276814951,b:272218757
TEST=emerge-rex coreboot
Change-Id: I993ae4024689b9cedbea247689a760bd83cd0d45
Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74961
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
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Generate RAM IDs for -
MT62F512M32D2DR-031 WT:B (LP5)
H9JCNNNBK3MLYR-N6E (LP5)
MT62F1G32D2DS-026 WT:B(LP5x)
H58G56BK7BX068 (LP5X)
BUG=b:276814951
TEST=Run part_id_gen tool without any errors
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: I0fb2e488c06ed74d3fd493e5ca0ab89a825a9349
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74802
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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add the initial gpio configuration for screebo initial variant
BUG=b:276814951
TEST=emerge-rex coreboot
Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Change-Id: Ib96e03f47bc1d6e5628ae459c3e1eb4dc18849c7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74475
Reviewed-by: YH Lin <yueherngl@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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