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path: root/src/mainboard/google/rex
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2023-08-24mb/google/rex/var/karis: Disable GSPI0Tyler Wang
According to the schematic, karis does not have a SPI touchscreen, remove related settings. BUG=b:294155897 TEST=emerge-rex coreboot Change-Id: I55eb9e3cebe426fcd023789831ce64a18d075d69 Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77347 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jakub Czapiga <jacz@semihalf.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-08-23mb/google/rex/var/karis: Remove WWAN temperature sensorTyler Wang
According to the schematic, karis does not have a WWAN temperature sensor, remove related settings. BUG=b:294155897 TEST=emerge-rex coreboot Change-Id: Ic82c6cfec067faa37d452bed5c4977402a2139a5 Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77284 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-08-21mb/google/rex/var/karis: Remove world facing cameraTyler Wang
According to the schematic, karis does not have a WFC. BUG=b:294155897 TEST=emerge-rex coreboot Change-Id: I9b4ecf2e96c77c131a60e48614d792370dd33423 Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77283 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Eran Mitrani <mitrani@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-08-20mb/google/rex: include Elan HID over SPI ASL for Rex4ESEran Mitrani
Existing code did not include the HID over SPI for rex4es. This CL corrects this issue. BUG=None TEST=Tested on Rex Signed-off-by: Eran Mitrani <mitrani@google.com> Change-Id: I02f7c4b68cfee2ebb202581c9f031af99ab4b6f9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/77245 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-18mb/google/rex: Dump ISH version for `rex_ec_ish` variantSubrata Banik
This patch selects `SOC_INTEL_STORE_ISH_FW_VERSION` config to dump the ISH version as part of the .final hook. BUG=b:285405031 TEST=Able to build and boot google/rex_ec_ish. Verify the ISH version is same as MFIT ISH version section. > cbmem -c | grep "ISH" [DEBUG]  ISH version: 5.6.0.28821 Change-Id: I052af85ad836ab81ff6c510bb74e042b11940a65 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77178 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-18mb/google/rex/var/screebo: Update DTT settings for thermal controlKun Liu
update DTT settings for thermal control BUG=b:291217859 TEST=emerge-rex coreboot Change-Id: I6e6ad653157dc87a7d87b5ffc4f9590991a7c284 Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76678 Reviewed-by: Simon Zhou <zhouguohui@huaqin.corp-partner.google.com> Reviewed-by: Martin L Roth <gaumless@gmail.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-17mb/google/rex: Update ISH GPIO's configurationBernardo Perez Priego
Configures ISH related GPIO's based on FW_CONFIG obtained from CBI. BUG=b:280329972,b:283023296 TEST= Set bit 21 of FW_CONFIG with CBI Boot rex board Check that ISH is enabled, loaded, and functional Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com> Change-Id: I778251aadef4499427fc9855adfdd9cade3a3e70 Reviewed-on: https://review.coreboot.org/c/coreboot/+/77235 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-17mb/google/rex/var/karis: Update USB settingsTyler Wang
BUG=b:294155897 TEST=emerge-rex coreboot Change-Id: Ia4bd6fe02ffa62ed8aeffb188de5c4c4b64900ff Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77106 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-08-17mb/google/rex/var/karis: Remove SD card and ISHTyler Wang
BUG=b:294155897 TEST=emerge-rex coreboot Change-Id: I1575ee1d7e4c834ad15f60a3b7d63c041a8d4890 Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77007 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-17mb/google/rex/var/karis: Modify SSD settingsTyler Wang
Follow schematic, modify SSD related settings. BUG=b:294155897, b:289880020 TEST=emerge-rex coreboot Change-Id: Ie9c228ed7ccc83afaa8365f89c1d5cdedc4f0c8c Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77006 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-17mb/google/rex/var/karis: Copy devicetree from rex0Tyler Wang
Add initial devicetree config for karis. It's copied from rex0 and only for initial settings, will update more settings afterward. BUG=b:294155897 TEST=emerge-rex coreboot Change-Id: I89585a86e8afe636d3927a21a64451b59591acda Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77203 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-08-17mb/google/rex/var/karis: Copy Kconfig from rex0Tyler Wang
Add initial Kconfig settings for karis. Copied from rex for support audio codec, SD card and ISH. It's only for initial settings, will update more settings afterward. BUG=b:294155897 TEST=emerge-rex coreboot Change-Id: I4bcea7f5e678f2862b3477206838786ff5bad173 Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77182 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-17mb/google/rex/var/karis: Add TPM supportTyler Wang
BUG=b:294155897 TEST=emerge-rex coreboot Change-Id: I4076ee4a16b7260db464760d5a19e1144081bab8 Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77181 Reviewed-by: Eran Mitrani <mitrani@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-17mb/google/rex/var/karis: Copy GPIO from rex0Tyler Wang
Add initial GPIO settings for karis. It's copied from rex0 and only for initial settings, will update more settings afterward. BUG=b:294155897 TEST=emerge-rex coreboot Change-Id: Ic1e52a1eaca0aa5f68661826a70ccb89d6e302dc Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77003 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-17mb/google/rex/var/ovis: Fix Bluetooth configurationJakub Czapiga
Bluetooth was missing USB configuration, so add it according to the schematics. BUG=b:290111789 TEST=Boot on Ovis and list bluetooth with `hciconfig` Change-Id: Iee8a3368bbad6c5b49f09ec7335d77ed63ecc784 Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77146 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-10mb/google/rex: Create karis4es variantEran Mitrani
This patch creates a new variant karis4es. The new variant will support only ESx samples. The existing karis variant will support the QS samples. BUG=b:293326312 TEST=Image built properly Change-Id: I854fee7206528a235f027ff8ec98593a02be4806 Signed-off-by: Eran Mitrani <mitrani@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76761 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-by: YH Lin <yueherngl@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2023-08-08mb/google/rex/variants/ovis: Use correct device_index for RT8168Stefan Reinauer
Fix ethernet MAC address configuration. Currently, coreboot would use ethernet_mac0 for both ports when setting the system's MAC address. Instead, set the right device_index for the second controller to pick up ethernet_mac1. BUG=b:294856127 TEST=boot device and observe two different MAC addresses on the ethernet ports. Change-Id: I5ff6d62d2f837a120f7095f9b9aed487e6c5aee4 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77044 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Jakub Czapiga <jacz@semihalf.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-08mb/google/rex/var/screebo: Change sdcard clk from 7 to 6Kun Liu
Update firmware to reflect schematics change for SD Card CLKSRC from 7 to 6 for EVT board revision BUG=b:291051683 TEST=emerge-rex coreboot Change-Id: I3347f739650458c833d5a825742cf1d663853cc5 Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77023 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Rui Zhou <zhourui@huaqin.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-06mainboard: Add SPDX license headers to MakefilesMartin Roth
To help identify the licenses of the various files contained in the coreboot source, we've added SPDX headers to the top of all of the .c and .h files. This extends that practice to Makefiles. Any file in the coreboot project without a specific license is bound to the license of the overall coreboot project, GPL Version 2. This patch adds the GPL V2 license identifier to the top of all makefiles in the mainboard directory that don't already have an SPDX license line at the top. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Ic451e68b1ad9ccdf34484dd98bd7fca7e177ef22 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68982 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Tim Crawford <tcrawford@system76.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-08-05mb/google/rex: enable d3hot for storage devicesSukumar Ghorai
_DSD "StorageD3Enable" property is needs to be set under the root port in the DSDT or SSDT. The ACPI _DSD method is the preferred way to opt D3hot support for storage devices. This also bypasses the low LTR from SSD that blocking S0i2.2 LTR/latency SoC requirement. Name (_DSD, Package () { ToUUID("5025030F-842F-4AB4-A561-99A5189762D0"), Package () { Package (2) {"StorageD3Enable", 1}, // 1 - Enable; 0 - Disable } } ) BUG=b:289028958 TEST=Check code compiles & boot rex, and verify the "StorageD3Enable" SSDT entry. Change-Id: I19decc2706954e73bc28fc2d9c3c4d18d2c384b7 Signed-off-by: Kangheui Won <khwon@chromium.org> Signed-off-by: Sukumar Ghorai <sukumar.ghorai@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76835 Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-04mb/google/{rex,ovis}: Disable C1-state auto demotion for rex & ovisSukumar Ghorai
C1-state auto demotion feature allows hardware to determine C1-state as per platform policy. Since platform sets performance policy to balanced from hardware, auto demotion can be disabled without performance impact. Also, disabling this feature results soc to enter PC2 and lower state in camera preview case and save platform power. Note: C1 demotion heuristics used EPB parameter to balance between power and performance, i.e. low threshold when EPB is low in-order to get C1 demotion faster and vice-versa. ChromeOS operates at default EPB=0x7 (low EPB) in both AC/DC, so in DC mode it gets more C1 demotion hits than expected (similar to AC mode) and losing power respectively. BUG=b:286328295 TEST=Code compiles and correct value of c1-state auto demotion is passed to FSP. Also verified PC residency improvement ~10% in camera preview case. Change-Id: I548e0e5340dec537d05718dd2f4652e10fb36ac0 Signed-off-by: Sukumar Ghorai <sukumar.ghorai@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76827 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-08-04mb/google/rex/var/screebo: Add fw_config probe for GL9750 and RTS5227SKun Liu
Add support for SD card reader GL9750 and RTS5227S BUG=b:284273384 TEST=emerge-rex coreboot Change-Id: I98aa0d3e52c355f6c1528c912a6fa0f32652dda8 Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76912 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Rui Zhou <zhourui@huaqin.corp-partner.google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-08-03mb/google: Add more comment on GFX devices for the future referenceWon Chung
Add more details to instruct future boards/models implementers regarding how GFX devices should be added. If HDMI and DP connectors are enumerated by the kernel in /sys/class/drm/ then corresponding GFX device should be added to ACPI. It is possible that some connectors do not have dedicated ports, but still enumerated. The order of GFX devices is DDIA -> DDIB -> TCPX. BUG=b:277629750 TEST=emerge-brya coreboot Change-Id: I59e82ee954a7d502e419046c1c2d7a20ea8a9224 Signed-off-by: Won Chung <wonchung@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76776 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
2023-08-02mb/google/rex/variants/ovis: Use and configure RT8168 driverStefan Reinauer
This makes sure google/ovis don't get a random mac address on boot. Additionally, program the LAN WAKE GPIO properly as per the Ovis schematics dated July'23. BUG=b:293905992 TEST=Verified on google/ovis that able to get the fixed MAC address across the power cycles. Change-Id: I699e52e25f851de325f96ef885e04d15ca64badd Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76872 Reviewed-by: Jakub Czapiga <jacz@semihalf.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-08-01mb/google/rex/var/screebo: Enable RTD3 for SSDKapil Porwal
Currently, S0iX test is failing because S0i2 susbstate is blocked. Enable RTD3 for SSD to unblock S0i2.2 substate residency. BUG=none TEST=Screebo can enter into S0iX. S0iX substate residency w/o this CL - ``` Substate Residency S0i2.0 0 S0i2.1 38451594 S0i2.2 0 ``` S0iX substate residency w/ this CL - ``` Substate Residency S0i2.0 0 S0i2.1 12108 S0i2.2 33878424 ``` Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: I50ac730820b3f29c387dc73bd90f1392a8797e24 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76831 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-08-01mb/google/rex/var/screebo: Restrict ASPM to L1 for SD controllerKapil Porwal
Restrict ASPM to L1 for SD controller to avoid AERs. BUG=b:288830220 TEST=No PCIE AER on SD controller on Screebo. w/o this CL - ``` ~ # lspci -s 00:06.0 -vvv | grep -i aspm LnkCap: Port #9, Speed 16GT/s, Width x4, ASPM L0s L1, Exit Latency L0s <4us, L1 <64us ClockPM- Surprise- LLActRep+ BwNot+ ASPMOptComp+ LnkCtl: ASPM L1 Enabled; RCB 64 bytes, Disabled- CommClk+ L1SubCap: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2+ ASPM_L1.1+ L1_PM_Substates+ L1SubCtl1: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2+ ASPM_L1.1+ ~ # lspci -s 02:00.0 -vvv | grep -i aspm LnkCap: Port #0, Speed 2.5GT/s, Width x1, ASPM L0s L1, Exit Latency L0s unlimited, L1 <64us ClockPM+ Surprise- LLActRep- BwNot- ASPMOptComp+ LnkCtl: ASPM L0s L1 Enabled; RCB 64 bytes, Disabled- CommClk+ L1SubCap: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2+ ASPM_L1.1+ L1_PM_Substates+ L1SubCtl1: PCI-PM_L1.2- PCI-PM_L1.1- ASPM_L1.2- ASPM_L1.1- ~ # dmesg | grep -i -e "pci.*error" [ 0.734597] pcieport 0000:00:06.1: AER: Corrected error received: 0000:02:00.0 [ 0.734882] rtsx_pci 0000:02:00.0: PCIe Bus Error: severity=Corrected, type=Data Link Layer, (Transmitter ID) [ 0.735258] rtsx_pci 0000:02:00.0: device [10ec:522a] error status/mask=00001000/00006000 [ 0.736159] pcieport 0000:00:06.1: AER: Corrected error received: 0000:02:00.0 [ 1.520903] pcieport 0000:00:06.1: AER: Corrected error received: 0000:02:00.0 [ 1.531587] rtsx_pci 0000:02:00.0: PCIe Bus Error: severity=Corrected, type=Data Link Layer, (Transmitter ID) [ 1.548894] rtsx_pci 0000:02:00.0: device [10ec:522a] error status/mask=00001000/00006000 [ 1.567490] pcieport 0000:00:06.1: AER: Multiple Corrected error received: 0000:02:00.0 ``` w/ this CL - ``` ~ # lspci -s 00:06.0 -vvv | grep -i aspm LnkCap: Port #9, Speed 16GT/s, Width x4, ASPM L0s L1, Exit Latency L0s <4us, L1 <64us ClockPM- Surprise- LLActRep+ BwNot+ ASPMOptComp+ LnkCtl: ASPM L1 Enabled; RCB 64 bytes, Disabled- CommClk+ L1SubCap: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2+ ASPM_L1.1+ L1_PM_Substates+ L1SubCtl1: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2+ ASPM_L1.1+ ~ # lspci -s 02:00.0 -vvv | grep -i aspm LnkCap: Port #0, Speed 2.5GT/s, Width x1, ASPM L0s L1, Exit Latency L0s unlimited, L1 <64us ClockPM+ Surprise- LLActRep- BwNot- ASPMOptComp+ LnkCtl: ASPM L1 Enabled; RCB 64 bytes, Disabled- CommClk+ L1SubCap: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2+ ASPM_L1.1+ L1_PM_Substates+ L1SubCtl1: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2+ ASPM_L1.1+ ~ # dmesg | grep -i -e "pci.*error" ``` Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: I05f02c46486be42286fe9bc4f4be17763bb12b79 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76829 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Jakub Czapiga <jacz@semihalf.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-31mb/google/rex: Allow to show early splash screen using GFX PEIMSubrata Banik
This patch chooses to show the early splash screen which is an OEM feature. The current implementation is relying on the Intel FSP GFX PEIM to perform the display initialization. Having this feature allows the platform to show the user notification with 500ms since boot compared to traditional scenarios where first user notification is coming from kernel (typically ~3sec+ after cpu reset). Eventually this feature will help to improve the user experience while booting Intel SoC platform based chromeos devices. BUG=b:284799726 TEST=Able to see the early splash screen on google/rex. Change-Id: I399ddb6618e774302200e8a87629647ba070d080 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76361 Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-31mb/google/rex: Create Ovis4ES variantJakub Czapiga
Ovis4ES variant supports only ESx SoCs. Existing Ovis variant will support QS SoCs. BUG=b:293409364 TEST=util/abuild/abuild -p none -t google/rex -b ovis4es -x -a TEST=util/abuild/abuild -p none -t google/rex -b ovis -x -a Change-Id: Iacf5ef6d3dfee8838fe13e68b254a84e4a6cf200 Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76789 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-31mb/google/rex/var/ovis: Simplify the USB-C port mappingSubrata Banik
This patch changes the `EC CONx Mapping` to fix the hot-plug issue where attaching a device to USB-C port C1 can affect the USB-C display over port C2. Note: `PMC MUX Mapping` remains unchanged to reflect the underlying board design where the physical MUX has swapped between C1 and C2 USB-C port. Before: | PMC MUX Mapping | Port C0 | Port C1 | Port C2 | +------------------+-------------+-------------+---------------+ | USB2-Port | 2 | 3 | 1 | | USB3-Port | 0 | 2 | 1 | | EC CONx Mapping | Port C0 | Port C1 | Port C2 | +------------------+-------------+-------------+---------------+ | USB2-Port | 2 | 3 | 1 | | USB3-Port | 0 | 2 | 1 | Physical Mapping between EC and SoC as below: Port C0 - EC CON0 ----> PMC MUX CON0 Port C1 - EC CON1 ----> PMC MUX CON2 Port C2 - EC CON2 ----> PMC MUX CON1 After: | PMC MUX Mapping | Port C0 | Port C1 | Port C2 | +------------------+-------------+-------------+---------------+ | USB2-Port | 2 | 3 | 1 | | USB3-Port | 0 | 2 | 1 | | EC CONx Mapping | Port C0 | Port C1 | Port C2 | +------------------+-------------+-------------+---------------+ | USB2-Port | 2 | 1 | 3 | | USB3-Port | 0 | 1 | 2 | Physical Mapping between EC and SoC as below: Port C0 - EC CON0 ----> PMC MUX CON0 Port C1 - EC CON1 ----> PMC MUX CON1 Port C2 - EC CON2 ----> PMC MUX CON2 Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I59e2630bc0f93321cc4b734fcf3c4cf254882477 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76758 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2023-07-25mb/google/rex: Create screebo4es variantSubrata Banik
This patch creates a new variant screebo4es. The new variant will support only ESx samples. The existing rex variant will support the QS samples. BUG=b:292280656 TEST=Able to build google/screebo4es board and boot on target hardware. Change-Id: If77b4a773bee3633008d39c1886b61869c9618de Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76668 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-07-25mb/google/rex: Use specific mainboard part name for each rex variantsSubrata Banik
BUG=b:290894460 TEST=`emerge-rex coreboot chromeos-bootimage` then check variant name with image*.bin. Signed-off-by: YH Lin <yueherngl@google.com> Change-Id: I8f739485dbaab074f57eaa4dacc9f228a3f4aa14 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76667 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-22mb/google/rex/var/screebo: Reduce TCC from 90°C to 80°CSubrata Banik
This patch increases the `tcc_offset` to reduce the TCC (Thermal Control Circuit) activation temperature to avoid running into abrupt power off during power cycle tests. On Intel processors, the core frequency can be by an HW agent when the current temperature reaches the TCC activation temperature. The default TCC activation temperature is specified by MSR_IA32_TEMPERATURE_TARGET (which is 90°C for google/rex variants). However, this patch adjusted the TCC by specifying an offset in degrees C (i.e., using `tcc_offset` from variant override device tree). Note: The bigger the TCC offset is, the lower the effective TCC activation temperature would be, to ensure that processors can be throttled earlier before the system critical overheats. BUG=b:283008762 TEST=Able to perform power cycle on google/screebo w/o any crash/shutdown. Change-Id: Ib19703877dbbfc26b2d9f538dda4f10c27cf872d Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76658 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-07-21mb/google/rex: Use BOARD_GOOGLE_MODEL_REX instead variant nameSubrata Banik
Choose BOARD_GOOGLE_MODEL_REX while setting up the default config value for variants created using google/rex model. TEST=Able to build and boot google/rex. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I107f4e375b5c9e9c0fb80c4d396164c10c1fc1e7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76657 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-07-21mb/google/rex: Create rex4es variantDinesh Gehlot
This patch creates a new variant rex4es. The new variant will support ESx samples. The existing rex variant will support the QS samples. BUG=b:290732344 TEST=Able to build google/rex4es board and boot on target hardware. Change-Id: I25dd1f42ee812f47289da0c2ef7aa79d6f340d48 Signed-off-by: Dinesh Gehlot <digehlot@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76605 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-07-21mb/google/rex: Create a `rex` model for easier variant integrationSubrata Banik
This patch creates  a rex model so that other variants developed using `rex` baseboard are easy to land without duplicating the config selection. So far, `rex0` and `rex_ec_ish` are developed using the `rex` model. The plan is to extend the support for `rex4es` and `rex4es_ec_ish` variants. TEST=Able to build and boot google/rex. Change-Id: Id4e8d1162da93b7266ee1108f870e89b6d884ab9 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76608 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Jakub Czapiga <jacz@semihalf.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-07-20mb/google/rex/var/screebo: Change GPIO of WIFI moduleWentao Qin
Follow baseboard Rex to make GPIO changes BUG=b:286187821 TEST=Ability to enable and disable WIFI function in OS. Change-Id: I805ce859c42c7c0a9d117418a80555658f844e09 Signed-off-by: Wentao Qin <qinwentao@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76551 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kun Liu <liukun11@huaqin.corp-partner.google.com> Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
2023-07-19mb/google/rex/var/ovis: Update the Type-C USB2/3 port mappingSubrata Banik
This patch updates the Type-C USB2/3 port mapping to reflect the mux connection change as mentioned in previous patch commit ee3f796200bf3baf8a1906 (mb/google/rex/var/ovis: Fix mux change as per schematics). Here is the correct port mapping after considering the mux swap: +--------------------------------+-------------+---------------+ | TCSS-USB Mapping | Port C0 | Port C1 | Port C2 | +------------------+-------------+-------------+---------------+ | USB2-Port | 2 | 3 | 1 | | USB3-Port | 0 | 2 | 1 | +------------------+-------------+-------------+---------------+ BUG=b:289300284 TEST=Able to build and boot google/ovis to get display over Type-C1 and Type-C2 port. Change-Id: I460004842dd8fcdc03fca6639d03e422259380ca Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76464 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-19mb/google/rex/var/screebo: Change SD_CLKREQ_ODL from GPP_D19 to GPP_D18Kun Liu
Change SD_CLKREQ_ODL from GPP_D19 to GPP_D18 BUG=b:291051683 BRANCH=none TEST=emerge-rex coreboot Change-Id: Ic102e42482328580c5334e6ff036b774f5002e00 Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76565 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Simon Zhou <zhouguohui@huaqin.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-07-17mb/google/rex/var/screebo: Update I2C timingZhongtian Wu
Change i2c[0] parameter Thd:dat = 50ns; Change i2c[1] parameter Thd:dat = 100ns; BUG=b:287898252 BRANCH=none TEST=Test success by EE. Change-Id: Ibdbe4e17cf21c914b48fa6dc7d3eecf8218a2d8b Signed-off-by: Zhongtian Wu <wuzhongtian@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76430 Reviewed-by: Kun Liu <liukun11@huaqin.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-17mb/google/rex: Disable early EC syncSubrata Banik
This patch disables early EC sync to avoid an idle delay (~3sec) without a provision to notify the user about some critical task in progress. Doing EC sync at later stage allows us to notify using graphical msg on screen to make user aware of the WIP task. BUG=b:279944831 TEST=Able to perform EC sync from depthcharge on google/rex. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I03ed40827c50e75ceaaf94e30d675014ebf22dac Reviewed-on: https://review.coreboot.org/c/coreboot/+/74837 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2023-07-17mb/google/rex/var/screebo: Update touchscreen GPIOZhongtian Wu
Change touchscreen reset_gpio GPP_C01 -> GPP_D07; Change touchscreen enable_gpio GPP_C00 -> GPP_B17. BUG=b:289425753 BRANCH=none TEST=Test success by EE. Change-Id: I7be6a2b4e87126b281f138c819d2a0a5b1af5821 Signed-off-by: Zhongtian Wu <wuzhongtian@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76429 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kun Liu <liukun11@huaqin.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-07-17mb/google/rex/var/karis: Generate SPD ID for supported memory partTyler Wang
Add karis supported memory parts in mem_parts_used.txt, generate SPD id. 1. MICRON MT62F1G32D2DS-023 WT:B 2. HYNIX H9JCNNNBK3MLYR-N6E 3. HYNIX H58G56BK8BX068 4. SAMSUNG K3KL8L80CM-MGCT BUG=b:291018417 TEST=Use part_id_gen to generate related settings Change-Id: I87c2c4f59454dec84d29590ee91379c9fa60ddcf Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76443 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-13mb/google/rex/var/screebo: Configure CNVi GPIO IO Standby StateWentao Qin
This configures GPIO IO Standby State of GPP_F00 - GPP_F05 as masked for CNVi. Meteor Lake rex platform does not wake up from low power state by bluetooth keyboard and mouse properly. It is identified that IO Standby State needs to be configured as masked to function properly for CNVi. BUG=b:286803481 TEST=Make screebo suspend to s0ix state and press a key from bluetooth keyboard. Check the platform wakes up properly from s0ix. Change-Id: I7fd342e52fa0f9126eab4c857a5adc04c26e49c6 Signed-off-by: Wentao Qin <qinwentao@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76406 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kun Liu <liukun11@huaqin.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-12mb/{google, intel}: Enable PCH Energy Reporting for MTL platformsSukumar Ghorai
This patch enables PCH to CPU energy report feature which can be used by Intel Telemetry Driver. BUG=b:269563588 TEST=Able to build and boot google/rex and perform below check to ensure the energy reporting is correct w/o this cl: # lspci -s 00:14.2 -vvv | grep "Region 0" Region 0: Memory at 957f8000 (64-bit, non-prefetchable) [size=16K] # iotools mmio_read32 0x957f8068 #i.e., 104th offset 0xXXXX0000 w/ this cl: #lspci -s 00:14.2 -vvv | grep "Region 0" Region 0: Memory at 957f8000 (64-bit, non-prefetchable) [size=16K] # iotools mmio_read32 0x957f8068 #i.e., 104th offset 0xXXXXfc004 Change-Id: I9bd4625ea311a05071878aaec68433a1ba018c0d Signed-off-by: Sukumar Ghorai <sukumar.ghorai@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76353 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
2023-07-12mb/google/rex: Disable DRIVERS_INTEL_DPTF_SUPPORTS_TPCHKane Chen
There is no PCH FIVR participant on MTL and we should remove it in Rex. TEST=compile ok and make sure there no TPCH device in acpi BUG=b:290322310 Change-Id: Icf4be86da3f3cb9b1f0a3f2586b029a533c3e6a9 Signed-off-by: Kane Chen <kane.chen@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76402 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-11mb/google/rex: LZ4 compress ramstage instead of LZMAWonkyu Kim
for saving boot time, change ramstage compression from LZMA to LZ4. Boot time saving is around 35ms (30-37ms) while SPI size impact is 230KB. For detail, refer below. Existing: LZMA(55.6 ms) 8:starting to load ramstage 894,519 (0) 15:starting LZMA decompress (ignore for x86) 903,556 (9,036) 16:finished LZMA decompress (ignore for x86) 949,997 (46,441) 9:finished loading ramstage 950,179 (182) Changed: LZ4(17.8ms) 8:starting to load ramstage 900,876 (0) 17:starting LZ4 decompress (ignore for x86) 917,650 (16,774) 18:finished LZ4 decompress (ignore for x86) 918,690 (1,040) 9:finished loading ramstage 918,849 (158) Size impact (73KB * 3 = 219KB) fallback/ramstage 0x62940 stage 240281 LZ4 (405524 decompressed) fallback/ramstage 0x62940 stage 165452 LZMA (405524 decompressed) BUG=b:286930648 TEST= Boot to OS and check boot time Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Change-Id: I6610f405d287bff2eb4eee6f09026e3361405ded Reviewed-on: https://review.coreboot.org/c/coreboot/+/75769 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-07-11mb/google/rex/var/ovis: Configure CNVi GPIO IO Standby StateJamie Ryu
This configures GPIO IO Standby State of GPP_F00 - GPP_F05 as masked for CNVi to function properly with the connected bluetooth devices and wake up from low power state. BUG=None TEST=None Change-Id: I977493fd95a99381279f5a3f5e679e4893369b8a Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76362 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com>
2023-07-11mb/google/rex/var/rex0: Configure CNVi GPIO IO Standby StateJamie Ryu
This configures GPIO IO Standby State of GPP_F00 - GPP_F05 as masked for CNVi. Meteor Lake rex platform does not wake up from low power state by bluetooth keyboard and mouse properly. It is identified that IO Standby State needs to be configured as masked to function properly for CNVi. BUG=None TEST=Make rex platform suspend to s0ix state and press a key from bluetooth keyboard. Check the platform wakes up properly from s0ix. Change-Id: Ia98abde584699fa01acba47a9df4ef6332ac16fd Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76338 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-11mb/google/rex/var/rex0: Reduce camera NVM size to 8KBJamie Ryu
The actual NVM size of camera module is 64KB; however, only 8KB is in use to store data. This reduces the size of both NVM0 and NVM1 to 8KB to minimize the time taken to read NVM and launch Camera preview. BUG=NONE TEST=Launch Chrome camera application and check the time taken to read eeprom from camera service log and show camera preview. It takes 2 to 3 seconds to show camera preview while it takes 4 to 5 seconds without the changes. Before the changes: 06:21:04.204944Z OpenDevice(): camera_id = 1 06:21:07.297584Z Read camera eeprom from eeprom 06:21:08.763491Z Read camera eeprom from nvmem After the changes: 21:37:23.923676Z OpenDevice(): camera_id = 1 21:37:24.386020Z Read camera eeprom from eeprom 21:37:24.574515Z Read camera eeprom from nvmem Change-Id: I0e2272b3307fea60ea7406fc6899ae2cb0134fa3 Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76189 Reviewed-by: Kiran2 Kumar <kiran2.kumar@intel.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-07-10mb/google/rex/var/ovis: Enable both Memory Channels (MC0 and MC1)Subrata Banik
This patch skips reading the MEM_CH_SEL GPIO aka GPP_E13 to determine the memory channel configuration. The signal behavior is not proper, hence limiting the DIMM capacity to half (only MC0 is enabled). This patch always reports the full memory capacity as in dual channel (both MC0 and MC1 enabled). This change is necessary to ensure that the system reports the correct memory capacity, even if the MEM_CH_SEL GPIO is not working properly. BUG=b:290174538 TEST=Able to detect 32GB memory capacity while booting google/ovis. Without this patch: localhost ~ # cat /proc/meminfo MemTotal: 16183080 kB With this patch: localhost ~ # cat /proc/meminfo   MemTotal: 32673664 kB Change-Id: I6c3fa941abb044b79b13785f7b65d09957f0487d Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76359 Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-07-10mb/google/rex/var/rex0: Change touch over spi interrupt trigger to edgeEran Mitrani
This CL corrects the trigger for HID over SPI from Level to Edge. BUG:None TEST:Tested with I2C and SPI Change-Id: I78937af22df22d80a702477b6790a7aa40d782a4 Signed-off-by: Eran Mitrani <mitrani@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76116 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-07-05soc/intel/meteorlake: Set TCC to 90°CSumeet Pawnikar
Set tcc_offset value to 20 in chipset for Thermal Control Circuit (TCC) activation feature for meteorlake silicon. Also, remove tcc_offset default value from rex baseboard and variants. BUG=b:270664854 BRANCH=None TEST=Build FW and test on rex board Change-Id: Ieec1b7e0873eef46a56e612ed1d9445019b1f4a9 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76232 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-07-05mb/google/rex/var/screebo: Update touchpad I2C timingZhongtian Wu
Change i2c[3] parameter to meet below timing: t-HIGH > 600ns; 900ns > Thd:dat > 300ns. BUG=b:286030723 BRANCH=none TEST=Test success by EE. Change-Id: I4b2d958a5a0d41e2cfa1087f5cb94cc83bbb1739 Signed-off-by: Zhongtian Wu <wuzhongtian@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76169 Reviewed-by: Kun Liu <liukun11@huaqin.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-05mb/google/rex/var/ovis: Set TCC to 100°CSubrata Banik
Set tcc_offset value to 10 in devicetree for Thermal Control Circuit (TCC) activation feature for ovis. BUG=b:270664854 TEST=Build and boot google/ovis. Change-Id: I0ef626f6cc460f1b460297804b97038705efaf4c Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76230 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-07-05mb/google/rex/var/ovis: Add Power Limit for 28WSubrata Banik
This patch adds a power limit for Ovis with 28W Intel Meteor Lake silicon. Reference: Intel MTL-UH_Power_Map_Rev1p2, doc: 640982 BUG=b:289854108 TEST=Able to boot google/ovis with power limit being overridden as appropriate to 28W. Change-Id: I312c70720fd89261c53d5bd4f45236e829d6c790 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76229 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2023-07-05mb/google/rex: Temporarily disable the crashlogKapil Porwal
Currently, boards with ES2 silicon are unable to boot with crashlog enabled because crashlog driver is unable to handle invalid data. Temporarily disable the crashlog to unblock development until the issue is fixed. BUG=b:289749310 TEST=Able to boot to the OS on Screebo Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: Ic63cf9cf5bfa2c92d8f2c5b13df2f23dc118b389 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76231 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
2023-07-05mb/google/rex/var/screebo: Update touchscreen I2C timingZhongtian Wu
Change i2c[0] parameter to meet touchscreen timing. Thd:dat > 100ns. BUG=b:287898252 BRANCH=none TEST=Test success by EE. Change-Id: I30e7c87d788f7f144276c45e8475af65f1f132ae Signed-off-by: Zhongtian Wu <wuzhongtian@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76190 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Kun Liu <liukun11@huaqin.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-07-04mb/google/rex: Enable Bluetooth offload for soundwire audioUday M Bhat
This patch enables BT offload feature for soundwire audio over SSP1. BT mode is selected via FW_CONFIG and corresponding VGPIOs are programmed. BUG=b:275538390 TEST=build and verify BT offload on rex soundwire audio Change-Id: I99df78787d9f54c91bcedf6f70352890a715cdb3 Signed-off-by: Uday M Bhat <uday.m.bhat@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75924 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-07-03mb/google/rex: Set AUX orientation at SoC to follow cable for kb8010Caveh Jalali
This configures the SoC to flip the orientation of the AUX pins to follow the orientation of the cable when using the kb8010 retimer. This is necessary when there is no external retimer/mux or the retimer/mux does not implement the flip. The kb8010 retimer does not support this feature, so let the SoC do the flip. BUG=b:267589112 TEST=verified DP-ALT mode works in both cable orientations on rex with reworked kb8010 DB by flykt@ Change-Id: Iad093e27617b80f8301008deb00b57fb9b3a48ba Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76137 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-07-02mb/google/rex/var/ovis: Enable LAN0Subrata Banik
This patch performs below operations to enable LAN0. - Complete the LAN PEREST power sequencing - Program the SRC_CLKREQ (GPP_D20) with correctly. - Add overridetree.cb entry to configure the LAN0 device. BUG=b:289395519 TEST=Able to boot google/ovis with LAN0 being enabled. Change-Id: I91b0a76395ade4459cf8705c333728a71f95df14 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76213 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-02mb/google/rex/var/ovis: Enable LAN1Subrata Banik
This patch performs below operations to enable LAN1. - Add overridetree.cb entry to configure the LAN device. - Complete the LAN1/SD PEREST power sequencing BUG=b:289395519 TEST=Able to boot google/ovis with LAN1 being enabled. Change-Id: Ifb67cb8e6fc03e3ff14b1b3d8382322fd0b3aeff Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76212 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-02mb/google/rex/var/ovis: Configure GPP_V12 PADSubrata Banik
This patch configures GPP_V12 aka SOC_SLP_LAN_L properly as per the Ovis schematics dated June'23 to ensure LAN port is not in sleep. BUG=b:289395519 TEST=Able to measure SLP_LAN PIN and confirm it's deasserted. Change-Id: I1fe8715862823149c8a1f05e3e4463a615fbbbce Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76211 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-02mb/google/rex/var/ovis: Configure GPP_C10 PADSubrata Banik
This patch configures GPP_C10 aka EN_LAN_RAILS properly as per the Ovis schematics dated June'23 to ensure LAN ports having power. BUG=b:289395519 TEST=Able to measure LAN port power is enabled with this CL. Change-Id: I3f4d611313325dba66905e0c8ef391765a1fe7a7 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76210 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-06-30mb/google/rex/var/ovis: Fix mux change as per schematicsSubrata Banik
This patch updates the mux connection to reflect the Ovis schematics dated June to ensure Type-C1 is able to work in DP-ALT mode. BUG=b:289300284 TEST=Able to get display over Type-C1 port. Change-Id: I223eb3a96e6a1b3abb4168fcf59c0df04c1b4498 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76149 Reviewed-by: Jakub Czapiga <jacz@semihalf.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2023-06-28mb/google/rex/var/ovis: Enable crashlog and IOE dieJakub Czapiga
BUG=b:262501347 TEST=Boot on Ovis board. Change-Id: I43aac857e3ec7989c9ab5201cd8f24a7c877e76b Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76151 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-06-28mb/google/rex: Avoid boot hang due to missing SOC/IOE SRAM deviceSubrata Banik
The SOC/IOE SRAM device is used to store crash logs. Previously, the crashlog enablement was hardcoded in the baseboard.common module. This commit moves the crashlog enablement logic to the baseboard module, so that it can be enabled or disabled based on the specific baseboard. Additionally, the SOC/IOE SRAM is now enabled by default in the baseboard devicetree.cb file. This prevents the system from hanging if the SOC/IOE SRAM device is not present. BUG=b:262501347 TEST=Able to build and boot google/screebo with this patch. w/o this patch: [ERROR]  SOC SRAM device not found! [ERROR]  IOE SRAM base not valid Change-Id: I02d581e5b62cfa114a3761a9704ad9f24dead8aa Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76134 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-06-28mb/google/rex/var/ovis: Enable SaGvSubrata Banik
This patch enables SaGv with fixed frequency and gears for Ovis. Restrict memory speed to 6400 MTS as per board design. BUG=b:282164577 TEST=Verified the settings on google/ovis using debug FSP logs Change-Id: Ia9703344a8ae9d2ba44a16c62afab820fd8e2177 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76138 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-28mb/google/rex: Set TCC to 90°CSumeet Pawnikar
Set tcc_offset value to 20 in devicetree for Thermal Control Circuit (TCC) activation feature for rex variants. BUG=b:270664854 BRANCH=None TEST=Build FW and test on rex board Change-Id: I0567b6240fcb53f38158c381b700169475cf3795 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76110 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-06-26mainboard/google/rex: Enable crashlogPratikkumar Prajapati
Enable crashlog for rex. Select config options SOC_INTEL_CRASHLOG, and SOC_INTEL_IOE_DIE_SUPPORT. Also enable ioe_shared_sram and pmc_shared_sram devices. BUG=b:262501347 TEST=Able to trigger Crashlog, BERT table gets generated and decodes as expected. Change-Id: I3d3a9fb41d1293f021ad9de9b29c756cb7559373 Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74770 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-06-26mb/google/rex: Avoid LPDDR5/x hangSubrata Banik
This patch avoids random hang issue observed after booted to OS on LPDD5/x platforms due to CLK not tuned properly in SAGV point 0, 2133MT/s. As per Intel doc 769410 the expected work around is to change SAGV point 0 from 2133 G4 to 3200 G4. BUG=b:287170545 TEST=Able to perform 500 power cycles on google/rex without any hang. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I02a9cadc075f396549703d7a008382e76268f865 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76076 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-23mb/google/rex: Configure ISH GPIO's based on FW_CONFIGBernardo Perez Priego
Configures ISH related GPIO's based on FW_CONFIG obtained from CBI. BUG=b:280329972,b:283023296 TEST= Set bit 21 of FW_CONFIG with CBI Boot rex board Check that ISH is enabled, loaded, and functional Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com> Change-Id: I3f0f9a7c8318fa9ae59b6f613eafdacbfa07c749 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75525 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-06-23soc/intel/meteorlake: Rename shared SRAM aliasesPratikkumar Prajapati
Rename shared SRAM aliases for IOE and PMC to make them more readable. pci device 13.3 is IOE shared sram, renamed to ioe_shared_sram. pci device 14.2 is PMC shared sram, renamed to pmc_shared_sram. Rename them in SOC code as well as mainboard to make sure the patch builds for the relevant boards. BUG=b:262501347 TEST=Able to build. Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati@intel.com> Change-Id: I02a8cacc075f396549703d7a008382e76258f865 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75999 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-23mb/google/rex: Keep CNVi PCI device enabled for OvisSubrata Banik
The CNVi PCI device is required for the system to boot properly. By ensuring that this device is enabled, we can prevent the below error message from appearing and ensure that the system boots successfully. BUG=b:274421383 TEST=Able to build and boot google/ovis without any error. w/o this patch: [ERROR] CNVi WiFi is enabled without CNVi being enabled [ERROR] CNVi BT is enabled without CNVi being enabled Change-Id: I4dbae14f0cfccf96a33437a0e2fdefb508209354 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76001 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
2023-06-22mb/google/rex: Disable TCSS config for pre-boot displayKapil Porwal
Pre-boot display is not POR for google/rex hence disable the config ENABLE_TCSS_DISPLAY_DETECTION. BUG=b:247670186 TEST=Build and boot to google/rex and make sure that display over TCSS works in the OS Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: Ib55e251a4620c7a375ee2f27763154c39207236e Reviewed-on: https://review.coreboot.org/c/coreboot/+/75927 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-06-21mb/google/rex/var/screebo: set HBR smbus pin as NCSimon Zhou
Since GPP_C03/GPP_04 are floating in HW design, we set HBR smbus pin as NC, in case it prevents ese and cse from entering suspend. BUG=b:283053968 TEST=Verified on screebo non-TBT SKU, suspend and resume works. Change-Id: I401db32f0286de61ce3ab6c61de9528ec76cb51d Signed-off-by: Simon Zhou <zhouguohui@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75643 Reviewed-by: Kun Liu <liukun11@huaqin.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-21mb/google/rex: Fix PLD for USB type-A portKapil Porwal
USB type-A port with same PLD.token information as USB type-C port, causes conflict while generating ACPI code for the EC CONN device. Use a different PLD.token number for type-A port to fix the issue. BUG=b:286328285 TEST=check ACPI can have right USB port in EC CON. before patch: Package (0x02) { "usb2-port", \_SB.PCI0.XHCI.RHUB.HS01 }, Package (0x02) { "usb3-port", \_SB.PCI0.TXHC.RHUB.SS01 }, after patch: Package (0x02) { "usb2-port", \_SB.PCI0.XHCI.RHUB.HS01 }, Package (0x02) { "usb3-port", \_SB.PCI0.TXHC.RHUB.SS03 }, Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: If3e76c11dd6808eee4c9c2f3f71604a60379b5a5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75911 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2023-06-21mb/google/rex/var/ovis: Select SOC_INTEL_METEORLAKE_U_HJakub Czapiga
Ovis uses MTL-H. BUG=b:274421383 TEST=util/abuild/abuild -p none -t google/rex -x -a -b ovis TEST=cros build-packages --board ovis chromeos-bootimage Change-Id: I284c72b902490187d0b15e4fc81650af1cfa16d7 Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75887 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-21meteorlake: Rename `SOC_INTEL_METEORLAKE_U_P` as per latest EDSSubrata Banik
This patch renames config `SOC_INTEL_METEORLAKE_U_P` to `SOC_INTEL_METEORLAKE_U_H` as per Intel Meteor Lake Processor EDS version 1.3.1 (doc number: 640228). With new branding, the MTL-U/H-Processor Line offered in a 1-chip platform that includes the Compute, SOC, GT, and IOE tile on the same package. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I032be650bbfef0bf0ef86bb37417b1d854303501 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75931 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
2023-06-20mb/google/rex/var/rex0: Configure I2C timing for I2C devicesIvy Jian
Configure I2C0/1/3/4 timing in devicetree to ensure I2C devices meet timing requirement. Note that I2C5 timing will be updated separately when the tuning done BUG=b:280559903 TEST=Build and check I2C devices timing meet spec. | | I2C0-Codec | I2C0-WFC | I2C1 | I2C3 | I2C4 | |-------------|------------|----------|--------|-------|---------| | FSMB(KHz) | 347 | 343.2 | 389.3 | 393.7 | 381.9 | | TLOW(us) | 2.1 | 2.093 | 1.895 | 1.902 | 1.953 | | THIGH(us) | 0.647 | 0.628 | 0.602 | 0.62 | 0.612 | | THD:STA(us) | 0.633 | 0.64 | 0.601 | 0.6 | 0.601 | | TSU:STA(us) | 0.617 | 0.621 | 0.619 | 0.659 | 0.61 | | TSU:STO(us) | 0.656 | 0.647 | 0.667 | 0.727 | 0.634 | | TBUF(us) | 86.15 | >14.088 | >9.833 | >8 | >10.366 | Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Change-Id: I5421e4fe68e856bbe9f19544954a94670c895a47 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75150 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2023-06-20mb/google/rex/var/screebo: Remove rp2 and add rp1/rp3Rui Zhou
Remove rp2 and add rp1/rp3 for screebo BUG=b:286187816 BRANCH=none TEST=emerge-rex coreboot and verify TBT works. Change-Id: I1013d26c705f2a3f9378d944bd863d94f319d36c Signed-off-by: Rui Zhou <zhourui@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75832 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Simon Zhou <zhouguohui@huaqin.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-18mb/google/rex/variants/ovis: Add display configurationJakub Czapiga
Enable DDI on ports 1 to 4 for Type-C DisplayPort. BUG=b:274421383 TEST=util/abuild/abuild -p none -t google/rex -x -a -b ovis Change-Id: I40f967b12b11c10a1a9329bfb42ebec5a8d7738f Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75579 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-17mb/google/rex: Set AUX orientation at SoC to follow cable for anx7452Caveh Jalali
This configures the SoC to flip the orientation of the AUX pins to follow the orientation of the cable when using the anx7452 retimer. This is necessary when there is no external retimer/mux or the retimer/mux does not implement the flip. The anx7452 retimer does not appear to support this feature, so let the SoC do the flip. BUG=b:267589042,b:281006910 TEST=verified DP-ALT mode works on rex using both cable orientations Change-Id: Ibb9f442d2afd81fb5dde4bca97c15457837f9f4a Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75827 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2023-06-17soc/intel/meteorlake: Update tcss_usb3 aliasEric Lai
TCSS and TBT use the same lane on schematic. Update the port start from 0 to match the Intel schematic. You can better follow the it without convert the port number. Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: Ic6631dcbbd9f6c79c756b015425e2da778eb395e Reviewed-on: https://review.coreboot.org/c/coreboot/+/75892 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-06-15mb/google/rex: Enable audio BT offloadRavi Sarawadi
This patch enables BT offload feature on Rex over SSP1. BT mode is selected via FW_CONFIG and corresponding VGPIOs are programmed. BUG=b:275538390 TEST=Verified audio playback using BT speaker/headset in I2S mode on google/rex. Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Change-Id: I46e9702add37464122ffc78826ebf8a6c5b5b07c Reviewed-on: https://review.coreboot.org/c/coreboot/+/72881 Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-15mb/google/rex: add Elan HID over SPI ASL for Rex0Eran Mitrani
This patch enables adding variant specific ASL code TEST=Kernel driver is able to communicate with device Signed-off-by: Eran Mitrani <mitrani@google.com> Change-Id: I231482d56dd4afa150766c07cfde105158e5e124 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74886 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-06-14mb/google/rex/var/rex0: add HID over SPI ACPI driverEran Mitrani
Add driver to support ELAN touchscreen using SPI for rex * See "HID Over SPI Protocol Specification" section 5.2 - ACPI enum * https://www.microsoft.com/en-us/download/details.aspx?id=103325 BUG=b:278783755 TEST=Kernel driver is able to communicate with device. Also tested S0ix, ran 'suspend_stress_test -c 1' - no issues in suspend/resume. Signed-off-by: Eran Mitrani <mitrani@google.com> Change-Id: Id51d385ce350cef23da4184b044c74569f4dd3f0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74885 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-06-14mb/google/rex/variants/ovis: Add basic DTTJakub Czapiga
Add default Intel DPTF. BUG=b:274421383 TEST=util/abuild/abuild -p none -t google/rex -x -a -b ovis Change-Id: Ib023f6d6d184f6935a6a454250755502a46b707f Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75580 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-06-14mb/google/rex/variants/ovis: Add USB and TCSS configurationJakub Czapiga
+-------------+----------------+------------+---------------------------------+ | PCH USB 2.0 | Connector Type | OC Mapping | Remarks | +-------------+----------------+------------+---------------------------------+ | 1 | Type-C | OC_0 | Type C port - TCP1 | | 2 | Type-C | OC_0 | Type C port - TCP0 | | 3 | Type-C | OC_0 | Type C port - TCP2 | | 4 | Type-A | OC_3 | USB3.2 Gen2x1 Type-A Port – TAP0| | 7 | Type-A | OC_3 | TAP1 | | 8 | Type-A | OC_3 | TAP2 | | 9 | Type-A | OC_3 | TAP3 | +-------------+----------------+------------+---------------------------------+ +---------------------+-------------------+------------+---------+ | PCH USB 3.1 Gen 2x1 | Connector Details | OC Mapping | Remarks | +---------------------+-------------------+------------+---------+ | 1 | Type-A | OC_3 | TAP0 | | 2 | Type-A | OC_3 | TAP1 | +---------------------+-------------------+------------+---------+ +------+-------------------+------------+-----------------------------+ | TCPx | Connector Details | OC Mapping | Remarks | +------+-------------------+------------+-----------------------------+ | 1 | Type C port 0 | OC_0 | To onboard Type-C connector | | 2 | Type C port 1 | OC_0 | To onboard Type-C connector | | 3 | Type C port 2 | OC_0 | To onboard Type-C connector | +------+-------------------+------------+-----------------------------+ BUG=b:274421383 TEST=util/abuild/abuild -p none -t google/rex -x -a -b ovis Change-Id: Icc81f12ec6cc4af37bcc1fcf3164cbfa5612a443 Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75578 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-06-12mb/google/rex/var/screebo: Enable touchscreenZhongtian Wu
Enable ILI2901 and eKTH7B18 touchscreen for Google Screebo. BUG=b:278167967 BRANCH=none TEST=Build and boot to Google Screebo. Verify touchscreen works. Change-Id: I57d55c5f2621d6fafd53b19d12ecad20271cdbb1 Signed-off-by: Zhongtian Wu <wuzhongtian@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75692 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Rui Zhou <zhourui@huaqin.corp-partner.google.com>
2023-06-12mb/google/rex/variants/ovis: Enable EC in device treeJakub Czapiga
BUG=b:274421383 TEST=util/abuild/abuild -p none -t google/rex -x -a -b ovis Change-Id: I6f3fa6543a4cec8c2562196105f17fbc7831bab7 Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75577 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-06-07mb/google/rex/variants/ovis: Add SSD card configJakub Czapiga
BUG=b:274421383 TEST=util/abuild/abuild -p none -t google/rex -x -a -b ovis Change-Id: I3795313e784595ac02ee2a38f466bcb9e613a6a4 Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75576 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Jan Dabros <dabros@google.com>
2023-06-07mb/google/rex/variants/ovis: Add I2C configJakub Czapiga
BUG=b:274421383 TEST=util/abuild/abuild -p none -t google/rex -x -a -b ovis Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Change-Id: I1644b1d8f49accbb2ea68e236534df80a5151360 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75503 Reviewed-by: Jan Dabros <dabros@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-06-07mb/google/rex/variants/ovis: Add GPIO configurationJakub Czapiga
Based on Platform Mapping Document for Ovis (go/ovis_mapping_doc) state for June 6, 2023 (Rev 0.3) BUG=b:274421383 TEST=util/abuild/abuild -p none -t google/rex -x -a -b ovis Change-Id: Iae3ca243a245928e8ec3d48877cf578843922fc7 Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75502 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-06mb/google/rex/var/rex0: Add new GFX devices with custom _PLDWon Chung
Add new GFX devices for DDI and TCP with custom _PLD to describe the corresponding ports. BUG=b:277629750 TEST=emerge-rex coreboot Signed-off-by: Won Chung <wonchung@google.com> Change-Id: I193b95e8bd8ae538c4f25fbe772b174ef455d744 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74367 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-06-06mb/google/rex/variants/ovis: Add RAM IDsJakub Czapiga
BUG=b:274421383 TEST=util/abuild/abuild -p none -t google/rex -x -a -b ovis Change-Id: Ic555fac846ebf1e9dad81b5847334c03d6804b5b Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75501 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-06-06mb/google/rex: Create ovis variantJakub Czapiga
BUG=b:274421383 TEST=util/abuild/abuild -p none -t google/rex -x -a ; Make sure GOOGLE_OVIS built successfully Change-Id: I5c8f290cfdcb4d47c0e5e9d72c1e34073b957681 Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75385 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-06mb/google/rex/var/rex0: probe for i2c1 touchscreenEran Mitrani
Touchscreen may either use I2C1 or SPI0. FW_CONFIG.TOUCHSCREEN is set to determine which is used. This CL adds a probe to enable I2C1. BUG=b:278783755 TEST=Tested on rex, confimed i2c1 is disabled when TOUCHSCREEN != TOUCHSCREEN_I2C Signed-off-by: Eran Mitrani <mitrani@google.com> Change-Id: I0bee176298fddd2aee35cf084db037a3ce7672f7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75565 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-06-04mb/google/rex: add macro for touchscreen IRQEran Mitrani
BUG=b:278783755 Signed-off-by: Eran Mitrani <mitrani@google.com> Change-Id: I2a6de778c7ab30a9946e100cb70c092ba98496e3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74944 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-04mb/google/rex: Enable ISH supportBernardo Perez Priego
Enable ISH based on FW_CONFIG obtained from EC CBI. This is useful in case device is a tablet and motion sensors are handled by ISH instead of EC. BUG=b:280329972,b:283023296 TEST= Set bit 21 of FW_CONFIG with CBI Boot rex board Check that ISH is enabled and loaded Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com> Change-Id: Ibe0e1b8ce2c9b08ac6b1e6fef9bd19afc9b4f59f Reviewed-on: https://review.coreboot.org/c/coreboot/+/75039 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-04mb/google/rex,screebo: Update GPIO PAD IO Standby StateBora Guvendik
Fix for the "Onboard Keyboard and Type-C ports are not working after resuming from powerd_dbus_suspend" issue. This issue was caused since FSP 3165 FSP was fixed and started skipping GpioConfigureIoStandbyState programming when GpioOverride UPD is enabled. This patch moves the IO Standby State programming that FSP was doing to coreboot. BUG=b:284264580 TEST=Boot to OS, compare gpio pins, verify keyboard / Type-C Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Change-Id: If96c1e71fdde784a55fe079875915ffa5a4f548a Reviewed-on: https://review.coreboot.org/c/coreboot/+/75555 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-02 22:50:58 +0000