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path: root/src/mainboard/google/rex/variants
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2023-06-06mb/google/rex/var/rex0: probe for i2c1 touchscreenEran Mitrani
Touchscreen may either use I2C1 or SPI0. FW_CONFIG.TOUCHSCREEN is set to determine which is used. This CL adds a probe to enable I2C1. BUG=b:278783755 TEST=Tested on rex, confimed i2c1 is disabled when TOUCHSCREEN != TOUCHSCREEN_I2C Signed-off-by: Eran Mitrani <mitrani@google.com> Change-Id: I0bee176298fddd2aee35cf084db037a3ce7672f7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75565 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-06-04mb/google/rex: add macro for touchscreen IRQEran Mitrani
BUG=b:278783755 Signed-off-by: Eran Mitrani <mitrani@google.com> Change-Id: I2a6de778c7ab30a9946e100cb70c092ba98496e3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74944 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-04mb/google/rex: Enable ISH supportBernardo Perez Priego
Enable ISH based on FW_CONFIG obtained from EC CBI. This is useful in case device is a tablet and motion sensors are handled by ISH instead of EC. BUG=b:280329972,b:283023296 TEST= Set bit 21 of FW_CONFIG with CBI Boot rex board Check that ISH is enabled and loaded Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com> Change-Id: Ibe0e1b8ce2c9b08ac6b1e6fef9bd19afc9b4f59f Reviewed-on: https://review.coreboot.org/c/coreboot/+/75039 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-04mb/google/rex,screebo: Update GPIO PAD IO Standby StateBora Guvendik
Fix for the "Onboard Keyboard and Type-C ports are not working after resuming from powerd_dbus_suspend" issue. This issue was caused since FSP 3165 FSP was fixed and started skipping GpioConfigureIoStandbyState programming when GpioOverride UPD is enabled. This patch moves the IO Standby State programming that FSP was doing to coreboot. BUG=b:284264580 TEST=Boot to OS, compare gpio pins, verify keyboard / Type-C Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Change-Id: If96c1e71fdde784a55fe079875915ffa5a4f548a Reviewed-on: https://review.coreboot.org/c/coreboot/+/75555 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-04mb/google/rex/var/screebo: Add devicetree for support audioRui Zhou
Add devicetree config for ALC1019_ALC5682I_I2S BUG=b:278169268 TEST=emerge-rex coreboot and verified on screebo Change-Id: I2814cc76aff43daf0353cfef41592591bbe3d213 Signed-off-by: Rui Zhou <zhourui@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75575 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Simon Zhou <zhouguohui@huaqin.corp-partner.google.com> Reviewed-by: Mac Chiang <mac.chiang@intel.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-06-03mb/google/rex: Create karis variantTyler Wang
Create the karis variant of the rex0 reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0.) BUG=b:285195072 TEST=util/abuild/abuild -p none -t google/rex -x -a make sure the build includes GOOGLE_KARIS Change-Id: I16d8b43390401789b87a6233238e37f32a17b46b Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75551 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-06-02mb/google/rex/variants/screebo: add FW_CONFIG for audio/DBSimon Zhou
This patch adds FW_CONFIG to accommodate different Screebo BOM components across various SKUs. 1. DB_CONFIG for DB_TPEC/DB_TBT/DB_UNKOWN 2. AUDIO for ALC1019_ALC5682I_I2S/AUDIO_UNKNOWN BUG=b:278169268 TEST=build pass Change-Id: I928aae61d4936509a7b68f4041c0cd72f298e83d Signed-off-by: Simon Zhou <zhouguohui@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75573 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: YH Lin <yueherngl@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Mac Chiang <mac.chiang@intel.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-05-31mb/google/rex/var/screebo: Add MIPI camera devicejason.z.chen
Enabling MIPI UCAM for screebo project BUG=b:277883010 TEST=none Signed-off-by: jason.z.chen <jason.z.chen@intel.corp-partner.google.com> Change-Id: Id06e5c162d911a4bd78190757c25e7f760160a8f Reviewed-on: https://review.coreboot.org/c/coreboot/+/75157 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Haikun Zhou <zhouhaikun5@huaqin.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-05-31mb/google/rex/var/screebo: Set TCC to 90°CWentao Qin
Set tcc_offset value to 20 in devicetree for Thermal Control Circuit (TCC) activation feature for proto phase. BUG=b:282865187 BRANCH=None TEST=Build FW and test on Screebo board Change-Id: I3a929aa20a700376d2a0a150911fed34e67f78eb Signed-off-by: Wentao Qin <qinwentao@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75360 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Haikun Zhou <zhouhaikun5@huaqin.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-31mb/google/rex: Enable SoundWire codecsKapil Porwal
Enable drivers for SoundWire codecs and define the topology in the devicetree for the rex0 variant with the SoundWire daughter board connected. +------------------+ +--------------------+ | | | Headphone Codec | | Intel Meteor Lake| +--->|Cirrus Logic CS42L42| | SoundWire | | | ID 0 | | Controller | | +--------------------+ | | | | Link 0 +----+ +-------------------+ | | | Left Speaker Amp | | Link 1 | +--->| Maxim MAX98363 | | | | | ID 0 | | Link 2 +----| +-------------------+ | | | | Link 3 | | +-------------------+ | | | | Right Speaker Amp | +------------------+ +--->| Maxim MAX98363 | | ID 1 | +-------------------+ This was tested by booting the firmware and dumping the SSDT table to ensure that all SoundWire ACPI devices are created as expected with the properties that are defined in coreboot under \_SB.PCI0: HDAS - Intel Meteor Lake HDA PCI device HDAS.SNDW - Intel Meteor Lake SoundWire Controller HDAS.SNDW.SW00 - Cirrus Logic CS42L42 - Headphone Codec HDAS.SNDW.SW20 - Maxim MAX98363 - Left Speaker Amp HDAS.SNDW.SW21 - Maxim MAX98363 - Right Speaker Amp BUG=b:269497731 TEST=Verified SSDT for SNDW in the OS. Playback and recording are also validated on google/rex. Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: I3e11dc642ff686ba7da23ed76332f7f10e60fade Reviewed-on: https://review.coreboot.org/c/coreboot/+/73280 Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-29mb/google/rex: Update GPIO PAD as per Proto 2 schematicsSubrata Banik
BUG=b:283477280 TEST=Able to build and boot google/rex as per Proto 2 schematics dated 05/16. +-----------------+------------------------------------+---------------------------+--------+ | GPIO | In Proto 1 | In Proto 2 | Impact | +-----------------+------------------------------------+---------------------------+--------+ | GPP_C01 | SOC_TCHSCR_RST_L | SOC_TCHSCR_RST_R_L | N | +-----------------+------------------------------------+---------------------------+--------+ | GPP_D19 | NC | EC_SOC_REC_SWITCH_ODL | Y | +-----------------+------------------------------------+---------------------------+--------+ | GPP_E04 | HPS_INT_L | SOC_PEN_DETECT | N | +-----------------+------------------------------------+---------------------------+--------+ | GPP_E17 | EN_HPS_PWR | EN_PP3300_SPARE_X | N | +-----------------+------------------------------------+---------------------------+--------+ | GPP_F13 | GSPI1_SOC_MISO | GSPI1_SOC_MISO_R | N | +-----------------+------------------------------------+---------------------------+--------+ | GPP_F21 | GPIO_F21_SPI_CS_L | SPI_SOC_CS_UWB_L_STRAP | N | +-----------------+------------------------------------+---------------------------+--------+ | GPP_H00 | GPIO_H00_SPI_CLK_R | SPI_SOC_CLK_UWB_STRAP_R | N | +-----------------+------------------------------------+---------------------------+--------+ | GPP_H01 | GPIO_H01_SPI_MOSI_R | SPI_SOC_DO_UWB_DI_STRAP_R | N | +-----------------+------------------------------------+---------------------------+--------+ | GPP_H02 | GPIO_H02_SPI_MISO | SPI_SOC_DI_UWB_DO_STRAP | N | +-----------------+------------------------------------+---------------------------+--------+ | GPP_S00 | UNNAMED_8_METEORLAKEU_I137_GPPS00 | SDW_HP_CLK_WLAN_PCM_CLK | N | +-----------------+------------------------------------+---------------------------+--------+ | GPP_S01 | UNNAMED_8_METEORLAKEU_I137_GPPS01 | SDW_HP_DATA_WLAN_PCM_SYNC | N | +-----------------+------------------------------------+---------------------------+--------+ | GPP_S02 | UNNAMED_8_METEORLAKEU_I137_GPPS02 | DMIC_SOC_CLK0_WLAN_PCM_OUT| N | +-----------------+------------------------------------+---------------------------+--------+ | GPP_S03 | UNNAMED_8_METEORLAKEU_I137_GPPS03 | DMIC_SOC_DATA0_WLAN_PCM_IN| N | +-----------------+------------------------------------+---------------------------+--------+ Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I4a8c43b0f845d3446188b7c926e482f91e5b45aa Reviewed-on: https://review.coreboot.org/c/coreboot/+/75407 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-05-26mb/google/rex/variants/baseboard/rex: Add CPU power limit valuesSumeet Pawnikar
Add support of variant_devtree_update() function to override devtree settings for variant boards. Also, add CPU power limit values for rex baseboard. BRANCH=None BUG=b:270664854 TEST=Built and verified power limit values as below log message for 15W SKU on Rex board. Overriding power limits PL1 (mW) (10000, 15000) PL2 (mW) (57000, 57000) PL4 (W) (114) Change-Id: If46445157358e3e0f227e26a35b4303fc9189a4b Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74754 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Harsha B R <harsha.b.r@intel.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-05-26mb/google/rex: Set frequency and gears for SaGv pointsBora Guvendik
Restrict memory speed to 6400 MTS as per board design. BUG=b:282164577 TEST=Verified the settings on google/rex using debug FSP logs. Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Change-Id: I3dec383c7c585b80a73089f3403011c5cda61f65 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75291 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-05-26mb/google/rex/var/screebo: Enable touchpadZhongtian Wu
Enable touchpad for Google Screebo. BUG=b:278160238 BRANCH=none TEST=Build and boot to Google Screebo. Verify touchpad works. Change-Id: Ib83e5ef5ca497592f5a26aa1e85d793d06d9dd7f Signed-off-by: Zhongtian Wu <wuzhongtian@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75412 Reviewed-by: Kun Liu <liukun11@huaqin.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-05-25mb/google/rex: Enable SaGvSubrata Banik
This patch overrides `SaGv` FSP-M UPD to enable SaGv feature to be able to train memory (DIMM) at different frequencies. On all latest Intel based platforms SaGv is expected to be enabled to support dynamic switching of memory operating frequency. BUG=b:267879107 TEST=Able to verify SaGv is enabled with 3 work point (0, 1 and 2) and MRC retraining takes around ~20ms extra compared to SaGv being disabled. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ic680bfeab4dd285c0d3916ba5e917cc12bae3284 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73534 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-24mb/google/Screebo: Enable AUX DC biasing on C0Simon Zhou
SKU1A C0 has no redriver, so enable SBU muxing in the SoC. BUG=b:283044004 BRANCH=none TEST=Voltages are correct on the C0 and C1 AUX bias pins Change-Id: I18b4ade2c60c270855fb2e733a9201539e08d8ba Signed-off-by: mike <mike5@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75381 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-05-24mb/google/rex/var/screebo: Add BT devicetree configqinwentao
Enabling BT for screebo project BUG=b:278169273 TEST=Check whether BT can connect to Bluetooth device Signed-off-by: qinwentao <qinwentao@huaqin.corp-partner.google.com> Change-Id: I0ecd62abfbe751e1036948b1490844e7e63d7f0d Signed-off-by: qinwentao <qinwentao@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75352 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kun Liu <liukun11@huaqin.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-05-23mb/google/rex: Add FW_CONFIG and device for VPUEran Mitrani
BUG=b:282912666 TEST=set and unset bit20 in HW_CONFIG and check if VPU(0b.0) is enabled when bit20 is set, and disabled when cleared Signed-off-by: Eran Mitrani <mitrani@google.com> Change-Id: Iee6a9026a4d210407350bfb7ecc8a058e7ff5c24 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75303 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-05-23mb/google/rex: Add FW_CONFIG for TOUCH over SPIEran Mitrani
TEST=set the corresponding cbi bit, and saw SPI0 under sysfs BUG=b:278783755 Signed-off-by: Eran Mitrani <mitrani@google.com> Change-Id: I7099cde14cff90ad63e9164769f9913a8284a805 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74888 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-05-22mb/google/rex/var/screebo: enable fingerprintSimon Zhou
BUG=b:278156430 TEST=verify the fingerprint on screebo Change-Id: I986e470b28145f7b17427e794055929a4283c721 Signed-off-by: Simon Zhou <zhouguohui@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75287 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dolan Liu <liuyong5@huaqin.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-05-19mb/google/rex: Enable stylus supportDinesh Gehlot
This patch enables stylus support by configuring the "GPP_D08" irqs for rex SoC. This allows the SoC to detect a stylus device, when in use. However stylus is not a wake up source for the rex. BUG=b:282256460 Test=Stylus is detected on proto1 device. Signed-off-by: Dinesh Gehlot <digehlot@google.com> Change-Id: I84a71aa664698e105b738f8680d0a4751ca1fc72 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71820 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-05-14mb/google/rex: Add variant specific SOC chip config update functionAnil Kumar
This patch adds support for variant specific chip config update similar to commit 061a93f93d2 ("mb/google/brya: Add variant specific soc chip config update"). Signed-off-by: Anil Kumar <anil.kumar.k@intel.com> Change-Id: I60a4042cba608fd527527af9340ec0215f3086ca Reviewed-on: https://review.coreboot.org/c/coreboot/+/75046 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-05-14mb/google/rex/var/screebo: Add initial devicetree configKun Liu
add initial devicetree config for screebo BUG=b:276814951 TEST=emerge-rex coreboot Change-Id: Ie64d0e50ec22b3e363597af64eb723ef1f86dfa8 Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74972 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-05-14screebo: fix the lp5ccc config from 0x55 to 0xaaSimon Zhou
BUG=b:278022971 TEST=verified on screebo Change-Id: I16f1d66ca7f885120358eb2a2d3c6fb111319f11 Signed-off-by: Simon Zhou <zhouguohui@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75173 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-12mb/google/rex: Set WWAN_RF_DISABLE_ODL to NCTarun Tuli
This signal isn't functionally being used and is causing leakage during suspend. Set it to NC. BUG=b:279762779 TEST=builds. WWAN functional. Change-Id: I93f2b0a781e250678280b57e4ab1d80ef27ff460 Signed-off-by: Tarun Tuli <taruntuli@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75053 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-05-08mb/google/rex/var/rex0: Correct _PLD values for USB C0Won Chung
Denote the correct value of ACPI _PLD for USB ports. The horizontal position of port C0 is incorrectly labelled. +----------------+ | | | Screen | | | +----------------+ C0 | | A0 | | C1 | | +----------------+ BUG=b:216490477 TEST=emerg-rex coreboot Signed-off-by: Won Chung <wonchung@google.com> Change-Id: Id9ed435ca0af131e3bb4538701fc97d78146899f Reviewed-on: https://review.coreboot.org/c/coreboot/+/74366 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-06mb/google/rex/var/screebo: Add DDR DQ map configKun Liu
Add DDR DQ map config for screebo BUG=b:276814951,b:272218757 TEST=emerge-rex coreboot Change-Id: I993ae4024689b9cedbea247689a760bd83cd0d45 Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74961 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2023-04-29mb/google/rex/variants/screebo: Generate RAM IDsKapil Porwal
Generate RAM IDs for - MT62F512M32D2DR-031 WT:B (LP5) H9JCNNNBK3MLYR-N6E (LP5) MT62F1G32D2DS-026 WT:B(LP5x) H58G56BK7BX068 (LP5X) BUG=b:276814951 TEST=Run part_id_gen tool without any errors Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: I0fb2e488c06ed74d3fd493e5ca0ab89a825a9349 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74802 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-04-28mb/google/rex/var/screebo: Add initial setup for gpio configKun Liu
add the initial gpio configuration for screebo initial variant BUG=b:276814951 TEST=emerge-rex coreboot Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com> Change-Id: Ib96e03f47bc1d6e5628ae459c3e1eb4dc18849c7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74475 Reviewed-by: YH Lin <yueherngl@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-04-27mb/google/rex: Add USB4 ANX7452 Rev 2 to USB_DB FW_CONFIGSubrata Banik
This patch adds new USB_DB FW_CONFIG to enable support for USB4 ANX7452 Rev 2. BUG=b:279647370 TEST=Able to build and boot google/rex with Proto 2 SKU Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I878b591e5919d05d3c5fc2eefdeb492e95d4f7b5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74775 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: YH Lin <yueherngl@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-04-17mb/google/rex: Enable all DDI lanesAnil Kumar
This patch enables all DDI ports on Rex board to support display port tunneling and dual display on TBT dock. BUG=b:273901499 TEST=Boot google/rex and connect two displays over a TBT dock and check the display functionality. Signed-off-by: Anil Kumar <anil.kumar.k@intel.com> Change-Id: I45ee5334fbb877bd58912c8d24920037f155dc42 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74413 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-16mb/google/rex: Create screebo variantSimon Zhou
Create the screebo variant of the rex0 reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0). BUG=b:276814951 BRANCH=None TEST=util/abuild/abuild -p none -t google/rex -x -a make sure the build includes GOOGLE_SCREEBO Change-Id: I8d05ca7c0fe596378ca15d0734d46ad1dc63a1f9 Signed-off-by: Simon Zhou <zhouguohui@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74391 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-04-12mb/google/rex: remove weak from cros gpioEric Lai
No need for variant to use _weak. BUG=b:276818954 TEST=new_variant_fulltest.sh rex0 Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: I7ad904e06e5d83edf4bc11cafd5060ca409bd4ae Reviewed-on: https://review.coreboot.org/c/coreboot/+/74294 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
2023-04-11mb/google/rex: Add DTT thermal settings for thermal controlSumeet Pawnikar
Add DTT thermal settings for thermal control provided by thermal team for rex0 board BRANCH=None BUG=b:262498724, b:270664854 TEST=Built and verified thermal entries in ACPI SSDT on Rex board Change-Id: I00dd97b759c8c68edaeeb4d64422b83c5e86981d Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71166 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-04-03mb/google/rex: Use FW_CONFIG for generating ACPI code for WIFISubrata Banik
This patch avoids creating runtime ACPI for unused WIFI solutions. For example: if the Rex SKU is with WIFI_CNVI then you don't need to populate ACPI code for WIFI_PCIE. FW_CONIG can be used for making those decisions. TEST=No ASL entries being created for WIFI_PCIE if the FW_CONIG is set to WIFI_CNVI. Also, helped to save the boot time on google/rex (FSP-S API) by 9ms. Change-Id: I60e4332d8d8c360fdf425b30513ff79209979e85 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74147 Reviewed-by: YH Lin <yueherngl@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-04-01mb/google/rex: Add FW_CONFIG for FP/UWB/WIFISubrata Banik
This patch adds FW_CONFIG to accommodate different Rex BoM components across various SKUs. 1. Fingerprint sensor - FP Present/Absent 2. Ultra wideband - UWB Absent/Using BITBANG/Using GSPI1 3. WIFI - CNVi/PCIe TEST=Able to build and boot google/rex. Change-Id: I97b0dc25f239103a0a235f14b50008a633e2f88d Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74146 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: YH Lin <yueherngl@google.com>
2023-03-30Revert "mb/google/rex: Enable VPU"Kapil Porwal
This reverts commit 555ceca38a78 ("mb/google/rex: Enable VPU"). Reason: Unable to boot to latest OS image with VPU enabled. BUG=none TEST=Boot to OS image 15376 on google/rex Change-Id: If61282528922304373d492b362056b52995cbcad Signed-off-by: Kapil Porwal <kapilporwal@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73694 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Paz Zcharya <pazz@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2023-03-25mb/google/rex: Use HI-556W for Proto 1 SKUsSubrata Banik
This patch drops the UFC sensor OV2740 (reused from the Brya chassis) support for Rex and added support for Rex specific UFC sensor HI-556W. BUG=b:269499723 TEST=Verified UFC is working on google/rex Proto 1. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I6b8ac08adec351a103ac1764d974db4881dc4d6e Reviewed-on: https://review.coreboot.org/c/coreboot/+/70225 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
2023-03-20mb/google/rex: Enable USB camera powerIvy Jian
Add enable_gpio for USB power resource BUG=b:273891168 TEST=Able to detect USB CAM Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Change-Id: I08ebe560c8b75c8b590c889b7b90dbe678318d2a Reviewed-on: https://review.coreboot.org/c/coreboot/+/73754 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-03-15mb/google/rex: Add Hayden Bridge (HB) to USB_DB FW_CONFIGSubrata Banik
This patch increases FW_CONFIG for USB_DB to 3-bits. BUG=b:273346973 TEST=Able to build and boot google/rex with Proto 2 SKU Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ib07ba1d54e7f7e2b09a99438529e503d9c9edb7d Reviewed-on: https://review.coreboot.org/c/coreboot/+/73719 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-03-15mb/google/rex: Configure _DSC for camera devicesJamie Ryu
Configure _DSC to ACPI_DEVICE_SLEEP_D3_COLD so that the driver skips initial probe during kernel boot and prevent privacy LED blink. BUG=b:268607999 TEST=Build and boot rex proto1 to OS and verify privacy LED behavior. Change-Id: Ife849f7407b02867ddb992d7eebb08b0b44aecc8 Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73193 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kiran2 Kumar <kiran2.kumar@intel.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-03-08mb/google/rex: Rename touchscreen signals as per latest Rex schematicsEran Mitrani
Touchscreen signals were renamed for Rex schematics dated 21st Dec'22. This CL fixes the comments for those signals. BUG=b:263411413 TEST=None required (changed comments only) Signed-off-by: Eran Mitrani <mitrani@google.com> Change-Id: Ic40ef943d199d9f4a2bec9c0e6d4820224ef6adc Reviewed-on: https://review.coreboot.org/c/coreboot/+/71795 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-03-02mb/google/rex: Enable VPURavi Sarawadi
BUG=b:270529665 TEST=Verify the build and boot on Rex board Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Change-Id: I0e3d3312c546a2a468fb906a08b8d3ec3e96c46a Reviewed-on: https://review.coreboot.org/c/coreboot/+/72417 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-03-02mb/google/rex: Generate LP5 RAM ID for `K3KL6L60GM-MGCT`Subrata Banik
Add the support LP5 RAM parts for rex: DRAM Part Name ID to assign K3KL6L60GM-MGCT 3 (0011) BUG=b:270708359 TEST=emerge-rex coreboot Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Id0925ccec014c9c535178ed3d908e60889df624d Reviewed-on: https://review.coreboot.org/c/coreboot/+/73344 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-03-02mb/google/rex: Generate LP5 RAM ID for `H58G56BK7BX068`Subrata Banik
Add the support LP5 RAM parts for rex: DRAM Part Name ID to assign H58G56BK7BX068 1 (0001) BUG=b:270708359 TEST=emerge-rex coreboot Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I9eea7e277628992be9b7768a678a50425444002a Reviewed-on: https://review.coreboot.org/c/coreboot/+/73342 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-02-27mb/google/rex: Remove `fixme` from gpio.hKapil Porwal
Remove `fixme` from gpio.h since it has been addressed. BUG=none TEST=Only a cosmetic change Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: I79a2493dba6becd4b8c1ebf37e452a5a173eb396 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73270 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2023-02-23mb/google/rex: Set audio GPIOs based on fw_configKapil Porwal
Define some actions based on probe results for audio: - Disable the SoundWire GPIOs when I2S option is selected. - Disable the I2S GPIOs when SoundWire option is selected. - Disable all the GPIOs when no audio is enabled. BUG=b:269497731 TEST=Test that GPIOs are configured based on the current value of the fw_config field in cbi. Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: I0ed452a0d08e6779add318d9bbd1e97b50b6aea9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73121 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-02-23mb/google/rex: Use gpio padbased table overrideKapil Porwal
In order to improve gpio merge mechanism. Change iteration override to padbased table override. And the following patch will change fw config override with ramstage gpio table override. Port of commit 7aef2b1294f2 ("mb/google/nissa: Apply gpio padbased table override") BUG=none TEST=Verify devbeep at depthcharge console Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: I2ee86bbec7d25a35d726f29ad79891f1054bf52c Reviewed-on: https://review.coreboot.org/c/coreboot/+/73182 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-02-22mb/google/*: Resume from suspend on critical batteryIvan Chen
This patch makes EC wake up AP from s3/s0ix for OS shutdown/hibernate when the state of charge drops to low_battery_shutdown_percent. BUG=b:255465618 TEST=emerge-nissa chromeos-bootimage (EC: https://crrev.com/c/4243898) Verify system resumes from s0ix and then enter S5 on nivviks with steps: 1. disconnect AC 2. powerd_dbus_suspend --disable_dark_resume=false 3. fakebatt 5 4. fakebatt 4 Change-Id: I63b5246432687e38ddfc5733ac3a115c3456d7e9 Signed-off-by: Ivan Chen <yulunchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73082 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com>
2023-02-16mb/google/rex: Mark unused USB ports as emptySubrata Banik
This patch marks unused USB ports (USB2.0/TCSS) empty to avoid prompting wrong dmesg as below. ``` usb usb2-port3: Cannot enable. Maybe the USB cable is bad? ``` Mainboard variants to override the USB ports as per the target board design. TEST=Able to build and boot google/rex with all USB ports are working as expected. Change-Id: Ic3d21151a22f2318413f480f3386bf2dbf696307 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73027 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-02-14mb/google/rex: Set `SkipExtGfxScan` FSP-M UPDSubrata Banik
This patch overrides `SkipExtGfxScan` UPD as the Rex device is equipped with an on-board graphics device hence, skip scanning external GFX devices. BUG=b:228002764 TEST=Able to save ~1ms+ boot time on google/rex. FSP FPDT Data is showing the timestamp between those function calls. Without this patch: [INFO ] CheckOffboardPcieVga/5b7cc220-e183-481c-87f427a92d8db88f -> 979684 -> 22 [INFO ] CheckOffboardPcieVga/5b7cc220-e183-481c-87f427a92d8db88f -> 980815 -> 1131 With this patch: `CheckOffboardPcieVga` is not getting called. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I20aa09e80671ab94e639787f40b95b740bbe5efb Reviewed-on: https://review.coreboot.org/c/coreboot/+/72948 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-02-04mb/google/rex: Use OV13B10 sensor for Proto 1 SKUsSubrata Banik
This patch drops the WFC sensor OV8856 (reused from the Brya chassis) support for Rex and added support for Rex specific UFC sensor OV13B10. BUG=b:267264348 TEST=WFC MIPI cameras have been enabled using google/rex Proto 1. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ic785b82db4368f40d91921f29c218cf417938541 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70226 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2023-02-04Revert "UPSTREAM: mb/google/rex: Enable SaGv"Subrata Banik
Enabling `SaGv` along with FSP v2473 is causing blank display issue. Mostly likely we shouldn't enable SaGv yet on Intel MeteorLake. BUG=b:267446159 TEST=Able to see ChromeOS UI in consecutive boot. This reverts commit cbca81c5946384843197c08401c4266f45fef4a2. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ifbcc36515f7550c183c40e5af94684f5c3e39a7a Reviewed-on: https://review.coreboot.org/c/coreboot/+/72774 Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-03mb/google/rex: update touchscreen report EN pin settingIvy Jian
Removed workaround since the latest schematics fixed. Power Sequencing of ELAN6918 (in ACPI) after this patch `POWER enabled -> RESET deasserted -> Report EN enabled` BUG=b:247029304 TEST=Verified ELAN touch panel is working as expected after booting Google/rex device to ChromeOS. Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Change-Id: I19629262776f7e0cccbdebb2285890d177a8a8a6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72725 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-01-24mb/google/rex: Enable SaGvSubrata Banik
This patch overrides `SaGv` FSP-M UPD to enable SaGv feature to be able to train memory (DIMM) at different frequencies. On all latest Intel based platforms SaGv is expected to be enabled to support dynamic switching of memory operating frequency. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I7cf52b966c1355c1f2bd4ae7c256fa4252a90666 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72136 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
2023-01-19intel/meteorlake: remove skip_mbp_hob SOC chip configKapil Porwal
Introduce at new config option CONFIG_FSP_PUBLISH_MBP_HOB to control the creation of ME_BIOS_PAYLOAD_HOB (MBP HOB) by FSP. This new option is hooked with `SkipMbpHob` UPD and is always disabled for ChromeOS platforms. This made skip_mbp_hob SOC chip config variable redundant which is also removed as part of this change. BUG=none TEST=Build and boot to Google/Rex. Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: Iaba1ea29a92a63d2b287e1ccdea1a81ec07b9971 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71997 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-01-15drivers/i2c/generic: Drop 'disable_gpio_export_in_crs' flagMatt DeVillier
Exposing the GPIOs via an ACPI PowerResource and the _CRS results in the OS driver and ACPI thinking they own the GPIO. This can cause timing problems because it's not clear which system should be controlling the GPIO. Previously, we flagged as an error any device which set the 'has_power_resource' flag but did not set 'disable_gpio_export_in_crs.' There's no reason to require explicit disablement however, so drop the superfluous 'disable' flag, and change the _CRS generation to check if the GPIOs will be exported via the 'has_power_resource' flag instead. BUG=b:265055477 TEST=build/boot skyrim, dump SSDT and verify touchscreen GPIOs only listed under PRx, not under _CRS. Change-Id: I837ae6c6fe4b8e1c4e10686406cba06bdb7759d2 Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71849 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-01-04mb/google/rex: Configure EN_DMIC_SOC_DATA to GPO and LOWSubrata Banik
This patch configures GPP_H15 (EN_DMIC_SOC_DATA) as GPO and put into safe state aka LOW/PD. BUG=b:263411621 TEST=Able to build and boot Google, Rex to ChromeOS. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I3d376f895b2f0882c9fa6fe7b98686907bde4321 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71631 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-02mb/google/rex: Update USB2-C1 mappingSubrata Banik
This patch updates the USB2-C1 mapping from USB2 Port 4 to USB2 Port 1 as per latest Rex schematics dated 12/06/2022. TEST=Hardward awaited. Change-Id: Ifc82200e6eafcea7e820a96df81325f3c8849fd1 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70426 Reviewed-by: Eran Mitrani <mitrani@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-02mb/google/rex: Remove USB2_8 ConnectionSubrata Banik
DCI interface deprecated for Proto1. USB2_8 port becomes no-connect. BUG=b:263494661 TEST=Able to build and boot Google/Rex. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I6f03d600acd8ceaa5a5630fc19c1c7e34a4ea28f Reviewed-on: https://review.coreboot.org/c/coreboot/+/71237 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-02mb/google/rex: Revise config for the Proto 1 buildSubrata Banik
1. Rename DB_USB4 for KB8010 while adding ANX7452 as different DB_USB4 option. 2. Add audio component for Soundwire. 3. Rename MAX98357_ALC5682I_I2S to MAX98360_ALC5682I_I2S. Change-Id: I9f04c644b8a392feb2609f906bc9db945bf5fce2 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70867 Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: YH Lin <yueherngl@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-24mb/google/rex: Enable DPTF functionality for Rexzhaojohn
Enable DPTF functionality for Meteor Lake Rex board. BUG=b:262498724 TEST=Booted to OS and verified DPTF entries in ACPI SSDT on Rex board. Change-Id: I87b2d71650be9ce940d9452bf4a76d4cd1ddba52 Signed-off-by: zhaojohn <john.zhao@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70884 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-24mb/google/rex: Use GPP_C15 as WWAN_DPR_SAR_ODLSubrata Banik
BUG=b:263413949 TEST=Able to build and boot Google/Rex. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I453fe8e1f4b4b8d4730ade259899d76aec949a44 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71231 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2022-12-24mb/google/rex: Rename GPP_D07 to FPMCU_UWB_MUX_SELSubrata Banik
BUG=b:263412235 TEST=Able to build and boot Google/Rex. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ia444cc8e3666fe15479ece81d068f9e8f1d339ea Reviewed-on: https://review.coreboot.org/c/coreboot/+/71228 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2022-12-15mb/google/rex: Add support for WWAN over USB3Subrata Banik
This patch connects USB3_PCH_*_WWAN_* to USB32_2 as per Proto 1 schematics dated 12/14/2022. TEST=Able to build Google/Rex. Change-Id: Ie04c79ff5c231527e3d5f63a5cc553ec39c46914 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70749 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2022-12-15mb/google/rex: Modify the PIN name as per schematicsSubrata Banik
This patch updates the GPIO PIN name as per Proto 1 schematics dated 12/14/2022. TEST=Not code change, just updated the comment section. Change-Id: Ic076ab35689fd2afb7c18eff065a90b9464a6b1d Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70747 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2022-12-15mb/google/rex: Add RTD3 support for discrete wifi moduleKapil Porwal
BUG=none TEST=Build and boot to the OS on google/rex. Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: I2c5bac880e7dbc2ec14376c5cee3c13363bab377 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70444 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-10mb/google/rex: Implement S0ix hooks aka `MS0X` methodSubrata Banik
This patch ensures to be able to drive SYS_SLP_S0IX_L `low` based on the state of the system while `SLP_S0_L` signal is `low` (while the system is in S0ix). Implemented runtime ASL method (MS0X) being called by PEPD device _DSM to configure `SLP_S0_GATE (GPP_H14)` PIN at S0ix entry/exit. Scope (\_SB) { Method (MS0X, 1, Serialized) { If ((Arg0 == One)) { \_SB.PCI0.CTXS (0x75) } Else { \_SB.PCI0.STXS (0x75) } } BUG=b:256807255 TEST=Able to see SYS_SLP_S0IX_L goes low in S0ix. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ie6b5e066f228ea5dc79ae14dd803fc283fd248ce Reviewed-on: https://review.coreboot.org/c/coreboot/+/70196 Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-09mb/google/rex: Enable S0ixSubrata Banik
This patch enables S0ix for Google/Rex platform. BUG=b:256807255 TEST=Able to program FADT table Bit 21 (Low Power Idle S0) Change-Id: I79546267d29622c65321f7dfa29d3aac2fa59438 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70430 Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2022-12-08mb/google/rex: Add MPTS method for WWAN over PCIeSubrata Banik
This patch generates the following for the mainboard: Scope (\_SB) {         Method (MPTS, 1, Serialized)         {             Local0 = \_SB.PCI0.RP06.RTD3._STA ()             If ((Local0 == One))             {                 \_SB.PCI0.RP06.PXSX.DPTS (Arg0)             }         } } Change-Id: I27ade63cfe0586aee9f03ba816b2590f14dcb610 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70229 Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-03mb/google/rex: Add PCIe based SD controllerSubrata Banik
This patch adds PCIe based SD controller at RP 7 (from RP 11) with Proto 1 schematics dated 11/30. Additionally, added the RTD3 entries for the SD controller. Finally, ensured that EN_PP3300_SD (GPP_D03) is configured in bootblock and SD_PERST_L (GPP_D02) is configured in romstage to meet the power cycle requirement. BUG=b:242917011 TEST=Able to build and boot Google/Rex. SD card detection is due for the Proto 1 hardware. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I23d53e4d61ec36d2145f9e5816d97d13eb5b219e Reviewed-on: https://review.coreboot.org/c/coreboot/+/70064 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
2022-12-03mb/google/rex: Drop `board_id` check while configuring GPIOSubrata Banik
This patch drops the usage of reading `board_id()` while performing the GPIO configuration. The reason to drop the board_id check is to ensure that GPIO configuration for MLB (mainboard) would remain the same and the only GPIO PIN configuration that differs would be due to usage of having different DBs (daughter board) which will be taken care using CBI (and fw_config.c file) in coreboot. Additionally, drop unused early GPIO default configuration table. BUG=b:260804656 TEST=Able to perform the GPIO configuration and able to boot Google/Rex. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I96cafd1c904001cbf4199977e9e721afe5eab470 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70224 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2022-11-26mb/google/rex: Disable SATA from the devicetreeKapil Porwal
SATA is not supported on google/rex hence disable it. BUG=none TEST=Build and boot to google/rex. Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: I35a742ab9782feed86c3af514505d870d181b34b Reviewed-on: https://review.coreboot.org/c/coreboot/+/69973 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-11-25{drivers/wifi, mb/google}: Rename `is_untrusted` to `add_acpi_dma_property`Kapil Porwal
`is_untrusted` is eventually ended up by adding DMA property _DSD which is similar to what `add_acpi_dma_property` does for WWAN drivers, hence it makes sense to have a unified name across different device drivers. BUG=b:259716145 TEST=Verified that the _DSD object is still present in the SSDT. Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: I4e0829a76a193b0a1e1e0f2b7ce2119bb00dd696 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69937 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-24mb/google/rex: Adding cros_gpios to rexIvy Jian
Adding cros_gpios for crossystem to access WP GPIO BUG=b:258048687 TEST= run FAFT firmware_WriteProtect passed. Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Change-Id: Ieac1df805c6399aefdc13aae136630d496aacd58 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69924 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-19ec/google/chromeec: Remove EC_HOST_EVENT_USB_CHARGERCaveh Jalali
EC_HOST_EVENT_USB_CHARGER is no longer defined by the EC, so remove all references. BUG=b:216485035,b:258126464 BRANCH=none TEST=none Change-Id: I9e3e0e9b45385766343489ae2d8fc43fb0954923 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69374 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Jon Murphy <jpmurphy@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-11-17mb/google/rex: Add `disable_gpio_export_in_crs` for rexSubrata Banik
None of the touchscreens (over I2C) used in the rex program requires exporting GPIOs in the ACPI _CRS method. This can cause i2c devices to malfunction or cause timing sequence violations if ACPI exports a PowerResource for the device that uses GPIOs that are also exported in _CRS. BUG=none TEST=Able to build and boot Google, Rex platform. Without this patch: [ERROR] I2C: 00:10: Exposing GPIOs in Power Resource and _CRS With this patch: None Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I578a60eff27f94d6dc94b900604bc7560337d60b Reviewed-on: https://review.coreboot.org/c/coreboot/+/69612 Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-12mb/google/rex: Add Write Protect GPIO to cros_gpiosIvy Jian
This will enable crossystem to access WP GPIO BUG=b:258048687 TEST= wpsw_cur in crossystem reads the correct gpio Change-Id: I67f4a57025064dbf8c691255b0abae9d3fa0dbd3 Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69468 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-09mb/google/rex: Add fingerprint SPIEran Mitrani
Add Fingerprint SPI, and power-off FPMCU during romstage. For reference see CL:66915 for a similar change to Brya's power sequence SHA: 2b523ce6316e5c5ec86fe812d739fe48ca81d83d ("Invoke power cycle of FPMCU on startup") TEST=Tested on Rex - setup and logged in using fingerprint Change-Id: I4e6be24e72a8232ae2c958a01cf8ea9a272d7365 Signed-off-by: Eran Mitrani <mitrani@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66992 Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-11-04mb/google/rex: Enable RFIM for CNVizhaojohn
This patch enables the radio frequency interference mitigation for Rex. BUG=b:248391777 TEST=Booted to OS on Rex board. Verified RFIM DSM is presented to kernel through ACPI SSDT. Change-Id: I22f9861452c2c222dd7a33bfeb02c63b026bf2f7 Signed-off-by: zhaojohn <john.zhao@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67791 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-11-04mb/google/rex: Fix fw_config probe for UFC and WFCKapil Porwal
Fix fw_config probe for UFC and WFC. BUG=b:255971791 TEST=Build Google Rex. Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: I5103e7da04004414d96f42057c105cf9fbf51b25 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69152 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-11-02mb/google/rex: Disable TBT PCIe rp1 and rp3 root portszhaojohn
Rex board only uses TBT PCIe root ports 0 and 2. This change disables rp1 and rp3 root ports. BUG=b:254207628 TEST=Booted to OS and verified rp1 and rp3 root ports were disabled. Change-Id: Ia5c1d657c0ad0482619d739f8949bc9168eac25b Signed-off-by: zhaojohn <john.zhao@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68854 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2022-10-20mb/google/rex: Skip sending the MBP HOB to save boot timeWonkyu Kim
This change is to skip sending the MBP HOB since coreboot doesn't use it and also helps to reduce the boot time by ~40 ms. Boot time data Before: * 955:returning from FspSiliconInit 1,656,985 (274,416) After: * 955:returning from FspSiliconInit 1,593,036 (233,286) BUG=b:252410202 TEST=Verified that boot time is reduced by ~40 msec. Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Change-Id: I0d4f66940529b8d38d9658c769feba8b5c9b715e Reviewed-on: https://review.coreboot.org/c/coreboot/+/68418 Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2022-10-14mb/google/rex: Add initial fw configKapil Porwal
Add initial fw config as per config.star. BUG=b:253199788, b:245158908, b:244113761, b:244012065 TEST=emerge-rex coreboot. Make sure that ACPI tables are equivalent before and after this change with CBI.FW_CONFIG set to 0x1561. Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: I66f8b3e4ab414c03b8d63fdd31e0f3f424619340 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68220 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-14mb/google/rex: Implement WIFI SAR related changesSubrata Banik
1. Add CHROMEOS_WIFI_SAR to include the SAR configs. 2. Add get_wifi_sar_cbfs_file_name() that return the wifi SAR filename. BUG=none TEST=emerge-rex coreboot Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ia863eaa53c9456ae0e9f0e8914e0de497a32b53b Reviewed-on: https://review.coreboot.org/c/coreboot/+/68393 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2022-09-28mb/google/rex: Set up MIPI cameras via ACPIDaniel Kang
This patch adds ACPI configurations of 8MP YHUX and 2MP CJFKF28-1 as world- and user-facing cameras of Rex. BUG=b:246413264 TEST=Verified world- and user-facing cameras using Chrome Camera App on Google/rex device. Signed-off-by: Daniel Kang <daniel.h.kang@intel.com> Change-Id: Iaaa16e491a66500606b3a9eb1d87f396641778e0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67085 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2022-09-20mb/google/rex: Add WWAN ACPI supportIvy Jian
Add FM350GL 5G WWAN support using drivers/wwan/fm and additional PM features from RTD3. BUG=b:244077118 TEST=check cbmem -c \_SB.PCI0.RP06: Enable RTD3 for PCI: 00:1c.5 (Intel PCIe Runtime D3) \_SB.PCI0.RP06: Enable WWAN for PCI: 00:1c.5 (Fibocom FM-350-GL) check PXSX Device is generated in ssdt. Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Change-Id: I6114c589769d2eca882cf1a5255cf4c5937121a6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67336 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-09-19mb/google/rex: Add ELAN6918 touchscreenSubrata Banik
ELAN6918 Power Sequencing seems not perfectly matching with the previous platforms and setting GPP_C06 to high prior to the power sequencing is actually makes it work. Ideally Power Sequencing should be as below for ELAN6918 (in ACPI) `POWER enabled -> RESET deasserted -> Report EN enabled` But below sequence is only working currently: `Report EN enabled (ramstage) -> POWER enabled (ACPI) -> RESET deasserted (ACPI)` BUG=b:247029304 TEST=Verified ELAN touch panel is working as expected after booting Google/rex device to ChromeOS. Change-Id: Ideaeb0faa882b8e603534bbface51ea76923d436 Signed-off-by: Eran Mitrani <mitrani@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66990 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2022-09-14mb/google/rex: Add audio parts ALC5682I-VS and MAX98357Eran Mitrani
BUG=b:232573696 TEST=Able to verify audio playback on Google/Rex with this change. Change-Id: Ia8dfc79e7e4d27828726145156c870733d716899 Signed-off-by: Eran Mitrani <mitrani@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66919 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-10mb/google/rex: Complete several remaining GPIO configsTarun Tuli
Lists of GPIO PINS being updated: SPKR_INT_L_R RST_HP_L SOC_HDMI_HPD_L SOCHOT_ODL SOC_FPMCU_INT_L EN_PP3300_WLAN BUG=b:24410269 TEST=Build and boot Google/Rex to ChromeOS. Change-Id: If2fb354f931217c09a6c1c81ca780cb121b24468 Signed-off-by: Tarun Tuli <taruntuli@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67449 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-10mb/google/rex: Enable touchpadKapil Porwal
Enable touchpad for Google Rex. BUG=b:245866939 TEST=Build and boot to Google Rex. Verify touchpad works. Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: I49fdd72bf3350085e82411b95edcd6a9a09d2df5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67471 Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Shaunak Saha <shaunak.saha@intel.corp-partner.google.com>
2022-09-10mb/google/rex: Add GPE route for GPP_BKapil Porwal
Add GPE route for GPP_B. BUG=b:245866939 TEST=Build and boot to Google Rex. Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: I28066a6cc75908f8ceefbdbf8c088c56833606ea Reviewed-on: https://review.coreboot.org/c/coreboot/+/67469 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Shaunak Saha <shaunak.saha@intel.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-09-08mb/google/rex: Add WWAN poweron sequencingIvy Jian
The PCIe WWAN module used on rex requires control over 4 signals to successfully power it on. It is desirable to do this before passing control to the payload, because the modem requires a ~10 seconds initialization phase before it can be used. The corrected sequence looks like: 1) Drive device into full reset and enable power in bootblock 2) Deassert FCPO in romstage, after power rails stabilize 3) Deassert WWAN_RST#, then WWAN_PERST# in ramstage BUG=b:244077118 TEST=FM350 could be enumerated via lspci Measured signals to check start-up Timing Sequence, tpr/ton1/ton2. Tpr = 572mS Ton1 = 6.3s Ton2 = 6.3+4.17ms Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Change-Id: I6cda9348ef7f54efe5ba2358040596a1c2da1b13 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67332 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-04mb/google/rex: Correct GPSI0 muxing for pads requiring NF8Tarun Tuli
GSPI0 pads required muxing to NF8. Support for extended native functions was added in commit b6c32d7fe4ea98ba8b3a10cb5ce46448801855b8 BUG=b:244610269 TEST=build and booted on Rex Change-Id: Iab4e0bc6890cd8e976c513fe87dda0da9b5f2ee0 Signed-off-by: Tarun Tuli <taruntuli@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67317 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
2022-09-02mb/google/rex: Enable DSP UPDEric Lai
Enable DSP setting. Make sure the SSP can work as expected. BUG=b:243123156 TEST=Dev beep working on Rex. Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: I6ae28e414ac4ac33f596df57691c979eac5fe132 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67270 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2022-08-31mb/google/rex: Correct EC-is-trusted logicKapil Porwal
Fix EC_IN_RW config for Rex. Dauntless on Rex does not have an EC_IN_RW GPIO pin. Port of commit 7f339c6050c5 ("mb/google/corsola: Correct EC-is-trusted logic") BUG=b:243950850 TEST=Built and booted to Google Rex. Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: I97e5c752b4f36c9221137903f755837880f6b1c4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67208 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2022-08-30mb/google/rex: Change GPP_A17 programmingTarun Tuli
To match byra commit 7c2514fc072f95eed6483518811fb6c39f780f5b (mb/google/brya: Change GPP_F17 programming), update A17 pad configuration to the APIC only. TEST=Verified booting to OS on Google/Rex. Signed-off-by: Tarun Tuli <taruntuli@google.com> Change-Id: Ie9f071dc4a2755dd1f396e2afe730ead66bb1dd0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67183 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-26mb/google/rex: Add mapping for GPIO_PCH_WPTarun Tuli
The define GPIO_PCH_WP needs to be mapped to GPP_H10 based on the Rex schematics 24/6/2022. TEST=Built and booted on Google Rex. Signed-off-by: Tarun Tuli <taruntuli@google.com> Change-Id: I2489c244bd4cbd9e10ed3db981a6e56a954b5e20 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67083 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-26mb/google/rex: Add mapping for EC_SYNC_IRQTarun Tuli
The define EC_SYNC_IRQ needs to be mapped to A17 based on the Rex schematics 24/6/2022. BUG=b:243781237 TEST=Successfully build rex and tested to ensure EC is now functional. Signed-off-by: Tarun Tuli <taruntuli@google.com> Change-Id: Ib61ddc9f73dd7b817d3b990bef8f0169f7cafbcd Reviewed-on: https://review.coreboot.org/c/coreboot/+/67082 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2022-08-25mb/google/rex: Update DQS for RexTarun Tuli
Update the DQS for Rex as per the latest Rex schematics (08/25). BUG=b:243734885 TEST=Built successfully. Confirmed on HW. Change-Id: I2a458a3da725f953cbba8a194ac6f314f5467419 Signed-off-by: Tarun Tuli <taruntuli@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67041 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maulik Vaghela <maulikvaghela@google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-23 08:27:01 +0000