summaryrefslogtreecommitdiff
path: root/src/mainboard/google/rex/variants
AgeCommit message (Collapse)Author
2023-07-05soc/intel/meteorlake: Set TCC to 90°CSumeet Pawnikar
Set tcc_offset value to 20 in chipset for Thermal Control Circuit (TCC) activation feature for meteorlake silicon. Also, remove tcc_offset default value from rex baseboard and variants. BUG=b:270664854 BRANCH=None TEST=Build FW and test on rex board Change-Id: Ieec1b7e0873eef46a56e612ed1d9445019b1f4a9 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76232 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-07-05mb/google/rex/var/screebo: Update touchpad I2C timingZhongtian Wu
Change i2c[3] parameter to meet below timing: t-HIGH > 600ns; 900ns > Thd:dat > 300ns. BUG=b:286030723 BRANCH=none TEST=Test success by EE. Change-Id: I4b2d958a5a0d41e2cfa1087f5cb94cc83bbb1739 Signed-off-by: Zhongtian Wu <wuzhongtian@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76169 Reviewed-by: Kun Liu <liukun11@huaqin.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-05mb/google/rex/var/ovis: Set TCC to 100°CSubrata Banik
Set tcc_offset value to 10 in devicetree for Thermal Control Circuit (TCC) activation feature for ovis. BUG=b:270664854 TEST=Build and boot google/ovis. Change-Id: I0ef626f6cc460f1b460297804b97038705efaf4c Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76230 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-07-05mb/google/rex/var/ovis: Add Power Limit for 28WSubrata Banik
This patch adds a power limit for Ovis with 28W Intel Meteor Lake silicon. Reference: Intel MTL-UH_Power_Map_Rev1p2, doc: 640982 BUG=b:289854108 TEST=Able to boot google/ovis with power limit being overridden as appropriate to 28W. Change-Id: I312c70720fd89261c53d5bd4f45236e829d6c790 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76229 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2023-07-05mb/google/rex/var/screebo: Update touchscreen I2C timingZhongtian Wu
Change i2c[0] parameter to meet touchscreen timing. Thd:dat > 100ns. BUG=b:287898252 BRANCH=none TEST=Test success by EE. Change-Id: I30e7c87d788f7f144276c45e8475af65f1f132ae Signed-off-by: Zhongtian Wu <wuzhongtian@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76190 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Kun Liu <liukun11@huaqin.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-07-04mb/google/rex: Enable Bluetooth offload for soundwire audioUday M Bhat
This patch enables BT offload feature for soundwire audio over SSP1. BT mode is selected via FW_CONFIG and corresponding VGPIOs are programmed. BUG=b:275538390 TEST=build and verify BT offload on rex soundwire audio Change-Id: I99df78787d9f54c91bcedf6f70352890a715cdb3 Signed-off-by: Uday M Bhat <uday.m.bhat@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75924 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-07-03mb/google/rex: Set AUX orientation at SoC to follow cable for kb8010Caveh Jalali
This configures the SoC to flip the orientation of the AUX pins to follow the orientation of the cable when using the kb8010 retimer. This is necessary when there is no external retimer/mux or the retimer/mux does not implement the flip. The kb8010 retimer does not support this feature, so let the SoC do the flip. BUG=b:267589112 TEST=verified DP-ALT mode works in both cable orientations on rex with reworked kb8010 DB by flykt@ Change-Id: Iad093e27617b80f8301008deb00b57fb9b3a48ba Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76137 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-07-02mb/google/rex/var/ovis: Enable LAN0Subrata Banik
This patch performs below operations to enable LAN0. - Complete the LAN PEREST power sequencing - Program the SRC_CLKREQ (GPP_D20) with correctly. - Add overridetree.cb entry to configure the LAN0 device. BUG=b:289395519 TEST=Able to boot google/ovis with LAN0 being enabled. Change-Id: I91b0a76395ade4459cf8705c333728a71f95df14 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76213 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-02mb/google/rex/var/ovis: Enable LAN1Subrata Banik
This patch performs below operations to enable LAN1. - Add overridetree.cb entry to configure the LAN device. - Complete the LAN1/SD PEREST power sequencing BUG=b:289395519 TEST=Able to boot google/ovis with LAN1 being enabled. Change-Id: Ifb67cb8e6fc03e3ff14b1b3d8382322fd0b3aeff Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76212 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-02mb/google/rex/var/ovis: Configure GPP_V12 PADSubrata Banik
This patch configures GPP_V12 aka SOC_SLP_LAN_L properly as per the Ovis schematics dated June'23 to ensure LAN port is not in sleep. BUG=b:289395519 TEST=Able to measure SLP_LAN PIN and confirm it's deasserted. Change-Id: I1fe8715862823149c8a1f05e3e4463a615fbbbce Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76211 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-02mb/google/rex/var/ovis: Configure GPP_C10 PADSubrata Banik
This patch configures GPP_C10 aka EN_LAN_RAILS properly as per the Ovis schematics dated June'23 to ensure LAN ports having power. BUG=b:289395519 TEST=Able to measure LAN port power is enabled with this CL. Change-Id: I3f4d611313325dba66905e0c8ef391765a1fe7a7 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76210 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-06-30mb/google/rex/var/ovis: Fix mux change as per schematicsSubrata Banik
This patch updates the mux connection to reflect the Ovis schematics dated June to ensure Type-C1 is able to work in DP-ALT mode. BUG=b:289300284 TEST=Able to get display over Type-C1 port. Change-Id: I223eb3a96e6a1b3abb4168fcf59c0df04c1b4498 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76149 Reviewed-by: Jakub Czapiga <jacz@semihalf.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2023-06-28mb/google/rex/var/ovis: Enable crashlog and IOE dieJakub Czapiga
BUG=b:262501347 TEST=Boot on Ovis board. Change-Id: I43aac857e3ec7989c9ab5201cd8f24a7c877e76b Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76151 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-06-28mb/google/rex: Avoid boot hang due to missing SOC/IOE SRAM deviceSubrata Banik
The SOC/IOE SRAM device is used to store crash logs. Previously, the crashlog enablement was hardcoded in the baseboard.common module. This commit moves the crashlog enablement logic to the baseboard module, so that it can be enabled or disabled based on the specific baseboard. Additionally, the SOC/IOE SRAM is now enabled by default in the baseboard devicetree.cb file. This prevents the system from hanging if the SOC/IOE SRAM device is not present. BUG=b:262501347 TEST=Able to build and boot google/screebo with this patch. w/o this patch: [ERROR]  SOC SRAM device not found! [ERROR]  IOE SRAM base not valid Change-Id: I02d581e5b62cfa114a3761a9704ad9f24dead8aa Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76134 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-06-28mb/google/rex/var/ovis: Enable SaGvSubrata Banik
This patch enables SaGv with fixed frequency and gears for Ovis. Restrict memory speed to 6400 MTS as per board design. BUG=b:282164577 TEST=Verified the settings on google/ovis using debug FSP logs Change-Id: Ia9703344a8ae9d2ba44a16c62afab820fd8e2177 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76138 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-28mb/google/rex: Set TCC to 90°CSumeet Pawnikar
Set tcc_offset value to 20 in devicetree for Thermal Control Circuit (TCC) activation feature for rex variants. BUG=b:270664854 BRANCH=None TEST=Build FW and test on rex board Change-Id: I0567b6240fcb53f38158c381b700169475cf3795 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76110 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-06-26mainboard/google/rex: Enable crashlogPratikkumar Prajapati
Enable crashlog for rex. Select config options SOC_INTEL_CRASHLOG, and SOC_INTEL_IOE_DIE_SUPPORT. Also enable ioe_shared_sram and pmc_shared_sram devices. BUG=b:262501347 TEST=Able to trigger Crashlog, BERT table gets generated and decodes as expected. Change-Id: I3d3a9fb41d1293f021ad9de9b29c756cb7559373 Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74770 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-06-26mb/google/rex: Avoid LPDDR5/x hangSubrata Banik
This patch avoids random hang issue observed after booted to OS on LPDD5/x platforms due to CLK not tuned properly in SAGV point 0, 2133MT/s. As per Intel doc 769410 the expected work around is to change SAGV point 0 from 2133 G4 to 3200 G4. BUG=b:287170545 TEST=Able to perform 500 power cycles on google/rex without any hang. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I02a9cadc075f396549703d7a008382e76268f865 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76076 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-23mb/google/rex: Configure ISH GPIO's based on FW_CONFIGBernardo Perez Priego
Configures ISH related GPIO's based on FW_CONFIG obtained from CBI. BUG=b:280329972,b:283023296 TEST= Set bit 21 of FW_CONFIG with CBI Boot rex board Check that ISH is enabled, loaded, and functional Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com> Change-Id: I3f0f9a7c8318fa9ae59b6f613eafdacbfa07c749 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75525 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-06-23soc/intel/meteorlake: Rename shared SRAM aliasesPratikkumar Prajapati
Rename shared SRAM aliases for IOE and PMC to make them more readable. pci device 13.3 is IOE shared sram, renamed to ioe_shared_sram. pci device 14.2 is PMC shared sram, renamed to pmc_shared_sram. Rename them in SOC code as well as mainboard to make sure the patch builds for the relevant boards. BUG=b:262501347 TEST=Able to build. Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati@intel.com> Change-Id: I02a8cacc075f396549703d7a008382e76258f865 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75999 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-23mb/google/rex: Keep CNVi PCI device enabled for OvisSubrata Banik
The CNVi PCI device is required for the system to boot properly. By ensuring that this device is enabled, we can prevent the below error message from appearing and ensure that the system boots successfully. BUG=b:274421383 TEST=Able to build and boot google/ovis without any error. w/o this patch: [ERROR] CNVi WiFi is enabled without CNVi being enabled [ERROR] CNVi BT is enabled without CNVi being enabled Change-Id: I4dbae14f0cfccf96a33437a0e2fdefb508209354 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76001 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
2023-06-21mb/google/rex/var/screebo: set HBR smbus pin as NCSimon Zhou
Since GPP_C03/GPP_04 are floating in HW design, we set HBR smbus pin as NC, in case it prevents ese and cse from entering suspend. BUG=b:283053968 TEST=Verified on screebo non-TBT SKU, suspend and resume works. Change-Id: I401db32f0286de61ce3ab6c61de9528ec76cb51d Signed-off-by: Simon Zhou <zhouguohui@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75643 Reviewed-by: Kun Liu <liukun11@huaqin.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-21mb/google/rex: Fix PLD for USB type-A portKapil Porwal
USB type-A port with same PLD.token information as USB type-C port, causes conflict while generating ACPI code for the EC CONN device. Use a different PLD.token number for type-A port to fix the issue. BUG=b:286328285 TEST=check ACPI can have right USB port in EC CON. before patch: Package (0x02) { "usb2-port", \_SB.PCI0.XHCI.RHUB.HS01 }, Package (0x02) { "usb3-port", \_SB.PCI0.TXHC.RHUB.SS01 }, after patch: Package (0x02) { "usb2-port", \_SB.PCI0.XHCI.RHUB.HS01 }, Package (0x02) { "usb3-port", \_SB.PCI0.TXHC.RHUB.SS03 }, Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: If3e76c11dd6808eee4c9c2f3f71604a60379b5a5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75911 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2023-06-20mb/google/rex/var/rex0: Configure I2C timing for I2C devicesIvy Jian
Configure I2C0/1/3/4 timing in devicetree to ensure I2C devices meet timing requirement. Note that I2C5 timing will be updated separately when the tuning done BUG=b:280559903 TEST=Build and check I2C devices timing meet spec. | | I2C0-Codec | I2C0-WFC | I2C1 | I2C3 | I2C4 | |-------------|------------|----------|--------|-------|---------| | FSMB(KHz) | 347 | 343.2 | 389.3 | 393.7 | 381.9 | | TLOW(us) | 2.1 | 2.093 | 1.895 | 1.902 | 1.953 | | THIGH(us) | 0.647 | 0.628 | 0.602 | 0.62 | 0.612 | | THD:STA(us) | 0.633 | 0.64 | 0.601 | 0.6 | 0.601 | | TSU:STA(us) | 0.617 | 0.621 | 0.619 | 0.659 | 0.61 | | TSU:STO(us) | 0.656 | 0.647 | 0.667 | 0.727 | 0.634 | | TBUF(us) | 86.15 | >14.088 | >9.833 | >8 | >10.366 | Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Change-Id: I5421e4fe68e856bbe9f19544954a94670c895a47 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75150 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2023-06-20mb/google/rex/var/screebo: Remove rp2 and add rp1/rp3Rui Zhou
Remove rp2 and add rp1/rp3 for screebo BUG=b:286187816 BRANCH=none TEST=emerge-rex coreboot and verify TBT works. Change-Id: I1013d26c705f2a3f9378d944bd863d94f319d36c Signed-off-by: Rui Zhou <zhourui@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75832 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Simon Zhou <zhouguohui@huaqin.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-18mb/google/rex/variants/ovis: Add display configurationJakub Czapiga
Enable DDI on ports 1 to 4 for Type-C DisplayPort. BUG=b:274421383 TEST=util/abuild/abuild -p none -t google/rex -x -a -b ovis Change-Id: I40f967b12b11c10a1a9329bfb42ebec5a8d7738f Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75579 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-17mb/google/rex: Set AUX orientation at SoC to follow cable for anx7452Caveh Jalali
This configures the SoC to flip the orientation of the AUX pins to follow the orientation of the cable when using the anx7452 retimer. This is necessary when there is no external retimer/mux or the retimer/mux does not implement the flip. The anx7452 retimer does not appear to support this feature, so let the SoC do the flip. BUG=b:267589042,b:281006910 TEST=verified DP-ALT mode works on rex using both cable orientations Change-Id: Ibb9f442d2afd81fb5dde4bca97c15457837f9f4a Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75827 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2023-06-17soc/intel/meteorlake: Update tcss_usb3 aliasEric Lai
TCSS and TBT use the same lane on schematic. Update the port start from 0 to match the Intel schematic. You can better follow the it without convert the port number. Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: Ic6631dcbbd9f6c79c756b015425e2da778eb395e Reviewed-on: https://review.coreboot.org/c/coreboot/+/75892 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-06-15mb/google/rex: Enable audio BT offloadRavi Sarawadi
This patch enables BT offload feature on Rex over SSP1. BT mode is selected via FW_CONFIG and corresponding VGPIOs are programmed. BUG=b:275538390 TEST=Verified audio playback using BT speaker/headset in I2S mode on google/rex. Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Change-Id: I46e9702add37464122ffc78826ebf8a6c5b5b07c Reviewed-on: https://review.coreboot.org/c/coreboot/+/72881 Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-14mb/google/rex/var/rex0: add HID over SPI ACPI driverEran Mitrani
Add driver to support ELAN touchscreen using SPI for rex * See "HID Over SPI Protocol Specification" section 5.2 - ACPI enum * https://www.microsoft.com/en-us/download/details.aspx?id=103325 BUG=b:278783755 TEST=Kernel driver is able to communicate with device. Also tested S0ix, ran 'suspend_stress_test -c 1' - no issues in suspend/resume. Signed-off-by: Eran Mitrani <mitrani@google.com> Change-Id: Id51d385ce350cef23da4184b044c74569f4dd3f0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74885 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-06-14mb/google/rex/variants/ovis: Add basic DTTJakub Czapiga
Add default Intel DPTF. BUG=b:274421383 TEST=util/abuild/abuild -p none -t google/rex -x -a -b ovis Change-Id: Ib023f6d6d184f6935a6a454250755502a46b707f Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75580 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-06-14mb/google/rex/variants/ovis: Add USB and TCSS configurationJakub Czapiga
+-------------+----------------+------------+---------------------------------+ | PCH USB 2.0 | Connector Type | OC Mapping | Remarks | +-------------+----------------+------------+---------------------------------+ | 1 | Type-C | OC_0 | Type C port - TCP1 | | 2 | Type-C | OC_0 | Type C port - TCP0 | | 3 | Type-C | OC_0 | Type C port - TCP2 | | 4 | Type-A | OC_3 | USB3.2 Gen2x1 Type-A Port – TAP0| | 7 | Type-A | OC_3 | TAP1 | | 8 | Type-A | OC_3 | TAP2 | | 9 | Type-A | OC_3 | TAP3 | +-------------+----------------+------------+---------------------------------+ +---------------------+-------------------+------------+---------+ | PCH USB 3.1 Gen 2x1 | Connector Details | OC Mapping | Remarks | +---------------------+-------------------+------------+---------+ | 1 | Type-A | OC_3 | TAP0 | | 2 | Type-A | OC_3 | TAP1 | +---------------------+-------------------+------------+---------+ +------+-------------------+------------+-----------------------------+ | TCPx | Connector Details | OC Mapping | Remarks | +------+-------------------+------------+-----------------------------+ | 1 | Type C port 0 | OC_0 | To onboard Type-C connector | | 2 | Type C port 1 | OC_0 | To onboard Type-C connector | | 3 | Type C port 2 | OC_0 | To onboard Type-C connector | +------+-------------------+------------+-----------------------------+ BUG=b:274421383 TEST=util/abuild/abuild -p none -t google/rex -x -a -b ovis Change-Id: Icc81f12ec6cc4af37bcc1fcf3164cbfa5612a443 Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75578 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-06-12mb/google/rex/var/screebo: Enable touchscreenZhongtian Wu
Enable ILI2901 and eKTH7B18 touchscreen for Google Screebo. BUG=b:278167967 BRANCH=none TEST=Build and boot to Google Screebo. Verify touchscreen works. Change-Id: I57d55c5f2621d6fafd53b19d12ecad20271cdbb1 Signed-off-by: Zhongtian Wu <wuzhongtian@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75692 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Rui Zhou <zhourui@huaqin.corp-partner.google.com>
2023-06-12mb/google/rex/variants/ovis: Enable EC in device treeJakub Czapiga
BUG=b:274421383 TEST=util/abuild/abuild -p none -t google/rex -x -a -b ovis Change-Id: I6f3fa6543a4cec8c2562196105f17fbc7831bab7 Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75577 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-06-07mb/google/rex/variants/ovis: Add SSD card configJakub Czapiga
BUG=b:274421383 TEST=util/abuild/abuild -p none -t google/rex -x -a -b ovis Change-Id: I3795313e784595ac02ee2a38f466bcb9e613a6a4 Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75576 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Jan Dabros <dabros@google.com>
2023-06-07mb/google/rex/variants/ovis: Add I2C configJakub Czapiga
BUG=b:274421383 TEST=util/abuild/abuild -p none -t google/rex -x -a -b ovis Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Change-Id: I1644b1d8f49accbb2ea68e236534df80a5151360 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75503 Reviewed-by: Jan Dabros <dabros@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-06-07mb/google/rex/variants/ovis: Add GPIO configurationJakub Czapiga
Based on Platform Mapping Document for Ovis (go/ovis_mapping_doc) state for June 6, 2023 (Rev 0.3) BUG=b:274421383 TEST=util/abuild/abuild -p none -t google/rex -x -a -b ovis Change-Id: Iae3ca243a245928e8ec3d48877cf578843922fc7 Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75502 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-06mb/google/rex/var/rex0: Add new GFX devices with custom _PLDWon Chung
Add new GFX devices for DDI and TCP with custom _PLD to describe the corresponding ports. BUG=b:277629750 TEST=emerge-rex coreboot Signed-off-by: Won Chung <wonchung@google.com> Change-Id: I193b95e8bd8ae538c4f25fbe772b174ef455d744 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74367 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-06-06mb/google/rex/variants/ovis: Add RAM IDsJakub Czapiga
BUG=b:274421383 TEST=util/abuild/abuild -p none -t google/rex -x -a -b ovis Change-Id: Ic555fac846ebf1e9dad81b5847334c03d6804b5b Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75501 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-06-06mb/google/rex: Create ovis variantJakub Czapiga
BUG=b:274421383 TEST=util/abuild/abuild -p none -t google/rex -x -a ; Make sure GOOGLE_OVIS built successfully Change-Id: I5c8f290cfdcb4d47c0e5e9d72c1e34073b957681 Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75385 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-06mb/google/rex/var/rex0: probe for i2c1 touchscreenEran Mitrani
Touchscreen may either use I2C1 or SPI0. FW_CONFIG.TOUCHSCREEN is set to determine which is used. This CL adds a probe to enable I2C1. BUG=b:278783755 TEST=Tested on rex, confimed i2c1 is disabled when TOUCHSCREEN != TOUCHSCREEN_I2C Signed-off-by: Eran Mitrani <mitrani@google.com> Change-Id: I0bee176298fddd2aee35cf084db037a3ce7672f7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75565 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-06-04mb/google/rex: add macro for touchscreen IRQEran Mitrani
BUG=b:278783755 Signed-off-by: Eran Mitrani <mitrani@google.com> Change-Id: I2a6de778c7ab30a9946e100cb70c092ba98496e3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74944 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-04mb/google/rex: Enable ISH supportBernardo Perez Priego
Enable ISH based on FW_CONFIG obtained from EC CBI. This is useful in case device is a tablet and motion sensors are handled by ISH instead of EC. BUG=b:280329972,b:283023296 TEST= Set bit 21 of FW_CONFIG with CBI Boot rex board Check that ISH is enabled and loaded Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com> Change-Id: Ibe0e1b8ce2c9b08ac6b1e6fef9bd19afc9b4f59f Reviewed-on: https://review.coreboot.org/c/coreboot/+/75039 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-04mb/google/rex,screebo: Update GPIO PAD IO Standby StateBora Guvendik
Fix for the "Onboard Keyboard and Type-C ports are not working after resuming from powerd_dbus_suspend" issue. This issue was caused since FSP 3165 FSP was fixed and started skipping GpioConfigureIoStandbyState programming when GpioOverride UPD is enabled. This patch moves the IO Standby State programming that FSP was doing to coreboot. BUG=b:284264580 TEST=Boot to OS, compare gpio pins, verify keyboard / Type-C Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Change-Id: If96c1e71fdde784a55fe079875915ffa5a4f548a Reviewed-on: https://review.coreboot.org/c/coreboot/+/75555 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-04mb/google/rex/var/screebo: Add devicetree for support audioRui Zhou
Add devicetree config for ALC1019_ALC5682I_I2S BUG=b:278169268 TEST=emerge-rex coreboot and verified on screebo Change-Id: I2814cc76aff43daf0353cfef41592591bbe3d213 Signed-off-by: Rui Zhou <zhourui@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75575 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Simon Zhou <zhouguohui@huaqin.corp-partner.google.com> Reviewed-by: Mac Chiang <mac.chiang@intel.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-06-03mb/google/rex: Create karis variantTyler Wang
Create the karis variant of the rex0 reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0.) BUG=b:285195072 TEST=util/abuild/abuild -p none -t google/rex -x -a make sure the build includes GOOGLE_KARIS Change-Id: I16d8b43390401789b87a6233238e37f32a17b46b Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75551 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-06-02mb/google/rex/variants/screebo: add FW_CONFIG for audio/DBSimon Zhou
This patch adds FW_CONFIG to accommodate different Screebo BOM components across various SKUs. 1. DB_CONFIG for DB_TPEC/DB_TBT/DB_UNKOWN 2. AUDIO for ALC1019_ALC5682I_I2S/AUDIO_UNKNOWN BUG=b:278169268 TEST=build pass Change-Id: I928aae61d4936509a7b68f4041c0cd72f298e83d Signed-off-by: Simon Zhou <zhouguohui@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75573 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: YH Lin <yueherngl@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Mac Chiang <mac.chiang@intel.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-05-31mb/google/rex/var/screebo: Add MIPI camera devicejason.z.chen
Enabling MIPI UCAM for screebo project BUG=b:277883010 TEST=none Signed-off-by: jason.z.chen <jason.z.chen@intel.corp-partner.google.com> Change-Id: Id06e5c162d911a4bd78190757c25e7f760160a8f Reviewed-on: https://review.coreboot.org/c/coreboot/+/75157 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Haikun Zhou <zhouhaikun5@huaqin.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-05-31mb/google/rex/var/screebo: Set TCC to 90°CWentao Qin
Set tcc_offset value to 20 in devicetree for Thermal Control Circuit (TCC) activation feature for proto phase. BUG=b:282865187 BRANCH=None TEST=Build FW and test on Screebo board Change-Id: I3a929aa20a700376d2a0a150911fed34e67f78eb Signed-off-by: Wentao Qin <qinwentao@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75360 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Haikun Zhou <zhouhaikun5@huaqin.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-31mb/google/rex: Enable SoundWire codecsKapil Porwal
Enable drivers for SoundWire codecs and define the topology in the devicetree for the rex0 variant with the SoundWire daughter board connected. +------------------+ +--------------------+ | | | Headphone Codec | | Intel Meteor Lake| +--->|Cirrus Logic CS42L42| | SoundWire | | | ID 0 | | Controller | | +--------------------+ | | | | Link 0 +----+ +-------------------+ | | | Left Speaker Amp | | Link 1 | +--->| Maxim MAX98363 | | | | | ID 0 | | Link 2 +----| +-------------------+ | | | | Link 3 | | +-------------------+ | | | | Right Speaker Amp | +------------------+ +--->| Maxim MAX98363 | | ID 1 | +-------------------+ This was tested by booting the firmware and dumping the SSDT table to ensure that all SoundWire ACPI devices are created as expected with the properties that are defined in coreboot under \_SB.PCI0: HDAS - Intel Meteor Lake HDA PCI device HDAS.SNDW - Intel Meteor Lake SoundWire Controller HDAS.SNDW.SW00 - Cirrus Logic CS42L42 - Headphone Codec HDAS.SNDW.SW20 - Maxim MAX98363 - Left Speaker Amp HDAS.SNDW.SW21 - Maxim MAX98363 - Right Speaker Amp BUG=b:269497731 TEST=Verified SSDT for SNDW in the OS. Playback and recording are also validated on google/rex. Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: I3e11dc642ff686ba7da23ed76332f7f10e60fade Reviewed-on: https://review.coreboot.org/c/coreboot/+/73280 Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-29mb/google/rex: Update GPIO PAD as per Proto 2 schematicsSubrata Banik
BUG=b:283477280 TEST=Able to build and boot google/rex as per Proto 2 schematics dated 05/16. +-----------------+------------------------------------+---------------------------+--------+ | GPIO | In Proto 1 | In Proto 2 | Impact | +-----------------+------------------------------------+---------------------------+--------+ | GPP_C01 | SOC_TCHSCR_RST_L | SOC_TCHSCR_RST_R_L | N | +-----------------+------------------------------------+---------------------------+--------+ | GPP_D19 | NC | EC_SOC_REC_SWITCH_ODL | Y | +-----------------+------------------------------------+---------------------------+--------+ | GPP_E04 | HPS_INT_L | SOC_PEN_DETECT | N | +-----------------+------------------------------------+---------------------------+--------+ | GPP_E17 | EN_HPS_PWR | EN_PP3300_SPARE_X | N | +-----------------+------------------------------------+---------------------------+--------+ | GPP_F13 | GSPI1_SOC_MISO | GSPI1_SOC_MISO_R | N | +-----------------+------------------------------------+---------------------------+--------+ | GPP_F21 | GPIO_F21_SPI_CS_L | SPI_SOC_CS_UWB_L_STRAP | N | +-----------------+------------------------------------+---------------------------+--------+ | GPP_H00 | GPIO_H00_SPI_CLK_R | SPI_SOC_CLK_UWB_STRAP_R | N | +-----------------+------------------------------------+---------------------------+--------+ | GPP_H01 | GPIO_H01_SPI_MOSI_R | SPI_SOC_DO_UWB_DI_STRAP_R | N | +-----------------+------------------------------------+---------------------------+--------+ | GPP_H02 | GPIO_H02_SPI_MISO | SPI_SOC_DI_UWB_DO_STRAP | N | +-----------------+------------------------------------+---------------------------+--------+ | GPP_S00 | UNNAMED_8_METEORLAKEU_I137_GPPS00 | SDW_HP_CLK_WLAN_PCM_CLK | N | +-----------------+------------------------------------+---------------------------+--------+ | GPP_S01 | UNNAMED_8_METEORLAKEU_I137_GPPS01 | SDW_HP_DATA_WLAN_PCM_SYNC | N | +-----------------+------------------------------------+---------------------------+--------+ | GPP_S02 | UNNAMED_8_METEORLAKEU_I137_GPPS02 | DMIC_SOC_CLK0_WLAN_PCM_OUT| N | +-----------------+------------------------------------+---------------------------+--------+ | GPP_S03 | UNNAMED_8_METEORLAKEU_I137_GPPS03 | DMIC_SOC_DATA0_WLAN_PCM_IN| N | +-----------------+------------------------------------+---------------------------+--------+ Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I4a8c43b0f845d3446188b7c926e482f91e5b45aa Reviewed-on: https://review.coreboot.org/c/coreboot/+/75407 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-05-26mb/google/rex/variants/baseboard/rex: Add CPU power limit valuesSumeet Pawnikar
Add support of variant_devtree_update() function to override devtree settings for variant boards. Also, add CPU power limit values for rex baseboard. BRANCH=None BUG=b:270664854 TEST=Built and verified power limit values as below log message for 15W SKU on Rex board. Overriding power limits PL1 (mW) (10000, 15000) PL2 (mW) (57000, 57000) PL4 (W) (114) Change-Id: If46445157358e3e0f227e26a35b4303fc9189a4b Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74754 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Harsha B R <harsha.b.r@intel.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-05-26mb/google/rex: Set frequency and gears for SaGv pointsBora Guvendik
Restrict memory speed to 6400 MTS as per board design. BUG=b:282164577 TEST=Verified the settings on google/rex using debug FSP logs. Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Change-Id: I3dec383c7c585b80a73089f3403011c5cda61f65 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75291 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-05-26mb/google/rex/var/screebo: Enable touchpadZhongtian Wu
Enable touchpad for Google Screebo. BUG=b:278160238 BRANCH=none TEST=Build and boot to Google Screebo. Verify touchpad works. Change-Id: Ib83e5ef5ca497592f5a26aa1e85d793d06d9dd7f Signed-off-by: Zhongtian Wu <wuzhongtian@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75412 Reviewed-by: Kun Liu <liukun11@huaqin.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-05-25mb/google/rex: Enable SaGvSubrata Banik
This patch overrides `SaGv` FSP-M UPD to enable SaGv feature to be able to train memory (DIMM) at different frequencies. On all latest Intel based platforms SaGv is expected to be enabled to support dynamic switching of memory operating frequency. BUG=b:267879107 TEST=Able to verify SaGv is enabled with 3 work point (0, 1 and 2) and MRC retraining takes around ~20ms extra compared to SaGv being disabled. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ic680bfeab4dd285c0d3916ba5e917cc12bae3284 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73534 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-24mb/google/Screebo: Enable AUX DC biasing on C0Simon Zhou
SKU1A C0 has no redriver, so enable SBU muxing in the SoC. BUG=b:283044004 BRANCH=none TEST=Voltages are correct on the C0 and C1 AUX bias pins Change-Id: I18b4ade2c60c270855fb2e733a9201539e08d8ba Signed-off-by: mike <mike5@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75381 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-05-24mb/google/rex/var/screebo: Add BT devicetree configqinwentao
Enabling BT for screebo project BUG=b:278169273 TEST=Check whether BT can connect to Bluetooth device Signed-off-by: qinwentao <qinwentao@huaqin.corp-partner.google.com> Change-Id: I0ecd62abfbe751e1036948b1490844e7e63d7f0d Signed-off-by: qinwentao <qinwentao@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75352 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kun Liu <liukun11@huaqin.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-05-23mb/google/rex: Add FW_CONFIG and device for VPUEran Mitrani
BUG=b:282912666 TEST=set and unset bit20 in HW_CONFIG and check if VPU(0b.0) is enabled when bit20 is set, and disabled when cleared Signed-off-by: Eran Mitrani <mitrani@google.com> Change-Id: Iee6a9026a4d210407350bfb7ecc8a058e7ff5c24 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75303 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-05-23mb/google/rex: Add FW_CONFIG for TOUCH over SPIEran Mitrani
TEST=set the corresponding cbi bit, and saw SPI0 under sysfs BUG=b:278783755 Signed-off-by: Eran Mitrani <mitrani@google.com> Change-Id: I7099cde14cff90ad63e9164769f9913a8284a805 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74888 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-05-22mb/google/rex/var/screebo: enable fingerprintSimon Zhou
BUG=b:278156430 TEST=verify the fingerprint on screebo Change-Id: I986e470b28145f7b17427e794055929a4283c721 Signed-off-by: Simon Zhou <zhouguohui@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75287 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dolan Liu <liuyong5@huaqin.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-05-19mb/google/rex: Enable stylus supportDinesh Gehlot
This patch enables stylus support by configuring the "GPP_D08" irqs for rex SoC. This allows the SoC to detect a stylus device, when in use. However stylus is not a wake up source for the rex. BUG=b:282256460 Test=Stylus is detected on proto1 device. Signed-off-by: Dinesh Gehlot <digehlot@google.com> Change-Id: I84a71aa664698e105b738f8680d0a4751ca1fc72 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71820 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-05-14mb/google/rex: Add variant specific SOC chip config update functionAnil Kumar
This patch adds support for variant specific chip config update similar to commit 061a93f93d2 ("mb/google/brya: Add variant specific soc chip config update"). Signed-off-by: Anil Kumar <anil.kumar.k@intel.com> Change-Id: I60a4042cba608fd527527af9340ec0215f3086ca Reviewed-on: https://review.coreboot.org/c/coreboot/+/75046 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-05-14mb/google/rex/var/screebo: Add initial devicetree configKun Liu
add initial devicetree config for screebo BUG=b:276814951 TEST=emerge-rex coreboot Change-Id: Ie64d0e50ec22b3e363597af64eb723ef1f86dfa8 Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74972 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-05-14screebo: fix the lp5ccc config from 0x55 to 0xaaSimon Zhou
BUG=b:278022971 TEST=verified on screebo Change-Id: I16f1d66ca7f885120358eb2a2d3c6fb111319f11 Signed-off-by: Simon Zhou <zhouguohui@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75173 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-12mb/google/rex: Set WWAN_RF_DISABLE_ODL to NCTarun Tuli
This signal isn't functionally being used and is causing leakage during suspend. Set it to NC. BUG=b:279762779 TEST=builds. WWAN functional. Change-Id: I93f2b0a781e250678280b57e4ab1d80ef27ff460 Signed-off-by: Tarun Tuli <taruntuli@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75053 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-05-08mb/google/rex/var/rex0: Correct _PLD values for USB C0Won Chung
Denote the correct value of ACPI _PLD for USB ports. The horizontal position of port C0 is incorrectly labelled. +----------------+ | | | Screen | | | +----------------+ C0 | | A0 | | C1 | | +----------------+ BUG=b:216490477 TEST=emerg-rex coreboot Signed-off-by: Won Chung <wonchung@google.com> Change-Id: Id9ed435ca0af131e3bb4538701fc97d78146899f Reviewed-on: https://review.coreboot.org/c/coreboot/+/74366 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-06mb/google/rex/var/screebo: Add DDR DQ map configKun Liu
Add DDR DQ map config for screebo BUG=b:276814951,b:272218757 TEST=emerge-rex coreboot Change-Id: I993ae4024689b9cedbea247689a760bd83cd0d45 Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74961 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2023-04-29mb/google/rex/variants/screebo: Generate RAM IDsKapil Porwal
Generate RAM IDs for - MT62F512M32D2DR-031 WT:B (LP5) H9JCNNNBK3MLYR-N6E (LP5) MT62F1G32D2DS-026 WT:B(LP5x) H58G56BK7BX068 (LP5X) BUG=b:276814951 TEST=Run part_id_gen tool without any errors Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: I0fb2e488c06ed74d3fd493e5ca0ab89a825a9349 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74802 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-04-28mb/google/rex/var/screebo: Add initial setup for gpio configKun Liu
add the initial gpio configuration for screebo initial variant BUG=b:276814951 TEST=emerge-rex coreboot Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com> Change-Id: Ib96e03f47bc1d6e5628ae459c3e1eb4dc18849c7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74475 Reviewed-by: YH Lin <yueherngl@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-04-27mb/google/rex: Add USB4 ANX7452 Rev 2 to USB_DB FW_CONFIGSubrata Banik
This patch adds new USB_DB FW_CONFIG to enable support for USB4 ANX7452 Rev 2. BUG=b:279647370 TEST=Able to build and boot google/rex with Proto 2 SKU Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I878b591e5919d05d3c5fc2eefdeb492e95d4f7b5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74775 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: YH Lin <yueherngl@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-04-17mb/google/rex: Enable all DDI lanesAnil Kumar
This patch enables all DDI ports on Rex board to support display port tunneling and dual display on TBT dock. BUG=b:273901499 TEST=Boot google/rex and connect two displays over a TBT dock and check the display functionality. Signed-off-by: Anil Kumar <anil.kumar.k@intel.com> Change-Id: I45ee5334fbb877bd58912c8d24920037f155dc42 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74413 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-16mb/google/rex: Create screebo variantSimon Zhou
Create the screebo variant of the rex0 reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0). BUG=b:276814951 BRANCH=None TEST=util/abuild/abuild -p none -t google/rex -x -a make sure the build includes GOOGLE_SCREEBO Change-Id: I8d05ca7c0fe596378ca15d0734d46ad1dc63a1f9 Signed-off-by: Simon Zhou <zhouguohui@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74391 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-04-12mb/google/rex: remove weak from cros gpioEric Lai
No need for variant to use _weak. BUG=b:276818954 TEST=new_variant_fulltest.sh rex0 Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: I7ad904e06e5d83edf4bc11cafd5060ca409bd4ae Reviewed-on: https://review.coreboot.org/c/coreboot/+/74294 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
2023-04-11mb/google/rex: Add DTT thermal settings for thermal controlSumeet Pawnikar
Add DTT thermal settings for thermal control provided by thermal team for rex0 board BRANCH=None BUG=b:262498724, b:270664854 TEST=Built and verified thermal entries in ACPI SSDT on Rex board Change-Id: I00dd97b759c8c68edaeeb4d64422b83c5e86981d Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71166 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-04-03mb/google/rex: Use FW_CONFIG for generating ACPI code for WIFISubrata Banik
This patch avoids creating runtime ACPI for unused WIFI solutions. For example: if the Rex SKU is with WIFI_CNVI then you don't need to populate ACPI code for WIFI_PCIE. FW_CONIG can be used for making those decisions. TEST=No ASL entries being created for WIFI_PCIE if the FW_CONIG is set to WIFI_CNVI. Also, helped to save the boot time on google/rex (FSP-S API) by 9ms. Change-Id: I60e4332d8d8c360fdf425b30513ff79209979e85 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74147 Reviewed-by: YH Lin <yueherngl@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-04-01mb/google/rex: Add FW_CONFIG for FP/UWB/WIFISubrata Banik
This patch adds FW_CONFIG to accommodate different Rex BoM components across various SKUs. 1. Fingerprint sensor - FP Present/Absent 2. Ultra wideband - UWB Absent/Using BITBANG/Using GSPI1 3. WIFI - CNVi/PCIe TEST=Able to build and boot google/rex. Change-Id: I97b0dc25f239103a0a235f14b50008a633e2f88d Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74146 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: YH Lin <yueherngl@google.com>
2023-03-30Revert "mb/google/rex: Enable VPU"Kapil Porwal
This reverts commit 555ceca38a78 ("mb/google/rex: Enable VPU"). Reason: Unable to boot to latest OS image with VPU enabled. BUG=none TEST=Boot to OS image 15376 on google/rex Change-Id: If61282528922304373d492b362056b52995cbcad Signed-off-by: Kapil Porwal <kapilporwal@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73694 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Paz Zcharya <pazz@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2023-03-25mb/google/rex: Use HI-556W for Proto 1 SKUsSubrata Banik
This patch drops the UFC sensor OV2740 (reused from the Brya chassis) support for Rex and added support for Rex specific UFC sensor HI-556W. BUG=b:269499723 TEST=Verified UFC is working on google/rex Proto 1. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I6b8ac08adec351a103ac1764d974db4881dc4d6e Reviewed-on: https://review.coreboot.org/c/coreboot/+/70225 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
2023-03-20mb/google/rex: Enable USB camera powerIvy Jian
Add enable_gpio for USB power resource BUG=b:273891168 TEST=Able to detect USB CAM Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Change-Id: I08ebe560c8b75c8b590c889b7b90dbe678318d2a Reviewed-on: https://review.coreboot.org/c/coreboot/+/73754 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-03-15mb/google/rex: Add Hayden Bridge (HB) to USB_DB FW_CONFIGSubrata Banik
This patch increases FW_CONFIG for USB_DB to 3-bits. BUG=b:273346973 TEST=Able to build and boot google/rex with Proto 2 SKU Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ib07ba1d54e7f7e2b09a99438529e503d9c9edb7d Reviewed-on: https://review.coreboot.org/c/coreboot/+/73719 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-03-15mb/google/rex: Configure _DSC for camera devicesJamie Ryu
Configure _DSC to ACPI_DEVICE_SLEEP_D3_COLD so that the driver skips initial probe during kernel boot and prevent privacy LED blink. BUG=b:268607999 TEST=Build and boot rex proto1 to OS and verify privacy LED behavior. Change-Id: Ife849f7407b02867ddb992d7eebb08b0b44aecc8 Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73193 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kiran2 Kumar <kiran2.kumar@intel.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-03-08mb/google/rex: Rename touchscreen signals as per latest Rex schematicsEran Mitrani
Touchscreen signals were renamed for Rex schematics dated 21st Dec'22. This CL fixes the comments for those signals. BUG=b:263411413 TEST=None required (changed comments only) Signed-off-by: Eran Mitrani <mitrani@google.com> Change-Id: Ic40ef943d199d9f4a2bec9c0e6d4820224ef6adc Reviewed-on: https://review.coreboot.org/c/coreboot/+/71795 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-03-02mb/google/rex: Enable VPURavi Sarawadi
BUG=b:270529665 TEST=Verify the build and boot on Rex board Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Change-Id: I0e3d3312c546a2a468fb906a08b8d3ec3e96c46a Reviewed-on: https://review.coreboot.org/c/coreboot/+/72417 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-03-02mb/google/rex: Generate LP5 RAM ID for `K3KL6L60GM-MGCT`Subrata Banik
Add the support LP5 RAM parts for rex: DRAM Part Name ID to assign K3KL6L60GM-MGCT 3 (0011) BUG=b:270708359 TEST=emerge-rex coreboot Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Id0925ccec014c9c535178ed3d908e60889df624d Reviewed-on: https://review.coreboot.org/c/coreboot/+/73344 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-03-02mb/google/rex: Generate LP5 RAM ID for `H58G56BK7BX068`Subrata Banik
Add the support LP5 RAM parts for rex: DRAM Part Name ID to assign H58G56BK7BX068 1 (0001) BUG=b:270708359 TEST=emerge-rex coreboot Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I9eea7e277628992be9b7768a678a50425444002a Reviewed-on: https://review.coreboot.org/c/coreboot/+/73342 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-02-27mb/google/rex: Remove `fixme` from gpio.hKapil Porwal
Remove `fixme` from gpio.h since it has been addressed. BUG=none TEST=Only a cosmetic change Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: I79a2493dba6becd4b8c1ebf37e452a5a173eb396 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73270 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2023-02-23mb/google/rex: Set audio GPIOs based on fw_configKapil Porwal
Define some actions based on probe results for audio: - Disable the SoundWire GPIOs when I2S option is selected. - Disable the I2S GPIOs when SoundWire option is selected. - Disable all the GPIOs when no audio is enabled. BUG=b:269497731 TEST=Test that GPIOs are configured based on the current value of the fw_config field in cbi. Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: I0ed452a0d08e6779add318d9bbd1e97b50b6aea9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73121 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-02-23mb/google/rex: Use gpio padbased table overrideKapil Porwal
In order to improve gpio merge mechanism. Change iteration override to padbased table override. And the following patch will change fw config override with ramstage gpio table override. Port of commit 7aef2b1294f2 ("mb/google/nissa: Apply gpio padbased table override") BUG=none TEST=Verify devbeep at depthcharge console Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: I2ee86bbec7d25a35d726f29ad79891f1054bf52c Reviewed-on: https://review.coreboot.org/c/coreboot/+/73182 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-02-22mb/google/*: Resume from suspend on critical batteryIvan Chen
This patch makes EC wake up AP from s3/s0ix for OS shutdown/hibernate when the state of charge drops to low_battery_shutdown_percent. BUG=b:255465618 TEST=emerge-nissa chromeos-bootimage (EC: https://crrev.com/c/4243898) Verify system resumes from s0ix and then enter S5 on nivviks with steps: 1. disconnect AC 2. powerd_dbus_suspend --disable_dark_resume=false 3. fakebatt 5 4. fakebatt 4 Change-Id: I63b5246432687e38ddfc5733ac3a115c3456d7e9 Signed-off-by: Ivan Chen <yulunchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73082 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com>
2023-02-16mb/google/rex: Mark unused USB ports as emptySubrata Banik
This patch marks unused USB ports (USB2.0/TCSS) empty to avoid prompting wrong dmesg as below. ``` usb usb2-port3: Cannot enable. Maybe the USB cable is bad? ``` Mainboard variants to override the USB ports as per the target board design. TEST=Able to build and boot google/rex with all USB ports are working as expected. Change-Id: Ic3d21151a22f2318413f480f3386bf2dbf696307 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73027 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-02-14mb/google/rex: Set `SkipExtGfxScan` FSP-M UPDSubrata Banik
This patch overrides `SkipExtGfxScan` UPD as the Rex device is equipped with an on-board graphics device hence, skip scanning external GFX devices. BUG=b:228002764 TEST=Able to save ~1ms+ boot time on google/rex. FSP FPDT Data is showing the timestamp between those function calls. Without this patch: [INFO ] CheckOffboardPcieVga/5b7cc220-e183-481c-87f427a92d8db88f -> 979684 -> 22 [INFO ] CheckOffboardPcieVga/5b7cc220-e183-481c-87f427a92d8db88f -> 980815 -> 1131 With this patch: `CheckOffboardPcieVga` is not getting called. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I20aa09e80671ab94e639787f40b95b740bbe5efb Reviewed-on: https://review.coreboot.org/c/coreboot/+/72948 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-02-04mb/google/rex: Use OV13B10 sensor for Proto 1 SKUsSubrata Banik
This patch drops the WFC sensor OV8856 (reused from the Brya chassis) support for Rex and added support for Rex specific UFC sensor OV13B10. BUG=b:267264348 TEST=WFC MIPI cameras have been enabled using google/rex Proto 1. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ic785b82db4368f40d91921f29c218cf417938541 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70226 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2023-02-04Revert "UPSTREAM: mb/google/rex: Enable SaGv"Subrata Banik
Enabling `SaGv` along with FSP v2473 is causing blank display issue. Mostly likely we shouldn't enable SaGv yet on Intel MeteorLake. BUG=b:267446159 TEST=Able to see ChromeOS UI in consecutive boot. This reverts commit cbca81c5946384843197c08401c4266f45fef4a2. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ifbcc36515f7550c183c40e5af94684f5c3e39a7a Reviewed-on: https://review.coreboot.org/c/coreboot/+/72774 Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-03mb/google/rex: update touchscreen report EN pin settingIvy Jian
Removed workaround since the latest schematics fixed. Power Sequencing of ELAN6918 (in ACPI) after this patch `POWER enabled -> RESET deasserted -> Report EN enabled` BUG=b:247029304 TEST=Verified ELAN touch panel is working as expected after booting Google/rex device to ChromeOS. Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Change-Id: I19629262776f7e0cccbdebb2285890d177a8a8a6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72725 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-01-24mb/google/rex: Enable SaGvSubrata Banik
This patch overrides `SaGv` FSP-M UPD to enable SaGv feature to be able to train memory (DIMM) at different frequencies. On all latest Intel based platforms SaGv is expected to be enabled to support dynamic switching of memory operating frequency. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I7cf52b966c1355c1f2bd4ae7c256fa4252a90666 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72136 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
2023-01-19intel/meteorlake: remove skip_mbp_hob SOC chip configKapil Porwal
Introduce at new config option CONFIG_FSP_PUBLISH_MBP_HOB to control the creation of ME_BIOS_PAYLOAD_HOB (MBP HOB) by FSP. This new option is hooked with `SkipMbpHob` UPD and is always disabled for ChromeOS platforms. This made skip_mbp_hob SOC chip config variable redundant which is also removed as part of this change. BUG=none TEST=Build and boot to Google/Rex. Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: Iaba1ea29a92a63d2b287e1ccdea1a81ec07b9971 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71997 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-01-15drivers/i2c/generic: Drop 'disable_gpio_export_in_crs' flagMatt DeVillier
Exposing the GPIOs via an ACPI PowerResource and the _CRS results in the OS driver and ACPI thinking they own the GPIO. This can cause timing problems because it's not clear which system should be controlling the GPIO. Previously, we flagged as an error any device which set the 'has_power_resource' flag but did not set 'disable_gpio_export_in_crs.' There's no reason to require explicit disablement however, so drop the superfluous 'disable' flag, and change the _CRS generation to check if the GPIOs will be exported via the 'has_power_resource' flag instead. BUG=b:265055477 TEST=build/boot skyrim, dump SSDT and verify touchscreen GPIOs only listed under PRx, not under _CRS. Change-Id: I837ae6c6fe4b8e1c4e10686406cba06bdb7759d2 Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71849 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-01-04mb/google/rex: Configure EN_DMIC_SOC_DATA to GPO and LOWSubrata Banik
This patch configures GPP_H15 (EN_DMIC_SOC_DATA) as GPO and put into safe state aka LOW/PD. BUG=b:263411621 TEST=Able to build and boot Google, Rex to ChromeOS. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I3d376f895b2f0882c9fa6fe7b98686907bde4321 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71631 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-02mb/google/rex: Update USB2-C1 mappingSubrata Banik
This patch updates the USB2-C1 mapping from USB2 Port 4 to USB2 Port 1 as per latest Rex schematics dated 12/06/2022. TEST=Hardward awaited. Change-Id: Ifc82200e6eafcea7e820a96df81325f3c8849fd1 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70426 Reviewed-by: Eran Mitrani <mitrani@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-02mb/google/rex: Remove USB2_8 ConnectionSubrata Banik
DCI interface deprecated for Proto1. USB2_8 port becomes no-connect. BUG=b:263494661 TEST=Able to build and boot Google/Rex. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I6f03d600acd8ceaa5a5630fc19c1c7e34a4ea28f Reviewed-on: https://review.coreboot.org/c/coreboot/+/71237 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-30 04:42:02 +0000