coreboot.git - my copy of coreboot

Age	Commit message (Collapse)	Author
2023-10-27	mb/google/rex: Update FMD to support CBFS verification	Anil Kumar
	This patch adds the required FMD changes to support the change in cse_lite 'commit Ie0266e50463926b8d377825 ("remove cbfs_unverified_area_map() API in cse_lite")' for CBFS verification. These blobs were kept separate originally to avoid hash loading and verification every time and hence save boot time. With the change in cse_lite the ME_RW_A/B blobs are now part of FW_MAIN_A/B and corresponding entries in FMD can be removed. BUG=b:284382452 TEST=Build CB image for google/rex board and test CSE FW update/downgrade with CONFIG_VBOOT_CBFS_INTEGRATION config enabled. Also confirm there is no increase in boot time with this change. Signed-off-by: Anil Kumar <anil.kumar.k@intel.com> Change-Id: I56865a9e5c8b5f9e908e00e1a7e7e187d5d6a2f5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78487 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
2023-09-22	mb/google/rex: Add new FMD for prod (QS) Meteor Lake silicon	Subrata Banik
	Intel Meteor Lake QS silicon provides better size optimized pre-x86 reset blobs. This patch creates a new flash layout (FMD) for QS to accommodate those optimizations, and renames the existing FMD for ES (pre-prod) silicon. Comparative analysis between QS and ES flash layout is here: For QS silicon: - SI_ALL reduced from 9MB to 8MB. - SI_BIOS increased by 1MB (from 23MB to 24MB) to fill in the 32MB SPI layout. - ME_RW_A/B reduce from ~4.5MB to 4MB. - Ensure RW-B slot is starting at 16MB boundary. - Unused space increased by 1MB. For ES silicon: - SI_ALL: 9MB - SI_BIOS: 23MB - ME_RWA/B: 4.5MB (for ISH) and 4.4MB (non-ISH). - Unused space 3MB (for release) and 2MB (for debug) layout. Change-Id: I881832a6b11a35710d4e847feadcc544b1f5d048 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77994 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jakub Czapiga <jacz@semihalf.com>