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path: root/src/mainboard/google/rex/Kconfig
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2022-08-02mb/google/rex: Enable CSE Lite SKUSubrata Banik
The first CSE Lite SKU is available, therefore enable the Kconfig option to have the CSE reboot the system into its RW FW during a cold boot. BUG=b:240228892 TEST=TBD Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I00ef4176cf08cbeed06e446cfe68f06cb1ea27b4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66287 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-23mb/google/rex: Add GBB related configsSubrata Banik
This patch adds more GBB related configs. Select `HAS_RECOVERY_MRC_CACHE` config. Additionally, move VBOOT_LID_SWITCH config under VBOOT config. TEST=Able to build the Google/Rex. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I28976200cbd70dc23f58868ee89c0ac700793be9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66007 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2022-07-22mb/google/rex: Add TPM device to Kconfig and devicetreeKapil Porwal
Add TPM device for Rex. Device details: I2C Controller/Bus = 4 I2C Slave Address = 0x50 GPE = GPE0_DW1_03/GPP_E03 BUG=b:224325352 TEST=Verified in emulator that there is no regression Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: Ifa3a5b503a203e3900049f27a54025156e22a285 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66014 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-22mb/google/rex: Enable EC_GOOGLE_CHROMEEC_BOARDID KconfigTarun Tuli
Enables the EC_GOOGLE_CHROMEEC_BOARDID feature so we can read board_id() on rex. TEST=Verified builds succeed and code is linked Change-Id: Id202019519fc4a05c80374bc97663e59fdca3d76 Signed-off-by: Tarun Tuli <taruntuli@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66018 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-07-14mb/google/rex: Add chip config for UART devicesSubrata Banik
This patch ensures LPSS UART 0 is used for the AP serial console as per Rex Proto 0 schematics dated 07/05. +-----------+-------------+-------------+ | INTERFACE | PCI (B:D:F) | DEVICE | +-----------+-------------+-------------+ | UART-0 | 0:0x1e:0 | For AP UART | +-----------+-------------+-------------+ | UART-1 | 0:0x1e:1 | NA | +-----------+-------------+-------------+ | UART-2 | 0:0x19:2 | NA | +-----------+-------------+-------------+ BUG=b:224325352 TEST=Able to get AP UART over LPSS UART0 using emulator. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ice0c81607c758e94d15ea19e346877776a3de7dd Reviewed-on: https://review.coreboot.org/c/coreboot/+/65668 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-07-14mb/google/rex: Add overridetree.cb for `rex0` variantSubrata Banik
This patch adds initial PCI device entries into the override devicetree. BUG=b:224325352 TEST=Able to build Google/Rex and verified on MTL emulator. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I16326747df46769f93813ce322ed8045449ffa85 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65784 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-07-01mb/google/rex: Redirect AP UART over LPSS UART 0Subrata Banik
This patch ensures AP UART messages are coming over LPSS UART 0 hence, select required kconfig and program both early and late UART RX/TX GPIOs accroding to the rex schematics dated 06/27. BUG=b:224325352 TEST=Able to see AP UART log over LPSS UART0. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I7daa8200d1a7cf825dfdfed538573efd57ab2d97 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65454 Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-01mb/google/rex: Add memory initEric Lai
Add memory init with placeholder to fill in required memory configuration parameters. DQ map and Rcomp can be auto probed by the FSP-M hence, kept it as default. BUG=b:224325352 TEST=util/abuild/abuild -p none -t google/rex -a -c max Able to boot till FSP-M/MRC using MTL simics. Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I5baa87411c28a20602eb5a7077f00664ccab3ade Reviewed-on: https://review.coreboot.org/c/coreboot/+/64850 Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-01mb/google/rex: Enable building for Chrome OSEric Lai
Enable building for Chrome OS and add associated ACPI configuration. BUG=b:224325352 TEST=util/abuild/abuild -p none -t google/rex -a -c max Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: I75cb2d30d699166a056ed9d3c0779816b733b0d2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64621 Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-01mb/google/rex: Enable ECEric Lai
Perform EC initialization in bootblock and ramstages. Add associated ACPI configuration. BUG=b:224325352 TEST=util/abuild/abuild -p none -t google/rex -a -c max Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I2ea934f32b34bc43650e20dd2736f4e652004dc2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64622 Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-01mb/google/rex: Enable ACPI and add ACPI tableEric Lai
Enable ACPI configuration and add DSDT ACPI table. BUG=b:224325352 TEST=util/abuild/abuild -p none -t google/rex -a -c max Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: I8374a9b528f8dff4e23b6bdb4d1368dfd2c79b8e Reviewed-on: https://review.coreboot.org/c/coreboot/+/64620 Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-01mb/google/rex: Add GPIO stubsEric Lai
Add stubbed out GPIO configuration and perform GPIO initialization during bootblock, romstage and ramstage. BUG=b:224325352 TEST=util/abuild/abuild -p none -t google/rex -a -c max Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: I51426f9557dafc357fc54a971b6f76fac5323e0a Reviewed-on: https://review.coreboot.org/c/coreboot/+/64593 Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-01mb/google/rex: Add MTL reference platformSubrata Banik
This commit is a stub for rex, which is a an Intel Meteor Lake-P reference platform. BUG=b:224325352 TEST=util/abuild/abuild -p none -t google/rex -a -c max Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I46bd8d47b370cacbe0a09bbeaccacf7f1d51d8b6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62969 Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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