summaryrefslogtreecommitdiff
path: root/src/mainboard/google/rex/Kconfig
AgeCommit message (Collapse)Author
2023-07-12mb/google/rex: Disable DRIVERS_INTEL_DPTF_SUPPORTS_TPCHKane Chen
There is no PCH FIVR participant on MTL and we should remove it in Rex. TEST=compile ok and make sure there no TPCH device in acpi BUG=b:290322310 Change-Id: Icf4be86da3f3cb9b1f0a3f2586b029a533c3e6a9 Signed-off-by: Kane Chen <kane.chen@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76402 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-11mb/google/rex: LZ4 compress ramstage instead of LZMAWonkyu Kim
for saving boot time, change ramstage compression from LZMA to LZ4. Boot time saving is around 35ms (30-37ms) while SPI size impact is 230KB. For detail, refer below. Existing: LZMA(55.6 ms) 8:starting to load ramstage 894,519 (0) 15:starting LZMA decompress (ignore for x86) 903,556 (9,036) 16:finished LZMA decompress (ignore for x86) 949,997 (46,441) 9:finished loading ramstage 950,179 (182) Changed: LZ4(17.8ms) 8:starting to load ramstage 900,876 (0) 17:starting LZ4 decompress (ignore for x86) 917,650 (16,774) 18:finished LZ4 decompress (ignore for x86) 918,690 (1,040) 9:finished loading ramstage 918,849 (158) Size impact (73KB * 3 = 219KB) fallback/ramstage 0x62940 stage 240281 LZ4 (405524 decompressed) fallback/ramstage 0x62940 stage 165452 LZMA (405524 decompressed) BUG=b:286930648 TEST= Boot to OS and check boot time Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Change-Id: I6610f405d287bff2eb4eee6f09026e3361405ded Reviewed-on: https://review.coreboot.org/c/coreboot/+/75769 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-07-05mb/google/rex: Temporarily disable the crashlogKapil Porwal
Currently, boards with ES2 silicon are unable to boot with crashlog enabled because crashlog driver is unable to handle invalid data. Temporarily disable the crashlog to unblock development until the issue is fixed. BUG=b:289749310 TEST=Able to boot to the OS on Screebo Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: Ic63cf9cf5bfa2c92d8f2c5b13df2f23dc118b389 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76231 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
2023-06-28mb/google/rex/var/ovis: Enable crashlog and IOE dieJakub Czapiga
BUG=b:262501347 TEST=Boot on Ovis board. Change-Id: I43aac857e3ec7989c9ab5201cd8f24a7c877e76b Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76151 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-06-28mb/google/rex: Avoid boot hang due to missing SOC/IOE SRAM deviceSubrata Banik
The SOC/IOE SRAM device is used to store crash logs. Previously, the crashlog enablement was hardcoded in the baseboard.common module. This commit moves the crashlog enablement logic to the baseboard module, so that it can be enabled or disabled based on the specific baseboard. Additionally, the SOC/IOE SRAM is now enabled by default in the baseboard devicetree.cb file. This prevents the system from hanging if the SOC/IOE SRAM device is not present. BUG=b:262501347 TEST=Able to build and boot google/screebo with this patch. w/o this patch: [ERROR]  SOC SRAM device not found! [ERROR]  IOE SRAM base not valid Change-Id: I02d581e5b62cfa114a3761a9704ad9f24dead8aa Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76134 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-06-26mainboard/google/rex: Enable crashlogPratikkumar Prajapati
Enable crashlog for rex. Select config options SOC_INTEL_CRASHLOG, and SOC_INTEL_IOE_DIE_SUPPORT. Also enable ioe_shared_sram and pmc_shared_sram devices. BUG=b:262501347 TEST=Able to trigger Crashlog, BERT table gets generated and decodes as expected. Change-Id: I3d3a9fb41d1293f021ad9de9b29c756cb7559373 Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74770 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-06-22mb/google/rex: Disable TCSS config for pre-boot displayKapil Porwal
Pre-boot display is not POR for google/rex hence disable the config ENABLE_TCSS_DISPLAY_DETECTION. BUG=b:247670186 TEST=Build and boot to google/rex and make sure that display over TCSS works in the OS Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: Ib55e251a4620c7a375ee2f27763154c39207236e Reviewed-on: https://review.coreboot.org/c/coreboot/+/75927 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-06-21mb/google/rex/var/ovis: Select SOC_INTEL_METEORLAKE_U_HJakub Czapiga
Ovis uses MTL-H. BUG=b:274421383 TEST=util/abuild/abuild -p none -t google/rex -x -a -b ovis TEST=cros build-packages --board ovis chromeos-bootimage Change-Id: I284c72b902490187d0b15e4fc81650af1cfa16d7 Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75887 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-21meteorlake: Rename `SOC_INTEL_METEORLAKE_U_P` as per latest EDSSubrata Banik
This patch renames config `SOC_INTEL_METEORLAKE_U_P` to `SOC_INTEL_METEORLAKE_U_H` as per Intel Meteor Lake Processor EDS version 1.3.1 (doc number: 640228). With new branding, the MTL-U/H-Processor Line offered in a 1-chip platform that includes the Compute, SOC, GT, and IOE tile on the same package. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I032be650bbfef0bf0ef86bb37417b1d854303501 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75931 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
2023-06-06mb/google/rex/var/rex0: Add new GFX devices with custom _PLDWon Chung
Add new GFX devices for DDI and TCP with custom _PLD to describe the corresponding ports. BUG=b:277629750 TEST=emerge-rex coreboot Signed-off-by: Won Chung <wonchung@google.com> Change-Id: I193b95e8bd8ae538c4f25fbe772b174ef455d744 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74367 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-06-06mb/google/rex: Create ovis variantJakub Czapiga
BUG=b:274421383 TEST=util/abuild/abuild -p none -t google/rex -x -a ; Make sure GOOGLE_OVIS built successfully Change-Id: I5c8f290cfdcb4d47c0e5e9d72c1e34073b957681 Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75385 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-04mb/google/rex: Enable ISH supportBernardo Perez Priego
Enable ISH based on FW_CONFIG obtained from EC CBI. This is useful in case device is a tablet and motion sensors are handled by ISH instead of EC. BUG=b:280329972,b:283023296 TEST= Set bit 21 of FW_CONFIG with CBI Boot rex board Check that ISH is enabled and loaded Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com> Change-Id: Ibe0e1b8ce2c9b08ac6b1e6fef9bd19afc9b4f59f Reviewed-on: https://review.coreboot.org/c/coreboot/+/75039 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-04mb/google/rex: Select SOC_INTEL_METEORLAKE_U_PSubrata Banik
Google/Rex is built with Intel Meteor Lake-U SoC, so select it. Currently, there is no functional difference, but in the future FSP UPD parameters can be overridden properly. BUG=b:276697173 TEST=Able to build and boot google/rex. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I4c233e0a8ce58998dc1a0379662e386f9b3d0073 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75612 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-06-03mb/google/rex: Create karis variantTyler Wang
Create the karis variant of the rex0 reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0.) BUG=b:285195072 TEST=util/abuild/abuild -p none -t google/rex -x -a make sure the build includes GOOGLE_KARIS Change-Id: I16d8b43390401789b87a6233238e37f32a17b46b Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75551 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-05-31mb/google/rex: Move I2S config from common to boardKapil Porwal
Move I2S config from common to board. BUG=none TEST=Build google/rex Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: I51ca902e9b0077d5d5cc9c3507d26301a0f61bc2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75513 Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-31mb/google/rex: Enable SoundWire codecsKapil Porwal
Enable drivers for SoundWire codecs and define the topology in the devicetree for the rex0 variant with the SoundWire daughter board connected. +------------------+ +--------------------+ | | | Headphone Codec | | Intel Meteor Lake| +--->|Cirrus Logic CS42L42| | SoundWire | | | ID 0 | | Controller | | +--------------------+ | | | | Link 0 +----+ +-------------------+ | | | Left Speaker Amp | | Link 1 | +--->| Maxim MAX98363 | | | | | ID 0 | | Link 2 +----| +-------------------+ | | | | Link 3 | | +-------------------+ | | | | Right Speaker Amp | +------------------+ +--->| Maxim MAX98363 | | ID 1 | +-------------------+ This was tested by booting the firmware and dumping the SSDT table to ensure that all SoundWire ACPI devices are created as expected with the properties that are defined in coreboot under \_SB.PCI0: HDAS - Intel Meteor Lake HDA PCI device HDAS.SNDW - Intel Meteor Lake SoundWire Controller HDAS.SNDW.SW00 - Cirrus Logic CS42L42 - Headphone Codec HDAS.SNDW.SW20 - Maxim MAX98363 - Left Speaker Amp HDAS.SNDW.SW21 - Maxim MAX98363 - Right Speaker Amp BUG=b:269497731 TEST=Verified SSDT for SNDW in the OS. Playback and recording are also validated on google/rex. Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: I3e11dc642ff686ba7da23ed76332f7f10e60fade Reviewed-on: https://review.coreboot.org/c/coreboot/+/73280 Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-27mb/google/rex: Update FMD to incorporate ISH firmwareSubrata Banik
This patch adds two new chromeos_*.fmd files for release and debug FSP builds targeting rex_ec_ish. `rex_ec_ish` variant would pack ISH firmware into the CSE boot partition hence, the blob size is expected to increase. Creates separate flash map layout to ensure ISH work is not impacting on the regular `rex0` project SPI flash usage. BUG=b:284254353 TEST=Able to build google/rex_ish_ec board and boot on target hardware. Change-Id: Ife4663d3ccf80a928646eadaac4c9ab49ad29055 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75471 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: YH Lin <yueherngl@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-27mb/google/rex: Create variant to support ISH enablementSubrata Banik
This patch creates a new variant to support the ISH enablement using Rex platform.The idea here is to leverage the `rex0` code as much as possible and add specific support for ISH enablement as per the hardware schematic differences. BUG=b:284254353 TEST=Able to build google/rex_ish_ec board and boot on target hardware. Change-Id: I625fd0b31aed998f4e8f2d139827bc212ee8a90b Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75470 Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: YH Lin <yueherngl@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-05-26mb/google/rex/variants/baseboard/rex: Add CPU power limit valuesSumeet Pawnikar
Add support of variant_devtree_update() function to override devtree settings for variant boards. Also, add CPU power limit values for rex baseboard. BRANCH=None BUG=b:270664854 TEST=Built and verified power limit values as below log message for 15W SKU on Rex board. Overriding power limits PL1 (mW) (10000, 15000) PL2 (mW) (57000, 57000) PL4 (W) (114) Change-Id: If46445157358e3e0f227e26a35b4303fc9189a4b Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74754 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Harsha B R <harsha.b.r@intel.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-05-19mb/google/rex: Enable stylus supportDinesh Gehlot
This patch enables stylus support by configuring the "GPP_D08" irqs for rex SoC. This allows the SoC to detect a stylus device, when in use. However stylus is not a wake up source for the rex. BUG=b:282256460 Test=Stylus is detected on proto1 device. Signed-off-by: Dinesh Gehlot <digehlot@google.com> Change-Id: I84a71aa664698e105b738f8680d0a4751ca1fc72 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71820 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-05-14mb/google/rex/var/screebo: Add initial devicetree configKun Liu
add initial devicetree config for screebo BUG=b:276814951 TEST=emerge-rex coreboot Change-Id: Ie64d0e50ec22b3e363597af64eb723ef1f86dfa8 Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74972 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-04-22mb/google/rex: Enable asynchronous End-Of-PostSubrata Banik
Set the `SOC_INTEL_CSE_SEND_EOP_ASYNC' flag to request End-Of-Post right after PCI enumeration and handle the command response at `BS_PAYLOAD_BOOT'. With these settings we have observed a boot time reduction of about 100ms on google/rex. TEST=Tests on google/rex with `SOC_INTEL_CSE_SEND_EOP_ASYNC' show End-Of-Post after PCI initialization and EOP message received at `BS_PAYLOAD_BOOT'. Change-Id: I27b540eeddcada521eba91fcc51504831d6dc855 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74562 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-04-16mb/google/rex: Create screebo variantSimon Zhou
Create the screebo variant of the rex0 reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0). BUG=b:276814951 BRANCH=None TEST=util/abuild/abuild -p none -t google/rex -x -a make sure the build includes GOOGLE_SCREEBO Change-Id: I8d05ca7c0fe596378ca15d0734d46ad1dc63a1f9 Signed-off-by: Simon Zhou <zhouguohui@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74391 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-04-04mb/google/rex: Enable CSE pre-cpu timestampsBora Guvendik
Enables pre-cpu boot timestamps from cse. 990:CSME ROM started execution 0 944:CSE sent 'Boot Stall Done' to PMC 47,000 945:CSE started to handle ICC configuration 225,000 (178,000) 946:CSE sent 'Host BIOS Prep Done' to PMC 225,000 (0) 947:CSE received 'CPU Reset Done Ack sent' from PMC 516,000 (291,000) 991:Die Management Unit (DMU) load completed 587,000 (71,000) 0:1st timestamp 597,427 (10,427) BUG=b:259366109 TEST=Boot on rex, check "cbmem -t" Change-Id: I68cd53c18af6a400bcd9dc15d428a904b0647495 Signed-off-by: Bora Guvendik <bora.guvendik@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73759 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-04-01mb/google/rex: Add fmd for debug FSPSubrata Banik
Debug FSP is ~920KiB larger than release FSP and we don't have sufficient space for rex flash layout. Remove RW_LEGACY and split them into RW_SECTION_A/B so we can have a room for it. Note: This fmd will only used for internal testing/debugging and not for the firmware in released devices. BUG=b:262868089 TEST=Build google/rex with CONFIG_BUILDING_WITH_DEBUG_FSP. Change-Id: I58b0af9c43c5d096dc80084497b39f13f67c25cd Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74140 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-03-29mb/google/rex/Kconfig: Add SMBIOS mainboard version flagJay Patel
Add GOOGLE_SMBIOS_MAINBOARD_VERSION flag for rex board. BUG=None TEST=Verfied board ID for rex using "crossystem" command, giving the output as 1. Without CL: localhost ~ # crossystem arch = x86 # [RO/str] Platform architecture backup_nvram_request = 1 # [RW/int] Backup the nvram somewh battery_cutoff_request = 0 # [RW/int] Cut off battery and shu block_devmode = 0 # [RW/int] Block all use of develo board_id = (error) # [RO/int] Board hardware revision clear_tpm_owner_done = 0 # [RW/int] Clear TPM owner done With CL: localhost ~ # crossystem arch = x86 # [RO/str] Platform architecture backup_nvram_request = 1 # [RW/int] Backup the nvram somewh battery_cutoff_request = 0 # [RW/int] Cut off battery and shu block_devmode = 0 # [RW/int] Block all use of develo board_id = 1 # [RO/int] Board hardware revision clear_tpm_owner_done = 0 # [RW/int] Clear TPM owner done Signed-off-by: Jay Patel <jay2.patel@intel.com> Change-Id: I644ed7a948f0094a0be080153d83eaa2e37b8f1f Reviewed-on: https://review.coreboot.org/c/coreboot/+/74037 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-19mb/google/rex: Move BOARD_GOOGLE_BASEBOARD_REX to Kconfig.nameEric Lai
Align project style with other chrome projects. TEST=built FW not changed Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: Icfd1d274216d387cab6feb68afa49fc63c8c52e5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73761 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-01-07mb/google/rex: Disable stage cacheSubrata Banik
This patch disables the stage cache to save boot time. Note: S3 is not POR for Intel MTL mobile skus. Boot time is reduced by ~8ms. Boot time before: 4:end of romstage 1,391,225 (13,724) 100:start of postcar 1,403,339 (12,114) Boot time after: 4:end of romstage 1,380,262 (5,618) 100:start of postcar 1,392,323 (12,060) Change-Id: I9775fc628f345a514894f30435a374e2ffa057c1 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71695 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2022-12-27mb/google/rex: Enable PMC IPC configSubrata Banik
TEST=Able to build and boot Google/Rex. Device (PMC) { Name (_HID, "INTC1026") // _HID: Hardware ID Name (_DDN, "Intel(R) Meteor Lake IPC Controller") // _DDN: DOS Dev ice Name Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0B) } ... } Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I28c0153a770b36cde0653ac92d2e5ad1b8dd3449 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71268 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-24mb/google/rex: Enable DPTF functionality for Rexzhaojohn
Enable DPTF functionality for Meteor Lake Rex board. BUG=b:262498724 TEST=Booted to OS and verified DPTF entries in ACPI SSDT on Rex board. Change-Id: I87b2d71650be9ce940d9452bf4a76d4cd1ddba52 Signed-off-by: zhaojohn <john.zhao@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70884 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-10mb/google/rex: Implement S0ix hooks aka `MS0X` methodSubrata Banik
This patch ensures to be able to drive SYS_SLP_S0IX_L `low` based on the state of the system while `SLP_S0_L` signal is `low` (while the system is in S0ix). Implemented runtime ASL method (MS0X) being called by PEPD device _DSM to configure `SLP_S0_GATE (GPP_H14)` PIN at S0ix entry/exit. Scope (\_SB) { Method (MS0X, 1, Serialized) { If ((Arg0 == One)) { \_SB.PCI0.CTXS (0x75) } Else { \_SB.PCI0.STXS (0x75) } } BUG=b:256807255 TEST=Able to see SYS_SLP_S0IX_L goes low in S0ix. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ie6b5e066f228ea5dc79ae14dd803fc283fd248ce Reviewed-on: https://review.coreboot.org/c/coreboot/+/70196 Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-19mb/google/rex: Enable TCSS DisplayPort detection at prebootzhaojohn
This change enables the DisplayPort detection at preboot for Rex board. BUG=b:247670186 TEST=Built image and validated DisplayPort feature at preboot on Rex. Change-Id: I1a8a13e937c7132696aa39d85c3c6b6fb2dd13a5 Signed-off-by: zhaojohn <john.zhao@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67742 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-11-18mb/google/rex: Disable `ACPI PM timer`Subrata Banik
This patch deselects `USE_PM_ACPI_TIMER` kconfig to ensure that ACPI PM timer remains disabled. The PM timer (by PMC IP) consumes more power and blocks S0ix so the timer is emulated by ucode to save power and unblock S0ix. TEST=Able to boot Google, Rex and ensure PMC MMIO register 0x18fc BIT 1 is set. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I2a23b417ff7fb6328323380a7df46b4b397fc8eb Reviewed-on: https://review.coreboot.org/c/coreboot/+/69685 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-11-09mb/google/rex: Add fingerprint SPIEran Mitrani
Add Fingerprint SPI, and power-off FPMCU during romstage. For reference see CL:66915 for a similar change to Brya's power sequence SHA: 2b523ce6316e5c5ec86fe812d739fe48ca81d83d ("Invoke power cycle of FPMCU on startup") TEST=Tested on Rex - setup and logged in using fingerprint Change-Id: I4e6be24e72a8232ae2c958a01cf8ea9a272d7365 Signed-off-by: Eran Mitrani <mitrani@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66992 Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-10-26mb/google/rex: Move `DRIVERS_INTEL_USB4_RETIMER` configSubrata Banik
This patch moves DRIVERS_INTEL_USB4_RETIMER config from Meteor Lake SoC to Rex mainboard to maintain the symmetry with previous generation ChromeOS devices (Brya and Volteer). BUG=none TEST=Able to build and boot to Google/Rex with USB4 functionality remaining intact. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I38360f6f1f2fcb4b0315de93c68f00d77e63003c Reviewed-on: https://review.coreboot.org/c/coreboot/+/68771 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-10-14mb/google/rex: Add FW_CONFIG* to KconfigEran Mitrani
BUG=b:253199788 TEST=Build and boot to Google/Rex. Change-Id: Ib729c98a4d67aa46992fdccf592010b0313605a6 Signed-off-by: Eran Mitrani <mitrani@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66817 Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-10-14mb/google/rex: Implement WIFI SAR related changesSubrata Banik
1. Add CHROMEOS_WIFI_SAR to include the SAR configs. 2. Add get_wifi_sar_cbfs_file_name() that return the wifi SAR filename. BUG=none TEST=emerge-rex coreboot Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ia863eaa53c9456ae0e9f0e8914e0de497a32b53b Reviewed-on: https://review.coreboot.org/c/coreboot/+/68393 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2022-10-11mb/google/rex: Enable PD SyncSubrata Banik
This patch enables PD Sync for Rex. BUG=b:248775521 TEST=Able to boot Google/Rex with PD sync enabled. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I749b5dea481c7546579e97f923f143dd17f831d3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67819 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
2022-09-29mb/google/rex: Enable EC SW SyncSubrata Banik
This patch de-selects EC software sync config and enable early EC Software Sync. BUG=b:248775521 TEST=Able to perform EC sync on Google/Rex. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I6bf8018e8a3fd06bb98c82a27d12883fc8d3a5db Reviewed-on: https://review.coreboot.org/c/coreboot/+/67817 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2022-09-28mb/google/rex: Set up MIPI cameras via ACPIDaniel Kang
This patch adds ACPI configurations of 8MP YHUX and 2MP CJFKF28-1 as world- and user-facing cameras of Rex. BUG=b:246413264 TEST=Verified world- and user-facing cameras using Chrome Camera App on Google/rex device. Signed-off-by: Daniel Kang <daniel.h.kang@intel.com> Change-Id: Iaaa16e491a66500606b3a9eb1d87f396641778e0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67085 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2022-09-26mb/google/rex: Allocate resources for PCIe TBT root portzhaojohn
This patch selects the SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES to allocate TBT/USB4 root port resources for PCIe tunneling. BUG=b:248328015 TEST=Built image and verified TBT/USB4 tunneling functions on Rex. Change-Id: I69f4d26bb7b3d74dbda068add284a69f1bbeff40 Signed-off-by: zhaojohn <john.zhao@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67781 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-09-26Revert "mb/google/rex: Create 64MB AP Firmware binary for Proto 0"Subrata Banik
This reverts commit 1a8eb6c02103727431ac1ea23f4f507e49f3cde7. Reason for revert: migrating to the 32MB AP Firmware hence, need to revert this CL. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ibea1ad0cff008f9391cbda9e51899557b1e9c979 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67282 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2022-09-20mb/google/rex: Add WWAN ACPI supportIvy Jian
Add FM350GL 5G WWAN support using drivers/wwan/fm and additional PM features from RTD3. BUG=b:244077118 TEST=check cbmem -c \_SB.PCI0.RP06: Enable RTD3 for PCI: 00:1c.5 (Intel PCIe Runtime D3) \_SB.PCI0.RP06: Enable WWAN for PCI: 00:1c.5 (Fibocom FM-350-GL) check PXSX Device is generated in ssdt. Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Change-Id: I6114c589769d2eca882cf1a5255cf4c5937121a6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67336 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-09-19mb/google/rex: Add ELAN6918 touchscreenSubrata Banik
ELAN6918 Power Sequencing seems not perfectly matching with the previous platforms and setting GPP_C06 to high prior to the power sequencing is actually makes it work. Ideally Power Sequencing should be as below for ELAN6918 (in ACPI) `POWER enabled -> RESET deasserted -> Report EN enabled` But below sequence is only working currently: `Report EN enabled (ramstage) -> POWER enabled (ACPI) -> RESET deasserted (ACPI)` BUG=b:247029304 TEST=Verified ELAN touch panel is working as expected after booting Google/rex device to ChromeOS. Change-Id: Ideaeb0faa882b8e603534bbface51ea76923d436 Signed-off-by: Eran Mitrani <mitrani@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66990 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2022-09-16mb/google/rex: Enable `DRIVERS_WIFI_GENERIC` configSubrata Banik
TEST=Able to build and boot the Google/rex. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Iae5317b24856ef2cbd2f36cc28f645826536c21a Reviewed-on: https://review.coreboot.org/c/coreboot/+/67641 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
2022-09-14mb/google/rex: Add audio parts ALC5682I-VS and MAX98357Eran Mitrani
BUG=b:232573696 TEST=Able to verify audio playback on Google/Rex with this change. Change-Id: Ia8dfc79e7e4d27828726145156c870733d716899 Signed-off-by: Eran Mitrani <mitrani@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66919 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-09-10mb/google/rex: Enable touchpadKapil Porwal
Enable touchpad for Google Rex. BUG=b:245866939 TEST=Build and boot to Google Rex. Verify touchpad works. Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: I49fdd72bf3350085e82411b95edcd6a9a09d2df5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67471 Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Shaunak Saha <shaunak.saha@intel.corp-partner.google.com>
2022-08-31Revert "mb/google/rex: Disable LID_SHUTDOWN"Subrata Banik
This reverts commit 47fee08fc3a383e14dc974754d6e463fa320badf. The required EC changes are now in place to revert this W/A that disables the LID based shutdown. BUG=b:243920003 TEST=No shutdown request has triggered while booting AP at depthcharge. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I5ae56912f030f6f0e3cb49282bbffc920fb389c0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67206 Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
2022-08-29drivers/i2c/tpm: Remove TI50_FIRMWARE_VERSION_NOT_SUPPORTEDReka Norman
This workaround was added since reading the firmware version on Ti50 versions < 0.0.15 will cause the Ti50 to become unresponsive. No one is using Ti50 this old anymore, so remove the workaround. BUG=b:224650720,b:236911319 TEST=Boot to OS on nivviks with Ti50 0.22.4. Check the log contains the firmware version: [INFO ] Firmware version: Ti50/D3C1 RO_B:0.0.26/- RW_B:0.22.4/ti50_common:v095c Change-Id: I3628b799e436a80d0512dabd356c4b2566ed600a Signed-off-by: Reka Norman <rekanorman@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67138 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2022-08-27mb/google/rex: Disable LID_SHUTDOWNSubrata Banik
This patch disables LID based shutdown requests. Google/Rex platform receives a forced shutdown request while booting to depthcharge due to EC wrongly detecting the LID is being closed. For now disable the LID based shutdown behaviour in depthcharge unless the EC issue gets resolved. BUG=b:243920003 TEST=Depthcharge no longer sees the force shutdown request now. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I03e33ea4d04dc48331d1cf98c47786b2a184c258 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67103 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2022-08-21mb/google/rex: Reshuffle CHROMEEC_* related configsEran Mitrani
1. Moved CHROMEEC_* to common (required for all boards) 2. added missing EC_GOOGLE_CHROMEEC_SKUID TEST=Verified with simics on RVP Change-Id: I26a01e5d1c78d4cd83b1aa53e68b2c3059da6061 Signed-off-by: Eran Mitrani <mitrani@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66762 Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-08-18mb/google/rex: Create 64MB AP Firmware binary for Proto 0Subrata Banik
This patch provides a mitigation path for having different size SPINOR parts across Rex board revisions. Rex Proto 0 only has 64MB SPINOR mounted on the board, and the plan is to use 32MB later with Proto 1 onwards. Hence, the idea here is to maintain a 32MB SPI Flash layout across all Rex board revisions, but the Proto 0 build only selects BOARD_ROMSIZE_KB_65536 config for adding padding at the end of the 32MB range. BUG=b:242825380 TEST=Able to create 64MB AP Firmware for Rex with below layout: SI_ALL: 0-9MB SI_BIOS: 9MB-32MB Padding/Unused: 32MB-64MB Additionally, able to hit CPU reset on MTLRVP (has 64MB SPINOR) with Rex AP Firmware binary. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ibcc2206456639ef4ff22e0c4069521e583be58cd Reviewed-on: https://review.coreboot.org/c/coreboot/+/66828 Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-08-12mb/google/rex: Add ACPI support for Type-C portsSubrata Banik
This patch backported from commit ba2e51bd496a (mb/google/brya: brya0: Add ACPI support for Type-C ports) for google/rex. BUG=b:224325352 TEST=Able to build Google/Rex and boot on MTLRVP. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: If0a9510784e8f62861ae4bc74805b1513a4865cb Reviewed-on: https://review.coreboot.org/c/coreboot/+/66538 Reviewed-by: Prashant Malani <pmalani@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
2022-08-02mb/google/rex: Enable CSE Lite SKUSubrata Banik
The first CSE Lite SKU is available, therefore enable the Kconfig option to have the CSE reboot the system into its RW FW during a cold boot. BUG=b:240228892 TEST=TBD Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I00ef4176cf08cbeed06e446cfe68f06cb1ea27b4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66287 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-23mb/google/rex: Add GBB related configsSubrata Banik
This patch adds more GBB related configs. Select `HAS_RECOVERY_MRC_CACHE` config. Additionally, move VBOOT_LID_SWITCH config under VBOOT config. TEST=Able to build the Google/Rex. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I28976200cbd70dc23f58868ee89c0ac700793be9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66007 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2022-07-22mb/google/rex: Add TPM device to Kconfig and devicetreeKapil Porwal
Add TPM device for Rex. Device details: I2C Controller/Bus = 4 I2C Slave Address = 0x50 GPE = GPE0_DW1_03/GPP_E03 BUG=b:224325352 TEST=Verified in emulator that there is no regression Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: Ifa3a5b503a203e3900049f27a54025156e22a285 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66014 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-22mb/google/rex: Enable EC_GOOGLE_CHROMEEC_BOARDID KconfigTarun Tuli
Enables the EC_GOOGLE_CHROMEEC_BOARDID feature so we can read board_id() on rex. TEST=Verified builds succeed and code is linked Change-Id: Id202019519fc4a05c80374bc97663e59fdca3d76 Signed-off-by: Tarun Tuli <taruntuli@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66018 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-07-14mb/google/rex: Add chip config for UART devicesSubrata Banik
This patch ensures LPSS UART 0 is used for the AP serial console as per Rex Proto 0 schematics dated 07/05. +-----------+-------------+-------------+ | INTERFACE | PCI (B:D:F) | DEVICE | +-----------+-------------+-------------+ | UART-0 | 0:0x1e:0 | For AP UART | +-----------+-------------+-------------+ | UART-1 | 0:0x1e:1 | NA | +-----------+-------------+-------------+ | UART-2 | 0:0x19:2 | NA | +-----------+-------------+-------------+ BUG=b:224325352 TEST=Able to get AP UART over LPSS UART0 using emulator. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ice0c81607c758e94d15ea19e346877776a3de7dd Reviewed-on: https://review.coreboot.org/c/coreboot/+/65668 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-07-14mb/google/rex: Add overridetree.cb for `rex0` variantSubrata Banik
This patch adds initial PCI device entries into the override devicetree. BUG=b:224325352 TEST=Able to build Google/Rex and verified on MTL emulator. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I16326747df46769f93813ce322ed8045449ffa85 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65784 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-07-01mb/google/rex: Redirect AP UART over LPSS UART 0Subrata Banik
This patch ensures AP UART messages are coming over LPSS UART 0 hence, select required kconfig and program both early and late UART RX/TX GPIOs accroding to the rex schematics dated 06/27. BUG=b:224325352 TEST=Able to see AP UART log over LPSS UART0. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I7daa8200d1a7cf825dfdfed538573efd57ab2d97 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65454 Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-01mb/google/rex: Add memory initEric Lai
Add memory init with placeholder to fill in required memory configuration parameters. DQ map and Rcomp can be auto probed by the FSP-M hence, kept it as default. BUG=b:224325352 TEST=util/abuild/abuild -p none -t google/rex -a -c max Able to boot till FSP-M/MRC using MTL simics. Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I5baa87411c28a20602eb5a7077f00664ccab3ade Reviewed-on: https://review.coreboot.org/c/coreboot/+/64850 Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-01mb/google/rex: Enable building for Chrome OSEric Lai
Enable building for Chrome OS and add associated ACPI configuration. BUG=b:224325352 TEST=util/abuild/abuild -p none -t google/rex -a -c max Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: I75cb2d30d699166a056ed9d3c0779816b733b0d2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64621 Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-01mb/google/rex: Enable ECEric Lai
Perform EC initialization in bootblock and ramstages. Add associated ACPI configuration. BUG=b:224325352 TEST=util/abuild/abuild -p none -t google/rex -a -c max Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I2ea934f32b34bc43650e20dd2736f4e652004dc2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64622 Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-01mb/google/rex: Enable ACPI and add ACPI tableEric Lai
Enable ACPI configuration and add DSDT ACPI table. BUG=b:224325352 TEST=util/abuild/abuild -p none -t google/rex -a -c max Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: I8374a9b528f8dff4e23b6bdb4d1368dfd2c79b8e Reviewed-on: https://review.coreboot.org/c/coreboot/+/64620 Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-01mb/google/rex: Add GPIO stubsEric Lai
Add stubbed out GPIO configuration and perform GPIO initialization during bootblock, romstage and ramstage. BUG=b:224325352 TEST=util/abuild/abuild -p none -t google/rex -a -c max Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: I51426f9557dafc357fc54a971b6f76fac5323e0a Reviewed-on: https://review.coreboot.org/c/coreboot/+/64593 Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-07-01mb/google/rex: Add MTL reference platformSubrata Banik
This commit is a stub for rex, which is a an Intel Meteor Lake-P reference platform. BUG=b:224325352 TEST=util/abuild/abuild -p none -t google/rex -a -c max Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I46bd8d47b370cacbe0a09bbeaccacf7f1d51d8b6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62969 Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-23 22:08:59 +0000