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2017-07-24google/reef: Configure EN_PP3300_DX_LTE on coralPatrick Georgi
BUG=b:63876329 BRANCH=none TEST=none Change-Id: I98c700d5b928c031129cf0138d22652a28d1ad1d Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/20752 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-07-24google/reef: copy gpio.c for coralPatrick Georgi
It requires changes to match the hardware. Except for the weak attributes that are now removed in coral's copy, the file is identical to the baseboard version. BUG=b:63876329 BRANCH=none TEST=none Change-Id: Ib0c5f0ecae9919f20631dacef0253416989fb011 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/20751 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-07-24Fix files with multiple newlines at the end.Martin Roth
Change-Id: Iaab26033e947cb9cf299faf1ce6d40a90a9facbe Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/20704 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-07-19google/snappy: Add keyboard backlight supportKevin Chiu
BUG=none BRANCH=reef TEST=emerge-snappy coreboot chromeos-bootimage and verify the keyboard backlight can be bright and alt+f6, alt+f7 function keys can be used. Change-Id: I6d06f72e1ccc66292b4e5f867314d84c309af885 Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/20633 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-12mainboard/google/snappy: Increase PL1 Min to 4.5WWisley Chen
Increase PL1 Min to 4.5W BUG=b:35585781 BRANCH=reef TEST=build, boot on snappy, and verified by thermal team. Change-Id: Ia55c5a57e1475fb605929cf33322728bd36295d4 Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/20473 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-07-01mainboards: Remove unused EC event for thermal overloadDuncan Laurie
The Chrome EC event for "thermal overload" was never implemented and is being repurposed as the EC event mask is out of free bits. Remove this from the boards that were enabling it. BUG=b:36024430 TEST=build coreboot for affected boards Change-Id: I6038389ad73cef8a57aec5041bbb9dea98ed2b6e Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/20424 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-06-05google/reef: Add coralPatrick Georgi
A new variant copied from reef. Allow override of the SKU. Change-Id: Ibe160e75aa23623812f0fb9121d1d8226afc00d8 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/20020 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-05-12mainboard/google/reef: Config needed GPIO for pull-up WALijian Zhao
This change is needed to minimize circuit level stress, by adjusting circuit voltage for proper operation. For mem config GPIO changes: To avoid leakge as those pins have internal 20K pull and 3.3K pull down on mainboard, change internal pull up to none. BUG=b:37998248 TEST=Boot up into OS and enter s0ix. Change-Id: Id82035d8e1fff9fbb8dd3b4125460cdf61a58488 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/19577 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-05-09google/sand: Add keyboard backlight supportKatherine Hsieh
BUG=None TEST=emerge-sand coreboot chromeos-bootimage and verify the keyboard backlight can be bright and alt+f6, alt+f7 function keys can be used. Change-Id: I86a35551a9348ff6ad26dfccd3b2786282d56069 Signed-off-by: Katherine Hsieh <Katherine.Hsieh@quantatw.com> Reviewed-on: https://review.coreboot.org/19479 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-05-08mb/google/reef: enable SAR and DSARWei-Ning Huang
Enable SAR and DSAR for reef. BUG=b:37612675 TEST=`emerge-reef coreboot` Change-Id: Ie0a59f8fcc9fb104328ee6d276ecab4193ec8eb8 Signed-off-by: Wei-Ning Huang <wnhuang@google.com> Reviewed-on: https://review.coreboot.org/19579 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-05-05mainboard/google/sand: Update DPTF parameters provided from thermal teamKatherine Hsieh
Update the DPTF parameters based on thermal test result. 1. Update DPTF CPU/TSR0/TSR1/TSR2 passive/critial trigger points. CPU passive point:83, critial point:99 TSR0 passive point:60, critial point:70 TSR1 passive point:50, critial point:90 TSR2 passive point:77, critial point:90 2. Update PL1/PL2 Min Power Limit/Max Power Limit Set PL1 min to 4W, max to 12W, and step size to 0.2W 3. Change thermal relationship table (TRT) setting. Change CPU Throttle Effect on CPU sample rate to 5secs Change CPU Effect on Temp Sensor 0 sample rate to 60secs The TRT of TCHG is TSR1, but real sensor is TSR2. sample rate to 30secs Change Charger Effect on Temp Sensor 2 sample rate to 30secs Change CPU Effect on Temp Sensor 2 sample rate to 120secs BUG=None TEST=build and boot on electro dut Change-Id: I0ea0bab7fa6b0ad75d9ddacbd7cd882f91e4b0db Signed-off-by: Katherine Hsieh <Katherine.Hsieh@quantatw.com> Reviewed-on: https://review.coreboot.org/19538 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-04-24mainboard/google/reef: Remove DRIVER_TPM_I2C_IRQDaniel Kurtz
DRIVER_TPM_I2C_IRQ has been removed. TPM_TIS_ACPI_INTERRUPT now specifies the TPM2 ACPI interrupt used by intel's tis_plat_irq_status() routine. BRANCH=none BUG=b:36786804 TEST=Boot reef w/ serial enabled firmware, verify verstage sees "cr50 TPM". Change-Id: If66a2a1d461a411e112589c84a434066d48b9399 Signed-off-by: Daniel Kurtz <djkurtz@chromium.org> Reviewed-on: https://review.coreboot.org/19410 Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2017-04-24mainboard/google/reef: Add TPM_TIS_ACPI_INTERRUPTDaniel Kurtz
TPM_TIS_ACPI_INTERRUPT specifies the TPM2 ACPI interrupt used by intel's tis_plat_irq_status() routine. BRANCH=none BUG=b:36786804 TEST=Boot reef w/ serial enabled firmware, verify verstage sees "cr50 TPM". Change-Id: Ic69add8a3ce35be64fb37db4ed40163f6144fc9c Signed-off-by: Daniel Kurtz <djkurtz@chromium.org> Reviewed-on: https://review.coreboot.org/19408 Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2017-04-24Kconfig: provide MAINBOARD_HAS_TPM_CR50 optionAaron Durbin
The CR50 TPM can do both SPI and I2C communication. However, there's situations where policy needs to be applied for CR50 generically regardless of the I/O transport. Therefore add MAINBOARD_HAS_TPM_CR50 to encompass that. Additionally, once the mainboard has selected CR50 TPM automatically select MAINBOARD_HAS_TPM2 since CR50 TPM is TPM 2.0. Change-Id: I878f9b9dc99cfb0252d6fef7fc020fa3d391fcec Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/19370 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins)
2017-04-13mainboard/google/reef: Configure sdcard card detect (CD) pin GPIO_177Venkateswarlu Vinjamuri
This configures GPIO_177 as native function. This enables OS to boot from sdcard. BUG=b:35648535 TEST=Check OS boot from sdcard. Change-Id: I73901d4a1b39752cbc452f3286d494587dac95d4 Signed-off-by: Venkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri@intel.com> Reviewed-on: https://review.coreboot.org/18948 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Vaibhav Shankar <vaibhav.shankar@intel.com>
2017-04-13mainboard/google/snappy: Increase weida touchscreen reset delayWisley Chen
Weida touchscreen controller needs 130 ms delay after reset BUG=b:35586513 BRANCH=reef TEST=Verified that touchscreen works on power-on and suspend/resume on snappy. Change-Id: I8418e742a69a2d6395baa2799a4da42a9bb5b312 Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/19245 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-04-05mainboard/google/reef: increase trackpad data hold timeAaron Durbin
Even though the i2c spec has no minimum data hold time in fast mode the trackpad vendor indicates 300ns is their minimum. However, the topology of the board uses FET isolation to cross voltage domains. Therefore, the default 300ns which should work isn't reflected on the device side of the voltage isolation circuit. Therefore, increase the data hold time to show an observed data hold time of more than 300ns on the device side. BUG=b:36469182 Change-Id: I1b70f2f53c5a29cc7cfd5035a71ca5811b3bcba0 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/19065 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-03-29mainboard/google/reef: turn off DMIC_CLK_B1 in S0ixSathyanarayana Nujella
Wake On Voice stream capture configuration is mono. It is sufficient to keep DMIC_CLK_A1 on in S0ix; so, turning off DMIC_CLK_B1. Power saving should be visible in the boards which has more than one DMIC connected. BUG=None BRANCH=None TEST=WoV and quad channel DMIC capture works Change-Id: Ic46d4c7b30b945eba47a05d78386f48e4a675a03 Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com> Reviewed-on: https://review.coreboot.org/19018 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Venkateswarlu V Vinjamuri <venkateswarlu.v.vinjamuri@intel.com> Tested-by: build bot (Jenkins)
2017-03-28vboot: Move remaining features out of vendorcode/google/chromeosJulius Werner
This patch attempts to finish the separation between CONFIG_VBOOT and CONFIG_CHROMEOS by moving the remaining options and code (including image generation code for things like FWID and GBB flags, which are intrinsic to vboot itself) from src/vendorcode/google/chromeos to src/vboot. Also taking this opportunity to namespace all VBOOT Kconfig options, and clean up menuconfig visibility for them (i.e. some options were visible even though they were tied to the hardware while others were invisible even though it might make sense to change them). CQ-DEPEND=CL:459088 Change-Id: I3e2e31150ebf5a96b6fe507ebeb53a41ecf88122 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/18984 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-28vboot: Assume EC_SOFTWARE_SYNC and VIRTUAL_DEV_SWITCH by defaultJulius Werner
The virtualized developer switch was invented five years ago and has been used on every vboot system ever since. We shouldn't need to specify it again and again for every new board. This patch flips the Kconfig logic around and replaces CONFIG_VIRTUAL_DEV_SWITCH with CONFIG_PHYSICAL_DEV_SWITCH, so that only a few ancient boards need to set it and it fits better with CONFIG_PHYSICAL_REC_SWITCH. (Also set the latter for Lumpy which seems to have been omitted incorrectly, and hide it from menuconfig since it's a hardware parameter that shouldn't be configurable.) Since almost all our developer switches are virtual, it doesn't make sense for every board to pass a non-existent or non-functional developer mode switch in the coreboot tables, so let's get rid of that. It's also dangerously confusing for many boards to define a get_developer_mode() function that reads an actual pin (often from a debug header) which will not be honored by coreboot because CONFIG_PHYSICAL_DEV_SWITCH isn't set. Therefore, this patch removes all those non-functional instances of that function. In the future, either the board has a physical dev switch and must define it, or it doesn't and must not. In a similar sense (and since I'm touching so many board configs anyway), it's annoying that we have to keep selecting EC_SOFTWARE_SYNC. Instead, it should just be assumed by default whenever a Chrome EC is present in the system. This way, it can also still be overridden by menuconfig. CQ-DEPEND=CL:459701 Change-Id: If9cbaa7df530580a97f00ef238e3d9a8a86a4a7f Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/18980 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-24mainboard/google/snappy: Update DPTF settingsWisley Chen
1. Remove CPU throttling effect of the charger sensor Refers Change-Id I267b6e07fa9def2c91ff9f6035f2d9437faf1965 (mb/google/reef: Remove CPU throttling effect of the charger sensor) to remove CPU throttling effect of the charger sensor since it's not relevant to throttle CPU based on the charger sensor. 2. Change TSR1 influence from 200 to 100 3. Change TSR2 sample period from 120s to 30s BUG=b:35585781 BRANCH=reef TEST=built, and verified on snappy by thermal team. Change-Id: Ic3fc51c4288b24f4e64950e5b148aed4495a1c3b Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/18950 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2017-03-22mainboard/google/reef: add nasher variantYH Lin
Create the initial Nasher variant which refers to the Reef. Nasher is APL board that derives from reference board Reef. BRANCH=master BUG=b:36389286 TEST=Build (as initial setup) Signed-off-by: YH Lin <yueherngl@chromium.org> Change-Id: I7962aa8246890149988c7f02dcd90d820df7b901 Reviewed-on: https://review.coreboot.org/18928 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-21google/pyro: Update DPTF settingsKevin Chiu
1. correct DPTF TCHG target device to TSR2 2. Refers Change-Id I267b6e07fa9def2c91ff9f6035f2d9437faf1965 (mb/google/reef: Remove CPU throttling effect of the charger sensor) to remove CPU throttling effect of the charger sensor since it's not relevant to throttle CPU based on the charger sensor. BUG=b:35586881 BRANCH=reef TEST=emerge-pyro coreboot Change-Id: I4801e0e612e0ddf90764ffe080c679818d33212a Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/18920 Tested-by: build bot (Jenkins) Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-21google/sand: Add Raydium touchscreen deviceKatherine Hsieh
We just support Raydium touchscreen instead of Elan. Thus we have to remove Elan touchscreen device and add Raydium touchsrcreen device. BUG=b:35775065 BRANCH=reef TEST=emerge-sand coreboot Change-Id: I7b33a29287dcb90e379b52cc93825f2988a0d3c9 Signed-off-by: Katherine Hsieh <Katherine.Hsieh@quantatw.com> Reviewed-on: https://review.coreboot.org/18789 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-20mainboard/google/snappy: Update _hid name for weida touchscreenWisley Chen
Change hid name to "WDHT0002" for Weida WDT8752 which is supported by standard hid i2c Linux driver. BUG=b:35586513 BRANCH=reef TEST=build, boot on snappy, and verified acpi node "WDHT0002" created. Change-Id: Ie0cc980aa427b6db1eb14eb7868718619bb1310f Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/18874 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2017-03-19mb/google/reef: Remove CPU throttling effect of the charger sensorSumeet Pawnikar
It's not relevant to throttle CPU based on the charger sensor. So, remove this CPU throttling effect. BUG=b:35908799 BRANCH=master TEST=Built and booted on Electro DUT Change-Id: I267b6e07fa9def2c91ff9f6035f2d9437faf1965 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/18852 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
2017-03-16mainboard/google/reef: Increase PL2 Max to 15WTim Chen
Update the DPTF parameters based on thermal test result. (ZHT_DPTF_DVT_v0.6_20170314.xlsx) 1. Increase PL2 Max to 15W. BUG=b:35583586 BRANCH=reef TEST=build and verify PL2 Max value on electro dut Change-Id: I13167e28267d5827d79a6bde31f077a01f2bd535 Signed-off-by: Tim Chen <Tim-Chen@quantatw.com> Reviewed-on: https://review.coreboot.org/18807 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-15mainboard/google/reef: Add FPF_STATUS FMAP regionAndrey Petrov
Add FPF_STATUS region under MISC_RW. The purpose of the region is to store FPF status. Change-Id: I2997b3d39a94bf444df51068f254edcf49c47afd Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/18773 Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-14google/sand: Remove support for tablet mode switchKatherine Hsieh
Sand is not convertible and no EC sensor sends event from EC to AP. That event default is tablet mode, we don't have to enable tablet event. Modify the ec.h, is based on <baseboard/ec.h> BUG=b:36108742 BRANCH=reef TEST=emerge-sand coreboot, boot to OS and touchpad and keyboard can work. Change-Id: I6b6b45b5b4daf2c430ed18130f39eab0bd9a9812 Signed-off-by: Katherine Hsieh <Katherine.Hsieh@quantatw.com> Reviewed-on: https://review.coreboot.org/18737 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-10google/sand: Add devicetree.cb file for sandKatherine Hsieh
It is a copy from baseboard/devicetree.cb (coreboot.org ToT) BUG=b:35775065 BRANCH=reef TEST=emerge-sand coreboot Change-Id: I5ba86e54ccfbf5af7bf0e9ad8fe7bf22020e48ee Signed-off-by: Katherine Hsieh <Katherine.Hsieh@quantatw.com> Reviewed-on: https://review.coreboot.org/18703 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-03-10mainboard/google/reef: Modify TCPU, TSR2 and TRT tableTim Chen
Update the DPTF parameters based on thermal test result. (ZHT_DPTF_EVT2_v0.5_20170306.xlsx) 1. Update DPTF TCPU critical trigger point. TCPU critical point: 105 2. Update DPTF TSR2 passive trigger point. TSR2 passive point: 58 3. Change thermal relationship table (TRT) setting. Change CPU Throttle Effect on CPU sample rate to 10secs. Change Charger Effect on Temp Sensor 2 sample rate to 30secs. Change CPU Effect on Temp Sensor 2 sample rate to 60secs. BUG=b:35583586 BRANCH=master TEST=build and boot on electro dut Change-Id: I85564ccdaf327eeaa13bf1f31d9a933609a21582 Signed-off-by: Tim Chen <Tim-Chen@quantatw.com> Reviewed-on: https://review.coreboot.org/18610 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-03-10mainboard/google/reef: Configure SDCARD card detect pinVenkateswarlu Vinjamuri
This configures GPIO_177 as an input pin for SDCARD card detect. This also changes the ownership of the pin from ACPI to GPIO driver. Assign the sdcard card detect pin in devicetree for reef variants. CQ-DEPEND=448173 BUG=chrome-os-partner:63070 TEST=None Change-Id: Ia8aef60bd7d0ea36afb39f76fab051aa46a2ed64 Signed-off-by: Venkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri@intel.com> Reviewed-on: https://review.coreboot.org/18497 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-09mainboard/google/reef: increase pre cbmem console size for Chrome OSAaron Durbin
verstage can be pretty chatty so bump the pre cbmem console size when building for Chrome OS so that all messages can be observed. BUG=b:35775104 BRANCH=reef TEST=Booted and noted no cutoff of console when sec data being saved. Change-Id: I0ce2976572dedf976f051c74a3014d282c3c5f4c Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/18679 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-03-09google/pyro: Update DPTF settingsKevin Chiu
1. Update DPTF TSR1 passive trigger points. TSR1 passive point: 50 2. Update DPTF PL1 Minimum PL1 min: 2.5W BUG=b:35586881 BRANCH=reef TEST=emerge-pyro coreboot Change-Id: Ia2634f40098d026c4d228fab4b7c05501c1ff05f Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/18699 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-03-08mainboard/google/snappy: Override USB2 phy settingWisley Chen
Fine tune USB2, need to override the following registers. port#1: PERPORTPETXISET=7 PERPORTTXISET=0 BUG=b:35858164 BRANCH=reef TEST=built, measured eye diagram on snappy, and reviewed by intel Change-Id: I461cf8f032b4e70abc9707e6cd3603a62cee448f Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/18590 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-02-25mainboard/google/reef: keep LPSS_UART2_TXD high in suspend stateAaron Durbin
The cr50 part on reef is connected to the SoC's UART lines. However, when the tx signal is low it causes an interrupt to fire on cr50. Therefore, keep the tx signal high in suspend state so that it doesn't cause an interrupt storm on cr50 which prevents cr50 from sleeping. BUG=chrome-os-partner:63283 BRANCH=reef TEST=s0ix no longer causes interrupt storm on cr50. Power consumption normal. Change-Id: Idaeb8e4427c1cec651122de76a43daa15dc54d0f Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/18491 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-02-22acpi: Add ACPI_ prefix to IRQ enum and struct namesFurquan Shaikh
This is done to avoid any conflicts with same IRQ enums defined by other drivers. BUG=None BRANCH=None TEST=Compiles successfully Change-Id: I539831d853286ca45f6c36c3812a6fa9602df24c Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/18444 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-02-20drivers/i2c: Use I2C HID driver for wacom devicesFurquan Shaikh
Wacom I2C driver does the same thing as I2C HID driver, other than defining macros for Wacom HID. Instead of maintaining two separate drivers providing the same functionality, update all wacom devices to use generic I2C HID driver. BUG=None BRANCH=None TEST=Verified that ACPI nodes for wacom devices are unchanged. Change-Id: Ibb3226d1f3934f5c3c5d98b939756775d11b792c Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/18401 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2017-02-20mainboard/{google,intel}: Change config option selectionFurquan Shaikh
Change config option selection from "config xyz default y" to "select xyz" if the config option has no dependencies. BUG=None BRANCH=None TEST=Verified that config option selection remains unchanged. Change-Id: I259ae40623b7f4d5589e2caa0988419ba4fefda4 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/18400 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2017-02-20mainboard/google/reef: Remove config DRIVERS_GENERIC_GPIO_REGULATORFurquan Shaikh
Since we are not using gpio regulators on reef anymore, remove the selection from Kconfig as well. BUG=None BRANCH=None TEST=Compiles successfully. Change-Id: Iae7d88dec3ac476d65b292f97a6ba3add71ce07a Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/18399 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2017-02-15mainboard/google/reef: add sand variantYH Lin
Create the initial Sand variant which refers to the Reef. Sand is APL board that derives from reference board Reef. BRANCH=master BUG=chrome-os-partner:62200 TEST=Build (as initial setup) Signed-off-by: YH Lin <yueherngl@chromium.org> Change-Id: Iba8c5653b6176676c759d2b48063f0c0c6cde625 Reviewed-on: https://review.coreboot.org/18324 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-02-13mainboard/google/snappy: Update DPTF settingsWisley Chen
Update DPTF parameters based on thermal team test result. 1. Update TSR2 trigger points. TSR2 passive point: 70, critical point: 90 2. Set PL2 Max to 15W. BUG=chrome-os-partner:61383 BRANCH=reef TEST=build, boot on snappy, and verified by thermal team Change-Id: I8d01d6c1d7eabd359ceb131f3cd10965d4ac2c42 Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/18318 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-02-11mainboard/google/reef: Increase PL1 sampling periodSumeet Pawnikar
Performance degradation seen with current PL1 throttling rate as 8 seconds for TSR1 sensor with Aquarium workload. After fine tuning PL1 throttling rate to 15 seconds, fps score improved. BUG=chrome-os-partner:60038 BRANCH=reef TEST=Built and tested on electro system Change-Id: I5cdebb08e00f0f28b88f1c6b2b1cafaeb8cdb453 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/18317 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Venkateswarlu V Vinjamuri <venkateswarlu.v.vinjamuri@intel.com>
2017-02-07mainboards/google/reef: Add support for tablet mode switch.Gwendal Grignou
Reef is a convertible add support for sending Tablet mode switch changes from EC to AP. Change-Id: I6dfddbfdb5a2ffbdfd77c5f49602bf68e9693a06 Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://review.coreboot.org/18277 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2017-02-04Revert "google/pyro: remove Wacom touchscreen probed flag"Kevin Chiu
Reason for revert: Pyro has two touchscreen sources: WACOM/ELAN. It will not have both touchscreen IC in one system at the same time. So the "probed" property of WACOM i2c device is mandatory to set for kernel to know whether it exists before driver initializes it. Otherwise in ELAN case, when driver fails to init WACOM i2c device, ACPI _OFF will be invoked to set GPIO#152 low to cut off power. BUG=chrome-os-partner:62371 BRANCH=reef TEST=emerge-pyro coreboot Change-Id: I30f467bd8720d959686dc14f7877e6bc11ea6213 Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/18291 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-02-03mainboard/google/snappy: Set PL2 override to 15000mWHarry Pan
This patch sets PL2 override value to 15W in RAPL registers. BUG=chrome-os-partner:62110 BRANCH=reef TEST=Apply new firmware to evaluate Octane benchmark score. Change-Id: I51734051586753677129314b5273fb275c74f5d2 Signed-off-by: Harry Pan <harry.pan@intel.com> Reviewed-on: https://review.coreboot.org/18283 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2017-01-31mainboard/google/reef: remove NHLT DMIC 1ch and 2ch configurationSathyanarayana Nujella
Apollolake boards should use DMIC-4ch configuration in Kernel side and use CaptureChannelMap in userspace to distinguish boards with different number of DMIC's. So, NHLT DMIC 1-ch & 2-ch endpoint configuration will not be required and hence removed. BUG=chrome-os-partner:60827 TEST=Verify internal mic capture TEST='arecord -Dhw:0,3 dmic_4ch.wav -f S16_LE -r 48000 -c 4 -d 10' works Change-Id: Ibe81290906c9e379ae49e437648ee9cd6f123ff8 Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com> Reviewed-on: https://review.coreboot.org/18252 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-01-31mainboard/google/reef: Set edge triggered interrupt for GPIO_22Vaibhav Shankar
EC sets the logic level based on outstanding wake events. When GPIO_22 is configured as a level triggered interrupt, the events are not cleared from the interrupt handler. Hence, we'd just be re-signalling over and over causing an interrupt storm upon lid open. So, GPIO_22 needs to be configured as EDGE_SINGLE instead of LEVEL. BUG=chrome-os-partner:62458 TEST=Lid close/open. check CPU usage using top. It should not show 70% CPU usage. Signed-off-by: Vaibhav Shankar <vaibhav.shankar@intel.com> Change-Id: I710a690578c6e5b63be34b7fbcb21c703ef56e3a Reviewed-on: https://review.coreboot.org/18267 Tested-by: build bot (Jenkins) Reviewed-by: Venkateswarlu V Vinjamuri <venkateswarlu.v.vinjamuri@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-01-29mainboard/google/snappy: Update WDT touchscreen deviceFurquan Shaikh
Export PowerResource for WDT touchscreen device. BUG=chrome-os-partner:62311, chrome-os-partner:60194, chrome-os-partner:62371 BRANCH=reef TEST=Compiles successfully. Change-Id: Icc5be170353753201d3571c39b50e29424d4d6d3 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/18240 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-01-29mainboard/google/pryo: Update touchscreen device ACPI nodesFurquan Shaikh
1. For ELAN, export reset GPIO as well as PowerResource 2. For WCOM, export PowerResource BUG=chrome-os-partner:62311, chrome-os-partner:60194, chrome-os-partner:62371 BRANCH=reef TEST=Verified that touchscreen works on pyro with WCOM device on power-on as well as after suspend/resume. Change-Id: I0306e24e19bf821cd3e08fdacc0d78b494c9a92f Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/18239 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-01-29i2c/generic: Allow GPIOs to be put in _CRS and PowerResource in ACPIFurquan Shaikh
Linux kernel expects that power management with ACPI should always be handled using PowerResource. However, some kernel drivers (e.g. ELAN touchscreen) check to see if reset gpio is passed in by the BIOS to decide whether the device loses power in suspend. Thus, until the kernel has a better way for drivers to query if device lost power in suspend, we need to allow passing in of GPIOs via _CRS as well as exporting PowerResource to control power to the device. Update mainboards to export reset GPIO as well as PowerResource for ELAN touchscreen device. BUG=chrome-os-partner:62311,chrome-os-partner:60194 BRANCH=reef TEST=Verified that touchscreen works on power-on as well as after suspend-resume. Change-Id: I3409689cf56bfddd321402ad5dda3fc8762e6bc6 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/18238 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2017-01-29mainboard/google/reef: Set IOSSTATE for trackpad I2C GPIOsVaibhav Shankar
I2C data (GPIO_132) and Clk (GPIO_133) lines are pulled low during standby states S3/S0ix. This causes leakage of power. To reduce the leakage, we have to pull these lines high during S3/S0ix. This is done by programming the IOSSTATE to HIz. Also note that we are using the internal pull ups to keep at SOC at 1.8V and the I2C lines are not floating. BUG=chrome-os-partner:62428,chrome-os-partner:61651 TEST=Enter S3/S0ix. Measure trackpad power. It should be less than 4mW. Also I2c lines should be pulled high in S3/S0ix. Change-Id: I5570ac37ec3cc41f6463dd6b858fdb56a20a1733 Signed-off-by: Vaibhav Shankar <vaibhav.shankar@intel.com> Reviewed-on: https://review.coreboot.org/18251 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2017-01-26google/pyro: Add USB2 phy setting overrideKevin Chiu
In order to pass type A USB2 eye diagram, USB2 port#0/#1 PHY register will need to be overridden. port#0: PERPORTPETXISET = 7 PERPORTTXISET = 1 IUSBTXEMPHASISEN = 3 PERPORTTXPEHALF = 0 port#1: PERPORTPETXISET = 7 PERPORTTXISET = 2 IUSBTXEMPHASISEN = 3 PERPORTTXPEHALF = 0 BUG=chrome-os-partner:59491 BRANCH=reef TEST=emerge-pyro coreboot Change-Id: I8e67a6f0192d1c0abf6ec4926c2a17e44c818948 Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/18229 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-01-26google/pyro: Disable Wacom touchscreen probedKevin Chiu
Wacom touchscreen is i2c hid device and it's the device that always exists. So no need to set "probed" property for it. BUG=chrome-os-partner:61513 BRANCH=reef TEST=emerge-pyro coreboot Change-Id: I27fe18ceadd03029b826e0237f80132eda1089b0 Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/18227 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-01-25google/pyro: Modify Wacom touchscreen IRQ type to level-triggeredKevin Chiu
Follow i2c-hid spec definition, level trigger interrupt is required for i2c-hid device. BUG=chrome-os-partner:61513 BRANCH=reef TEST=emerge-pyro coreboot Change-Id: Ia825bd0c898e71e2ee2bf411f117a49a8fb411b6 Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/18217 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-01-23google/pyro: Update DPTF settingsKevin Chiu
1. Update DPTF CPU/TSR1 passive trigger points. CPU passive point: 80 TSR1 passive point: 46 2. Update DPTF TRT Sample Period TSR1: 8s BUG=chrome-os-partner:62133 BRANCH=reef TEST=emerge-pyro coreboot Change-Id: I8fcf750ac17b8894ed3c8704eec62f5071d9cf24 Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/18174 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-01-22mainboard/google/reef: Increase TSR1 trigger pointTim Chen
Update the DPTF parameters based on thermal test result. (ZHT_DPTF_EVT2_v0.4_20170120.xlsx) 1. Update DPTF TSR1 passive trigger point. TSR1 passive point: 46 BUG=chrome-os-partner:60038 BRANCH=master TEST=build and boot on electro dut Change-Id: If35e4cf2dbf7c506534c52a052598f6204d5315a Signed-off-by: Tim Chen <Tim-Chen@quantatw.com> Reviewed-on: https://review.coreboot.org/18183 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-01-21mainboard/google/reef: remove internal pullups on PP1800_S railAaron Durbin
The PP1800_S rail is turned off in S3. However, enabling internal pullups on the pins which are connected to PP1800_S results in leakage into the P1800_S rail. Fix this by disabling the internal pullups on PP1800_S rail pins. BUG=chrome-os-partner:61968 BRANCH=reef TEST=measured leakage on PP1800_S rail. Gone with this patch. Change-Id: I5ae92b31c1a633f59d425f4105b8db1c9c18c808 Signed-off-by: Aaron Duribn <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/18189 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-01-20google/snappy: Add weida touchscreen supportWisley Chen
Add weida touchscreen as 2nd touchscreen source BUG=chrome-os-partner:61865 BRANCH=reef TEST=emerge-snappy coreboot, and verified that touchscreen works on snappy. Change-Id: If76312a62e97da9d5de18ad895e90ee6b0f0c6ae Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/18166 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-01-20google/snappy: Use exported GPIOs and ACPI regulator for touchscreenWisley Chen
ELAN touchscreen device expects firmware to export GPIOs and ACPI regulators for managing power to the device. Thus, provide the required ACPI elements for OS driver to properly manage this device. BUG=None BRANCH=None TEST=Verified that touchscreen works properly on boot-up and after suspend/resume. Change-Id: I78e0c35f60289afe338d140d90784a433ca534ae Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/18163 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-01-19mainboard/google/snappy: Disable unused devicesWisley Chen
The following devices i2c6, i2c7, spi1, spi2, uart3 are not used. BUG=none BRANCH=master TEST=emerge-snappy coreboot chromeos-bootimage Change-Id: I9bacdbdd194ce21686c1618494d113402f2bef6c Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/18140 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-01-19mainboard/google/reef: Ignore Audio DMIC IOSSTATEVaibhav Shankar
Audio DMIC PLL needs to be ON in S0ix to support Wake on Voice. This requires GPIO_79 and GPIO_80 to be configured as IGNORE IOSSTATE. So DMIC CLKs will be ON in S0ix. Change-Id: If91045a8664ce853366b670b9db38d620818fbab Signed-off-by: Vaibhav Shankar <vaibhav.shankar@intel.com> Reviewed-on: https://review.coreboot.org/18155 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-01-17Revert "mainboard/google/snappy: Add PowerResource for ELAN touchscreen"Martin Roth
This reverts commit 01ba8cf7 (mainboard/google/snappy: Add PowerResource for ELAN touchscreen) Change was out of date and broke the build. Change-Id: Id47631ece1172c3f93bf6f40b8686dfd728842a9 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/18158 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-01-17mainboard/google/reef: Ignore SPI IOSTANDBYLijian Zhao
SPI controller need to access flash descriptors/SFDP during s0ix exit, so all fast SPI IO can't be put into IOSTANDBY state. For reef, that will be FST_SPI_CLK_FB, GPIO_97, GPIO_99, GPIO_100, GPIO_103 and GPIO_106. BUG=chrome-os-partner:61370 BRANCH=reef TEST=Enter s0ix state in OS, after resume run flashrom to read SPI content. Change-Id: I5c59601ec00e93c03dd72a99a739add0950c6a51 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/18137 Tested-by: build bot (Jenkins) Reviewed-by: Vaibhav Shankar <vaibhav.shankar@intel.com> Reviewed-by: Venkateswarlu V Vinjamuri <venkateswarlu.v.vinjamuri@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-01-17mainboard/google/snappy: Add PowerResource for ELAN touchscreenWisley Chen
Define reset_gpio and enable_gpio for touchscreen device so that when kernel puts this device into D3, we put the device into reset. PowerResource _ON and _OFF routines are used to put the device into D0 and D3 states. BUG=chrome-os-partner:59034 BRANCH=master TEST=emerge-snappy coreboot chromeos-bootimage Change-Id: I08c05d06b2812a33b3fdff9b42b2a8e0653dd8b4 Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/17366 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2017-01-13google/pyro: Add ELAN touch screen supportKevin Chiu
Current fw does not create ACPI device for OS to recognize ELAN touchscreen. List the touch screen in the devicetree so that the correct ACPI device are created. BUG=chrome-os-partner:61803 BRANCH=reef TEST=emerge-pyro coreboot Change-Id: I9015fa63ef3aba74b682da3608a05ee49c4947c5 Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/18086 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-01-03google/snappy: Update DPTF settingsWisley Chen
1. Update DPTF TSR1/TSR2 passive/critial trigger points. TSR1 passive point:53, critial point:80 TSR2 passive point:90, critial point:100 2. Update PL1 Min to 4W and PL1 Max to 12W 3. Update thermal relationship table (TRT) setting. BUG=none BRANCH=master TEST=build, boot on snappy dut and verified by thermal team member. Change-Id: I8b4fb178daa7c2e4091a14779a125bd5e943d023 Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/17955 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-01-03mainboard/google/reef: Update DPTF parameters EVT1_v0.3Tim Chen
Update the DPTF parameters based on thermal test result. (ZHT_DPTF_EVT1_v0.3_20161227.xlsx) 1. Update DPTF CPU/TSR1/TSR2 passive/critial trigger points. CPU critical point:103 TSR1 passive point:45 TSR2 passive point:55, critical point:90 2. Change thermal relationship table (TRT) setting. Change CPU Throttle Effect on CPU sample rate to 3secs Change Charger Effect on Temp Sensor 2 sample rate to 60secs Change CPU Effect on Temp Sensor 1 sample rate to 8secs BUG=chrome-os-partner:60038 BRANCH=master TEST=build and boot on electro dut Change-Id: I3746750f7ea4a2e01153a36c28a5c33140c9e38c Signed-off-by: Tim Chen <Tim-Chen@quantatw.com> Reviewed-on: https://review.coreboot.org/17975 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-17google/reef: Use exported GPIOs and ACPI regulator for touchscreenFurquan Shaikh
ELAN touchscreen device expects firmware to export GPIOs and ACPI regulators for managing power to the device. Thus, provide the required ACPI elements for OS driver to properly manage this device. BUG=chrome-os-partner:60194 BRANCH=None TEST=Verified that touchscreen works properly on boot-up and after suspend/resume. Change-Id: I298ca5de9c0ae302309d87e3dffb65f9be1e882e Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17799 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-12-16drivers/i2c/generic: Allow mainboards to export reset and enable GPIOsFurquan Shaikh
Add power management type config option that allows mainboards to either: 1. Define a power resource that uses the reset and enable gpios to power on and off the device using _ON and _OFF methods, or 2. Export reset and enable GPIOs in _CRS and _DSD so that the OS can directly toggle the GPIOs as required. GPIO type needs to be updated in drivers_i2c_generic_config to use acpi_gpio type so that it can be used for both the above cases. BUG=chrome-os-partner:60194 BRANCH=None TEST=Verified that elan touchscreen works fine on reef using exported GPIOs. Change-Id: I4d76f193f615cfc4520869dedc55505c109042f6 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17797 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-12-15mainboard/google/reef: clear normal MRC cache on recovery retrainAaron Durbin
For Chrome OS the normal MRC cache should be cleared when a hardware retrain recovery request is observed. The reason is that since there are 2 different MRC cache slots there needs to be a mechanism which allows an end user make a system bootable again if the MRC settings happen to not allow the system to boot any longer. Therefore, one just needs to enter recovery with the hardware retrain flag and the system normal MRC cache slot will be invalidated. BUG=chrome-os-partner:60592 BRANCH=reef Change-Id: I6ad32ed0dd217d66404b77467a88689a06044544 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17871 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-12-15google/reef: Remove VARIANT_DIR definitionMartin Roth
VARIANT_DIR is defined in coreboot/Makefile.inc, so doesn't need to be defined in each mainboard. Change-Id: Ic93957b710e4a9863774de7fcf3bd006696b6aa1 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/17841 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-12-13mainboard/google/reef: implement phase enforcement pinAaron Durbin
On upcoming boards an optional pull up is applied on GPIO_10 to indicate if the board should have security features locked down for a shipping system. Provide a weak pull down so that all boards will indicate a logic 0 until the stronger pull up resistor is stuffed. BUG=chrome-os-partner:59951 BRANCH=reef Change-Id: I6f514a69bccd05ca02480f3c30d0ad503a955b1e Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17803 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-12-12google/pyro: Set PL2 override to 15000mWKevin Chiu
This patch sets PL2 override value to 15W in RAPL registers and sets DPTF PL2 Max to 15W BUG=none BRANCH=reef TEST=emerge-pyro coreboot Change-Id: Ibadf0fa442f556d018c249b1cf88e29c4d57c97f Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/17779 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-09mainboard/google/reef: fill in NHLT ACPI OEM header fieldsAaron Durbin
Fill in the NHLT ACPI OEM header fields to differentiate different audio solutions on a per board basis. This handles boards that share a firmware that are differentiated by the SKU id and boards that have their own firmware. For the latter, the Oem Table ID uses the VARIANT_DIR to differentiate. "reef" is always used for Oem ID which is treated as more of family in this case. iasl -d shows the following on reef: [00Ah 0010 6] Oem ID : "reef" [010h 0016 8] Oem Table ID : "reef" [018h 0024 4] Oem Revision : 00000008 BUG=chrome-os-partner:60494 BRANCH=reef Change-Id: I5daa6f0306bc05e812a8737ce61ee37177a36b76 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17772 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-12-09mainboard/google/reef: add board SKU'ing supportAaron Durbin
There are 2 gpios on reef-like boards that can be composed into a SKU. Add support for identifying the SKU value using the base 3 gpio logic. Also export the SKU information to the SMBIOS type 1 table. BUG=chrome-os-partner:59887,chrome-os-partner:60494 BRANCH=reef Change-Id: I8bb94207b0b7833d758054a817b655e248f1b239 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17771 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-12-08mainboard/google/reef: Set PL2 override to 15000mWSumeet Pawnikar
This patch sets PL2 override value to 15W in RAPL registers. BUG=chrome-os-partner:60535 TEST=Built, booted on reef and verified PL2 value. Change-Id: I4ff6a5e7b8686d97134846ee80cdac10916d58ef Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/17730 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-07mainboard/google/reef: adjust chromeos.fmd regionsAaron Durbin
- Drastically reduced RW_MRC_CACHE size to hold one update. Now that this area isn't changing after every S5 entry there's no need make it so large. - ELOG area reduced by 4KiB for subsequent area alignment. In practice this doesn't matter because the elog library only uses 4KiB bytes. 16KiB->12KiB is a nop. - Moved RW_NVRAM for subsequent alignment. - Most importantly, RW_SECTION_(A|B) are aligned to 64KiB boundaries and sized to 64KiB multiples. This ensures updates don't need a read-modify-write that could force a system into recovery if an inopportune power event occurred. BUG=chrome-os-partner:60492 BRANCH=reef Change-Id: I2a2e2797897c934db1a3f9627c6c13a9b2aad540 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17727 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-12-02google/pyro: set i2c bus timings by rise/fall timesKevin Chiu
Provide the rise and fall times for the i2c buses and let the library perform the necessary calculations for the i2c controller registers instead of manually tuning the values. BUG=chrome-os-partner:58112 BRANCH=master TEST=emerge-pyro coreboot Change-Id: I68be9b96dc731eb0084ee5e15921866818637e73 Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/17652 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-02mainboard/google/reef: Add all DMIC endpointsSathyanarayana Nujella
Independent of Board DMIC configuration, add all DMIC points i.e. add DMIC-1ch, DMIC-2ch, DMIC-4ch endpoints. This allows flexibility to userspace to open capture devices as needed. This is a temporary fix; once upper layers support choosing particular channels from 4-ch PCM stream, we will limit exposing only DMIC-4ch endpoint. BUG=chrome-os-partner:60444 BRANCH=none TEST=Verify All DMIC blobs are included Change-Id: I9729a3570c0668f3da4e7986291ebad6fe1de47a Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com> Reviewed-on: https://review.coreboot.org/17660 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-01mainboard/google/reef: allow variants to modify nhlt oem revisionAaron Durbin
In order to mirror the full flexibility of the NHLT library that allows a caller to set the OEM revision field in the ACPI header modify the variant callback to override the value. Change-Id: I16e539b350a50e3c163be1439c8637b82e53a759 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17651 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins)
2016-12-01lib/nhlt: add support for setting the oem_revisionAaron Durbin
In the ACPI header there's an OEM revision field that was previously just being implicitly set to 0. Allow for a board to provide a non-zero value for this field. Change-Id: Icd40c1c162c2645b3990a6f3361c592706251f82 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17650 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-11-30mainboard/google/snappy: Tune i2c frequency to 400 KhzWisley Chen
tune i2c devices clk for snappy: I2C0: audio I2C2: TPM H1 I2C3: elan touchscreen I2C4: elan touchpad I2C5: wacom digitizer BUG=chrome-os-partner:59034 BRANCH=master TEST=emerge-snappy coreboot chromeos-bootimage, and measured on EVT. audio: Freq. 393.7kHz Rise Time 58.8ns Fall time 12.11ns TPM H1: Freq. 398.8kHz Rise Time 31.71ns Fall time 13.28ns elan touchscreen: Freq. 390.5kHz Rise Time 235.7ns Fall time 37.64ns elan touchpad: Freq. 393.7kHz Rise Time 288.8ns Fall time 51.67ns wacom digitizer: Freq. 388.8kHz Rise Time 124.1ns Fall time 21.10ns Change-Id: Ib2be9e1575d4962476423eafa80f9bb10ba40e17 Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/17634 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-11-30mainboard/reef: Add RW_VAR_MRC_CACHEAndrey Petrov
Chop off 4kb block from RW_MRC_CACHE to store variable MRC cache. BUG=chrome-os-partner:57515 TEST=with patch series applied: cold reboot, make sure MRC is not updated. Do S3 suspend/resume cycle. Change-Id: I3e19fff9c9b20d6c73cbb13bfeec49e9a274bb72 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/17235 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-29google/pyro: disable unused devicesKevin Chiu
The following devices i2c5, i2c6, i2c7, spi1, spi2, uart3 are not used. BUG=none BRANCH=master TEST=emerge-pyro coreboot Change-Id: I3b7b96e72b82af1885926800ee99beff07755bbc Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/17589 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-11-29mainboard/google/snappy: Add digitizer device to devicetreeWisley Chen
BUG=chrome-os-partner:59034 BRANCH=none TEST=emerge-snappy coreboot chromeos-bootimage Change-Id: Ib99ae5357274ad0824d0989888dfddcb32ace7e2 Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/17618 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-29mainboard/google/reef: Set DPTF CPU passive temperature trip point to 95CSumeet Pawnikar
This pach sets the DPTF passive temperature trip point for CPU back to 95 degree celsius from 61 degree celsius as per previous thermal optimizations (https://review.coreboot.org/#/c/16766/). BUG=chrome-os-partner:60038 BRANCH=master TEST=built, booted on Reef and verified the passive trip point funtionality. Change-Id: I83ce69b19a94e4ea8ebedfc06f259579ed6dd5d3 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/17598 Tested-by: build bot (Jenkins) Reviewed-by: Venkateswarlu V Vinjamuri <venkateswarlu.v.vinjamuri@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-28mainboard/google/reef: Set PL1 MAX power limit value to 12WTim Chen
Set PL1 maximum power limit value back to 12W (https://review.coreboot.org/#/c/16596/) from 6W due to Intel's and thermal team's suggestion. BUG=chrome-os-partner:60038 BRANCH=master TEST=build, boot on electro dut and verify by thermal team member Change-Id: I57ae29180962724fde72d522caa542f0f21d5922 Signed-off-by: Tim Chen <Tim-Chen@quantatw.com> Reviewed-on: https://review.coreboot.org/17574 Tested-by: build bot (Jenkins) Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Venkateswarlu V Vinjamuri <venkateswarlu.v.vinjamuri@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-23google/pyro: Update DPTF settingsKevin Chiu
1. Update DPTF CPU/TSR1/TSR2 passive/critial trigger points. CPU passive point:57, critical point:90 TSR1 passive point:55, critial point:70 TSR2 passive point:65, critial point:80 2. Update DPTF TRT Sample Period. CPU: 5s TSR0: 50s TSR1: 55s TSR2: 120s BUG=none BRANCH=master TEST=emerge-pyro coreboot Change-Id: Ib1b4b31a49d9396b1c5c9dd8d0b9b9998d01744f Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/17552 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-20mainboard/google/reef: Update DPTF parameters provided from thermal teamTim Chen
Update the DPTF parameters based on thermal test result. 1. Update DPTF CPU/TSR0/TSR1/TSR2 passive/critial trigger points. CPU passive point:61 TSR0 passive point:120, critial point:125 TSR1 passive point:46, critial point:75 TSR2 passive point:100, critial point:125 2. Update PL1/PL2 Min Power Limit/Max Power Limit Set PL1 min to 3W, and max to 6W Set PL2 min to 8W 3. Change thermal relationship table (TRT) setting. Change CPU Throttle Effect on CPU sample rate to 80secs Change CPU Effect on Temp Sensor 0 sample rate to 120secs The TRT of TCHG is TSR1, but real sensor is TSR2. Change Charger Effect on Temp Sensor 2 sample rate to 120secs Change CPU Effect on Temp Sensor 2 sample rate to 120secs BUG=chrome-os-partner:60038 BRANCH=master TEST=build and boot on electro dut Change-Id: I7a701812cb45f51828a3cbb3343e03817645110e Signed-off-by: Tim Chen <Tim-Chen@quantatw.com> Reviewed-on: https://review.coreboot.org/17466 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-18google/chromeec: Add common infrastructure for boot-mode switchesFurquan Shaikh
Instead of defining the same functions for reading/clearing boot-mode switches from EC in every mainboard, add a common infrastructure to enable common functions for handling boot-mode switches if GOOGLE_CHROMEEC is being used. Only boards that were not moved to this new infrastructure are those that do not use GOOGLE_CHROMEEC or which rely on some mainboard specific mechanism for reading boot-mode switches. BUG=None BRANCH=None TEST=abuild compiles all boards successfully with and without ChromeOS option. Change-Id: I267aadea9e616464563df04b51a668b877f0d578 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17449 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner <jwerner@chromium.org>
2016-11-17google/snappy: Update DPTF settingsWisley Chen
1. Update DPTF CPU/TSR1/TSR2 passive/critial trigger points. CPU passive point:100, critical point:105 TSR1 passive point:48, critial point:65 TSR2 passive point:85, critial point:100 2. Update PL1/PL2 Min Power Limit/Max Power Limit Set PL1 min to 3W, and max to 6W Set PL2 min and max to 8W 3. Change thermal relationship table (TRT) setting. The TRT of TCHG is TSR1, but real sensor is TSR2. BRANCH=master BUG=none TEST= Compiled, verified by thermal team. Change-Id: Ib197c36eca88e3d05f632025cf3c238e1a2eae23 Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/17426 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-11-17mainboard/google/reef: disable unused devicesJagadish Krishnamoorthy
The following devices i2c6, i2c7, spi1, spi2, uart3 are not used. BUG=chrome-os-partner:59880 TEST=Boot to OS and lspci command should not list the above disabled devices. Change-Id: I819cdb34709703e6431b49446417ed9d6b3543cd Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy@intel.com> Reviewed-on: https://review.coreboot.org/17441 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-17mainboard/google/reef: set i2c bus timings by rise/fall timesAaron Durbin
Provide the rise and fall times for the i2c buses and let the library perform the necessary calculations for the i2c controller registers instead of manually tuning the values. BUG=chrome-os-partner:58889,chrome-os-partner:59565 Change-Id: I0c84658471d90309cdbb850e3128ae01780633af Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17397 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins)
2016-11-16mainboard/google/reef: Add proper DMIC endpoints based on DMIC config pinSathyanarayana Nujella
Reef board uses GPIO_17 as DMIC config pin. This pin distinguishes board with Quad DMIC's or Mono DMIC. This patch adds necessary DMIC endpoints to support either of those configurations. CQ-DEPEND=CL:*304339,CL:409774 BUG=chrome-os-partner:56918 BRANCH=none TEST=Verify Mono and Quad Channel DMIC record Change-Id: I5b2825b5f39f8962985a129f8ec65265fb18f0b2 Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com> Reviewed-on: https://review.coreboot.org/17158 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-11-11mainboard/google/snappy: Configure PERST pinWisley Chen
Configure GPIO 122 as PERST. This is to assert WiFi PERST during s0ix entry. BUG=chrome-os-partner:59034 BRANCH=master TEST=emerge-snappy coreboot chromeos-bootimage Change-Id: If2528632fe65c3ed1af19b2ce6f99e8be0cd1ad9 Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/17356 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-11-11google/snappy: update timing of sdmode togglingWisley Chen
Maxim98357a speaker amp requires BCLK & SFRM to be active and stable before it is unmuted. If there is a BLCK and no SFRM, it results in a pop sound. sdmode_delay property already exists which facilitates this configuration. This patch updates "sdmode_delay" to avoid pop sound. BUG=chrome-os-partner:59034 BRANCH=master TEST=emerge-snappy coreboot chromeos-bootimage Change-Id: Ic9095ae6812ba822c760229e69f5b27c6c244cdf Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/17361 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-11-11mainboard/google/snappy: Set PL1 override to 12000mWWisley Chen
Snappy is using APL SoC SKU's with 6W TDP max. As Reef, the energy calculation is wrong with the current VR solution. Experiments show that SoC TDP max (6W) can be reached when RAPL PL1 is set to 12W. Therefore, we've inserted 12W override after reading the fused value (6W) so that the system can reach the right performance level. BUG=chrome-os-partner:59034 BRANCH=master TEST=emerge-snappy coreboot chromeos-bootimage Change-Id: Idd702077cd05e2b43823542cb804b2d4b42f7116 Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/17362 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-11-10mainboard/google/reef: Add digitizer device to devicetreeFurquan Shaikh
BUG=chrome-os-partner:56246 BRANCH=None TEST=Verified kernel is able to talk to the device. Even without the digitizer, no issues observed with the kernel. Change-Id: I894a5f4cd8f6a51e641a2c8f7b1f682ab76712ae Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17343 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-11-10mainboard/google/reef: Tune digitizer I2C frequency to 400kHzFurquan Shaikh
This brings the I2C frequency down to 400kHz which is spec for fast I2C. BUG=chrome-os-partner:56246 BRANCH=None TEST=Verified frequency in kernel. Change-Id: Ib83c57eec8644903cb9c4b2ab50c94038eb690c1 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17342 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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