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2020-11-17mb/google/reef/variants/: add Naya NT6AN256T32AV-J2James Chao
BUG=b:172843935 BRANCH=coral TEST=emerge-coral coreboot chromeos-bootimage Signed-off-by: James Chao <james_chao@asus.corp-partner.google.com> Change-Id: I70195acc33218d3ad4c77acfdbc8f6ed93ab144e Reviewed-on: https://review.coreboot.org/c/coreboot/+/47382 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-13mb/google/reef: Configure IRQs as level triggered for HID over I2CKarthikeyan Ramasubramanian
As per HID over I2C Protocol Specification[1] Version 1.00 Section 7.4, the interrupt line used by the device is required to be level triggered. Hence, this change updates the configuration of the HID over I2C devices to be level triggered. References: [1] http://download.microsoft.com/download/7/d/d/7dd44bb7-2a7a-4505-ac1c-7227d3d96d5b/hid-over-i2c-protocol-spec-v1-0.docx BUG=b:172846122 TEST=./util/abuild/abuild Change-Id: Ifc6dd5f6549e7501f350afe8456a9a8096edcc25 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47425 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-10-13mb, soc/intel: Switch to using drivers/wifi/generic for Intel WiFi devicesFurquan Shaikh
This change switches all mainboard devices to use drivers/wifi/generic instead of drivers/intel/wifi chip driver for Intel WiFi devices. There is no need for two separate chip drivers in coreboot to handle Intel and non-Intel WiFi devices since the differences can be handled at runtime using the PCI vendor ID. This also allows mainboard to easily multi-source WiFi chips and still use the same firmware image without having to distinguish between the chip drivers. BUG=b:169802515 BRANCH=zork Change-Id: Ieac603a970cb2c9bf835021d1fb0fd07fd535280 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46035 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-09-22mb/google: Drop unneeded empty linesElyes HAOUAS
Change-Id: I4151d1a6ce94763432f307fbc8bc4afe229856ea Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44616 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-09-19apollolake boards: Enable CSE in devicetreeSubrata Banik
Enable CSE PCI device Bus 0: Device 0x0f: Function 0x00 to let Intel common cse block code can use this device. Calling me_read_config32(offset) function from ramstage: Without this CL : HECI: Global Reset(Type:1) Command BUG: me_read_config32 requests hidden 00:0f.0 PCI: dev is NULL! With this CL : HECI: Global Reset(Type:1) Command HECI: Global Reset success! Signed-off-by: Subrata Banik <subrata.banik@intel.com> Change-Id: I97d221ae52b4b03ecd859d708847ad77fe4bf465 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45469 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-06-28mb/google/reef/variants/: add Samsung K4F8E3S4HD-MGCL supportKevin Chiu
Add Samsung K4F8E3S4HD-MGCL DRAM support. DRAMID: 0x8 BUG=b:145094527 BRANCH=master TEST=emerge-snappy coreboot chromeos-bootimage Change-Id: Ic450c4abebfeaed050a7b8fcae74b87a148dd5cd Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42772 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-06-02drivers/vpd: rename VPD_ANY to VPD_RO_THEN_RWJonathan Zhang
Rename VPD_ANY to VPD_RO_THEN_RW, to reflect the VPD region search preference. Update all existing code references for VPD_ANY. Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Change-Id: I960688d1f6ab199768107ab73b8a7400a3fdf473 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41586 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-26apollolake: update processor power limits configurationSumeet R Pawnikar
Update processor power limit configuration parameters based on common code base support for Intel Apollo Lake SoC based platforms. BRANCH=None BUG=None TEST=Built and tested on octopus system Change-Id: I609744d165a53c8f91e42a67da1b972de00076a5 Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41233 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-11treewide: Remove "this file is part of" linesPatrick Georgi
Stefan thinks they don't add value. Command used: sed -i -e '/file is part of /d' $(git grep "file is part of " |egrep ":( */\*.*\*/\$|#|;#|-- | *\* )" | cut -d: -f1 |grep -v crossgcc |grep -v gcov | grep -v /elf.h |grep -v nvramtool) The exceptions are for: - crossgcc (patch file) - gcov (imported from gcc) - elf.h (imported from GNU's libc) - nvramtool (more complicated header) The removed lines are: - fmt.Fprintln(f, "/* This file is part of the coreboot project. */") -# This file is part of a set of unofficial pre-commit hooks available -/* This file is part of coreboot */ -# This file is part of msrtool. -/* This file is part of msrtool. */ - * This file is part of ncurses, designed to be appended after curses.h.in -/* This file is part of pgtblgen. */ - * This file is part of the coreboot project. - /* This file is part of the coreboot project. */ -# This file is part of the coreboot project. -# This file is part of the coreboot project. -## This file is part of the coreboot project. --- This file is part of the coreboot project. -/* This file is part of the coreboot project */ -/* This file is part of the coreboot project. */ -;## This file is part of the coreboot project. -# This file is part of the coreboot project. It originated in the - * This file is part of the coreinfo project. -## This file is part of the coreinfo project. - * This file is part of the depthcharge project. -/* This file is part of the depthcharge project. */ -/* This file is part of the ectool project. */ - * This file is part of the GNU C Library. - * This file is part of the libpayload project. -## This file is part of the libpayload project. -/* This file is part of the Linux kernel. */ -## This file is part of the superiotool project. -/* This file is part of the superiotool project */ -/* This file is part of uio_usbdebug */ Change-Id: I82d872b3b337388c93d5f5bf704e9ee9e53ab3a9 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41194 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-08mb/google/reef: add G2 TS support for snappyKevin Chiu
Add G2 GTCH7503 HID TS support spec from G2: G7500 / Ver.1.2 (3, April, 2018) BUG=b:155827595 BRANCH=master TEST=emerge-snappy coreboot Change-Id: I151bf141148f4f00b3dadd9c44ab3a6b7731cde1 Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41090 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-02acpi: Move ACPI table support out of arch/x86 (3/5)Furquan Shaikh
This change moves all ACPI table support in coreboot currently living under arch/x86 into common code to make it architecture independent. ACPI table generation is not really tied to any architecture and hence it makes sense to move this to its own directory. In order to make it easier to review, this change is being split into multiple CLs. This is change 3/5 which basically is generated by running the following command: $ git grep -iIl "arch/acpi" | xargs sed -i 's/arch\/acpi/acpi\/acpi/g' BUG=b:155428745 Change-Id: I16b1c45d954d6440fb9db1d3710063a47b582eae Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40938 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-04-06mb/google/reef: Use SPDX for GPL-2.0-only filesAngel Pons
Done with sed and God Lines. Only done for C-like code for now. Change-Id: I57e6790e49032902703ba84b68f285749aab2573 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40192 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-03-20drivers/generic/max98357a: Allow custom _HID from configAamir Bohra
Add HID field in max98357a_config and allow mainboards to set it. Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Change-Id: I22d2d078a9a4eb6ab330da8439737ff5133086d4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39286 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-18mainboard/google: Remove copyright noticesPatrick Georgi
They're listed in AUTHORS and often incorrect anyway, for example: - What's a "Copyright $year-present"? - Which incarnation of Google (Inc, LLC, ...) is the current copyright holder? - People sometimes have their editor auto-add themselves to files even though they only deleted stuff - Or they let the editor automatically update the copyright year, because why not? - Who is the copyright holder "The coreboot project Authors"? - Or "Generated Code"? Sidestep all these issues by simply not putting these notices in individual files, let's list all copyright holders in AUTHORS instead and use the git history to deal with the rest. Change-Id: I09cc279b1f75952bb397de2c3f2b299255163685 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39607 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2019-07-02mb/google/reef/variants/: fix Samsung K4F6E3S4HM-MGCJ densityKevin Chiu
Samsung K4F6E3S4HM-MGCJ density is 16Gb BUG=b:121228792 BRANCH=master TEST=emerge-snappy coreboot chromeos-bootimage MemTotal: 8041964kB in /proc/meminfo Change-Id: Ie8ecd82b92d4e82d3955cf773febca30f6280a5e Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33795 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-06-21mb/google/snappy: Remove unneeded 'else'Elyes HAOUAS
'else' is not needed after a 'break' or 'return'. Change-Id: I7b6c319a58b9f4f47de19336d18d00b73d3d3772 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33335 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Vlado Cibic Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-03-08coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)Julius Werner
This patch is a raw application of find src/ -type f | xargs sed -i -e 's/IS_ENABLED\s*(CONFIG_/CONFIG(/g' Change-Id: I6262d6d5c23cabe23c242b4f38d446b74fe16b88 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31774 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-11-27mainboard/google/reef: Bump mainboard mem versionKane Chen
This change is to bump fsp_memory_mainboard_version in order to trigger MRC full training BUG=b:119481870 CQ-DEPEND=CL:*716558 BRANCH=reef, coral TEST=make sure MRC retraining is triggered and the MRC cache is updated to newer version. Change-Id: I92463045f7a808fb25aaa7a2d5f6fcde36dfb458 Signed-off-by: Kane Chen <kane.chen@intel.com> Reviewed-on: https://review.coreboot.org/c/29647 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-08Move compiler.h to commonlibNico Huber
Its spreading copies got out of sync. And as it is not a standard header but used in commonlib code, it belongs into commonlib. While we are at it, always include it via GCC's `-include` switch. Some Windows and BSD quirk handling went into the util copies. We always guard from redefinitions now to prevent further issues. Change-Id: I850414e6db1d799dce71ff2dc044e6a000ad2552 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/28927 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-10-06soc/intel/common, mb/google, mb/siemens: Use lower case x for RXDFurquan Shaikh
In order to make the macro name consistent for all PAD_CFG1_IOSSTATE_* macros, this change uses lower case x for *RXD*. It helps avoid confusion when using the macros. Change-Id: I6b1ce259ed184bcf8224dff334fcf0a0289f1788 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/28924 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-09drivers/vpd: Add VPD supportPatrick Rudolph
VPD reference: https://chromium.googlesource.com/chromiumos/platform/vpd/+/master/README.md Copy ChromeOS VPD driver to add support for VPD without CROMEOS. Possible use case: * Storing calibration data * Storing MAC address * Storing serial * Storing boot options + Now it's possible to define the VPD space by choosing one of the following enums: VPD_ANY, VPD_RW, VPD_RO. + CHROMEOS selects now VPD as part of it. + VPD is implemented as driver. Change-Id: Id9263bd39bf25d024e93daa57053fefcb1adc53a Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/25046 Reviewed-by: David Hendricks <david.hendricks@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-06soc/intel/common/block: Add common chip config blockSubrata Banik
Adding common chip config structure which will be used to return data to common code. When common code requires soc data, code used to fetch entire soc config structure. With this change, common code will only get the data/structure which is required by common code and not entire config. For now, adding i2c, gspi and lockdown configuration which will be used by common code. BUG=none BRANCH=b:78109109 TEST=compile code for APL/SKL/CNL. Boot using SKL/APL/CNL and check values are returned properly using common structure. Change-Id: I7f1671e064782397d3ace066a08bf1333192b21a Signed-off-by: Subrata Banik <subrata.banik@intel.com> Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/26189 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Hannah Williams <hannah.williams@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-25mb/google/reef: fix indention in memory.cAaron Durbin
In cbdbf018 (mb/google/reef/variants/: Add new memory ID) a new memory configuration entry was added. However, it was using spaces for indention. Correct that. Change-Id: Iaf788b0ad8a6ef3b001e7f29a6710e6e8f731ecf Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/26513 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-05-24mb/google/reef: Remove unused DPTF_CPU_ACTIVE_ACx definesSumeet Pawnikar
ApolloLake based reef platform is fan-less design. We do not need these DPTF_CPU_ACTIVE_ACx defines. Removing these from all reef variants as those are not being used. Change-Id: Id3cb7f7826a5e02cf447c70ab5cdc9b5d86982ca Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/26468 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-19mb/google/reef/variants/: Add new memory IDren kuo
Add a new RAM ID of memrory PN:K4F6E3S4HM-MGCJ BUG=b:78491470 TEST= emerge-coral coreboot chromeos-bootimage. Change-Id: Ic40e36ab222572945f8588eb3df063e4fe0dbeb5 Signed-off-by: Ren Kuo <Ren.Kuo@quantatw.com> Reviewed-on: https://review.coreboot.org/26365 Reviewed-by: Ren Kuo <ren.kuo@quantatw.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-11mainboard/google/coral: Override VBT selection for epauletteren kuo
Current VBT setting for T8 is only 1ms which is under Innolux N116BCA-EA1 panel's spec. Modify T8 to 100ms. (Innolux's panel's spec requires T8 needs to be greater than 80ms BUG=b:78541692 BRANCH=master TEST=emerge-coral depthcharge coreboot chromeos-bootimage Run on DUT and check panel sequence meets spec. Change-Id: I5f9103aca7871095a828a74cd6a97e1951adb81f Signed-off-by: Ren Kuo <Ren.Kuo@quantatw.com> Reviewed-on: https://review.coreboot.org/26214 Reviewed-by: Ren Kuo <ren.kuo@quantatw.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-11mb/google/reef/variants/: Add new memory IDren kuo
Add a new RAM ID of memrory PN:MT53E512M32D2NP BUG=b:78491470 TEST= emerge-coral coreboot chromeos-bootimage. Signed-off-by: Ren Kuo <Ren.Kuo@quantatw.com> Change-Id: I855702c2850887df74941e00da69322124557498 Reviewed-on: https://review.coreboot.org/26213 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Ren Kuo <ren.kuo@quantatw.com>
2018-05-09drivers/intel/gma, soc/intel/common: improve cooperationPatrick Georgi
Instead of both featuring their own VBT loaders, use a single one. It's the compression-enabled one from soc/intel/common, but moved to drivers/intel/gma. The rationale (besides making all the Kconfig fluff easier) is that drivers/intel/gma is used in some capacity on all platforms that load a VBT, while soc/intel/common's VBT code is for use with FSP. BUG=b:79365806 TEST=GOOGLE_FALCO and GOOGLE_CHELL both build, exercising both affected code paths. Change-Id: I8d149c8b480e457a4f3e947f46d49ab45c65ccdc Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/26039 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-03mainboard/google/reef: Remove tablet mode switch supportMartin Roth
The _SB.DPTF.TPET ACPI code attached to EC_ENABLE_TABLET_EVENT doesn't exist in the apollo lake code. Remove it from reef as part of the cleanup to update to the new version of IASL. This was in commit 4f803ac28f4 (mainboards/google/reef: Add support for tablet mode switch.) Change-Id: Ic10c418ddc708c1aed87ad4a9861f04d32445116 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/25982 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-24compiler.h: add __weak macroAaron Durbin
Instead of writing out '__attribute__((weak))' use a shorter form. Change-Id: If418a1d55052780077febd2d8f2089021f414b91 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/25767 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2018-04-16Revert "mb/google/reef/sand: Override USB2 phy settings"Katherine Hsieh
This reverts commit aef0d6b0a7ec867ee29acf9e1c695be27626f239. This commit can only pass far-end USB eye diagram but will fail on near-end. Confirmed with Intel we should revert it. Change-Id: I2eb1d5ddb05ca6bbf6512edf48e3e0d8396ce6a7 Signed-off-by: Katherine Hsieh <Katherine.Hsieh@quantatw.com> Reviewed-on: https://review.coreboot.org/25651 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-04-13Revert "mb/google/reef: Override USB2 phy settings"Tim Chen
This reverts commit 70ba1b7e78930acca578114cdadcbcec367730e8. This commit can only pass far-end USB eye diagram but will fail on near-end. Confirmed with Intel we should revert it. Change-Id: I6de44d5240393409d9ec5835a9de0c23453300f7 Signed-off-by: Tim Chen <tim-chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/25630 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-13Revert "mb/google/coral: add usb2 phy setting override for some variants"Tim Chen
This reverts commit 06e3e1f055593bd2e2906f43040a703bc471cde4. This commit can only pass far-end USB eye diagram but will fail on near-end. Confirmed with Intel we should revert it. Change-Id: Ie987061e27996b0acc8345bf9aadb42d2c940808 Signed-off-by: Tim Chen <tim-chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/25629 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-16soc/intel/apollolake and mainboards: Use pcie_rp_clkreq_pin arrayFurquan Shaikh
This change uses an array pcie_rp_clkreq_pin for accepting CLKREQ# from mainboards instead of defining a separate property for each root port. This allows us to use memcpy to copy the entire array into FSP params as well as new properties for PCIe root ports can be added as arrays in future CLs. BUG=b:74633273 BRANCH=reef,coral Change-Id: Ifa05f1e38fcfd95063ec327712e472cdbd12dbb7 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/25186 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-03-06google/snappy: enhance CCD type-A USB 2.0 phy strengthKevin Chiu
Alan(11")/BigDaddy(14") right type-A(port#2), CCD(port#4) are occasionally undetectable. USB 2.0 phy needs an override to enhance drive strength. right type-A port#2 PERPORTPETXISET: 4 PERPORTTXISET: 4 IUSBTXEMPHASISEN: 1 PERPORTTXPEHALF: 0 CCD port#4 PERPORTPETXISET: 7 PERPORTTXISET: 7 IUSBTXEMPHASISEN: 1 PERPORTTXPEHALF: 0 BUG=b:72922816 BRANCH=reef TEST=emerge-snappy coreboot Change-Id: I2b18c11709280d00ec3a6ef10f93a416acb4fb45 Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/24969 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-03-01mb/google/reef/sand: Override USB2 phy settingsKatherine Hsieh
Sometimes the USB device is not detected. USB2 port#1 and #4 PHY register need to be overridden. port#1: PERPORTPETXISET = 4 PERPORTTXISET = 4 IUSBTXEMPHASISEN= 1 PERPORTTXPEHALF= 0 port#4: PERPORTPETXISET = 7 PERPORTTXISET = 7 IUSBTXEMPHASISEN= 1 PERPORTTXPEHALF= 0 BUG=b:72623892 BRANCH=master TEST=emerge-sand coreboot chromeos-bootimage Change-Id: I4051aefbec4583bb1f8babec08fdbeb27f749769 Signed-off-by: Katherine Hsieh <Katherine.Hsieh@quantatw.com> Reviewed-on: https://review.coreboot.org/23879 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-01mb/google/reef: Override USB2 phy settingsTim Chen
Sometimes the USB device is not detected. USB2 port#1 and #4 PHY register need to be overridden. port#1: PERPORTPETXISET = 4 PERPORTTXISET = 4 IUSBTXEMPHASISEN= 1 PERPORTTXPEHALF= 0 port#4: PERPORTPETXISET = 7 PERPORTTXISET = 7 IUSBTXEMPHASISEN= 1 PERPORTTXPEHALF= 0 BUG=b:72623892 BRANCH=master TEST=emerge-reef coreboot chromeos-bootimage Change-Id: Iab782ac6dfd81af839fff0e60e2b2460ce722733 Signed-off-by: Tim Chen <Tim-Chen@quantatw.com> Reviewed-on: https://review.coreboot.org/23878 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-01mb/google/coral: add usb2 phy setting override for some variantsSheng-Liang Pan
Due to there are some chances USB devices can not be detected. USB2 port#1 and #4 PHY register need to be overridden for variants Santa/Lava/Blue/Bruce/Astronaut. port#1: PERPORTPETXISET = 4 PERPORTTXISET = 4 IUSBTXEMPHASISEN= 1 PERPORTTXPEHALF= 0 port#4: PERPORTPETXISET = 7 PERPORTTXISET = 7 IUSBTXEMPHASISEN= 1 PERPORTTXPEHALF= 0 BUG=b:72623892 BRANCH=master TEST=emerge-coral coreboot chromeos-bootimage Change-Id: I401905685cc3078df657919b162272c3de320296 Signed-off-by: Pan Sheng-Liang <Sheng-Liang.Pan@quantatw.com> Reviewed-on: https://review.coreboot.org/23881 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-02-12google/snappy: enhance BigDaddy USB#2 2.0 strengthKevin Chiu
Fine tune 14" BigDaddy USB#2 2.0 strength: PERPORTPETXISET: 7 PERPORTTXISET: 1 IUSBTXEMPHASISEN: 3 PERPORTTXPEHALF: 0 this value could have USB#2 2.0 EA/function pass. BUG=b:72922816 BRANCH=reef TEST=emerge-snappy coreboot Change-Id: I0ea1b966b7c02c95bf0ea1138a5629fd3b576439 Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/23649 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-01-30chromeec: Decouple EC tablet event and TBMC deviceFurquan Shaikh
This change decouples EC tablet event and TBMC device by guarding TBMC definition and notification using EC_ENABLE_TBMC_DEVICE. It allows mainboards to use tablet events without having to define a TBMC device. BUG=b:72554519 Change-Id: Ie38b6d68486e8e644dd0d6d406def3ae7fdb5152 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/23461 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2018-01-23mb/google/reef,sand: Set S0ix lazy wake maskJenny TC
Enable S0ix wake mask programming from coreboot using unified host event programming interface. Lazy s0ix wake mask helps to configure s0ix wake mask during boot and EC sets the wake mask during S0ix entry. BRANCH=none BUG=b:63969337 TEST=verify masks with ec hostevent command on S0, S3, S5 and S0ix Change-Id: If56d1de5d1157c8cf9c418e3a9d2396ffcfcb0fd Signed-off-by: Jenny TC <jenny.tc@intel.com> Reviewed-on: https://review.coreboot.org/21610 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-12-15mb/google/snappy: add reset pin for Melfas touch controllerKevin Chiu
Melfas kernel TS driver (melfas_mip4.c) will look up "ce" GPIO during driver probe in ACPI _DSD. But FW does not report "ce-gpios" but "enable-gpios" in _DSD. Kernel will obtain GPIO from _CRS by index "0" without ID. Melfas driver does not have separate condition for MIT-410 so driver will set TS IC power off in probe. FW now may need to add back "reset" pin in order to hack this condition to let Melfas driver get "useless" GPIO so TS IC power (VTSP) will be not off during driver probe by itself. BUG=b:70149336 BRANCH=reef TEST=emerge-snappy coreboot Change-Id: Icf0451ff0c3df97cb2474e30542a2f46ba67d82a Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/22858 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-08mb/google/reef: provide override GPIO table in coralChris Wang
Allow overriding specific GPIOs by SKU ID. Override two GPIO settings for nasher to save the power consumption when the system in S0ix. Change as below: AVS_DMIC_CLK_A1: IGNORE -> Tx1RXDCRx0. AVS_DMIC_CLK_B1: IGNORE -> Tx1RXDCRx0. BUG=b:69025557 BRANCH=master TEST=compile/verify the power consumption change from ~150mW to ~100mW on clamshell SKU and from ~200mW to ~100mW for convertible SKU. Change-Id: I9e0674f206426fddb3947273754774b310106334 Signed-off-by: Chris Wang <chriswang@ami.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/22752 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-12-02google/reef: Fix whitespace inconsistency in coral codePatrick Georgi
BUG=none BRANCH=none TEST=none Change-Id: I4e61f1327027c5100773e2b837f439a939807e72 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/22662 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-12-02google/reef: add more USB tuning for coral variantsPatrick Georgi
Lava numbers are in. BUG=b:69990330 BRANCH=none TEST=verified that USB signal is within spec Change-Id: I7416ec8d058271700ebe43f8d92af61c6c0d6b42 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/22661 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ren Kuo <ren.kuo@quantatw.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-23src/mainboard: Fix various typosJonathan Neuschäfer
These typos were found through manual review and grep. Change-Id: Ia5a9acae4fbe2627017743106d9326a14c99a225 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/22525 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-11-10mainboard/google/coral: power off EN_PP3300_DX_LTE_SOC when entering S5Ben Chan
On Astronaunt, after the system enters the S5 power state, there is a 10-second timeout before the system transitions the power state from S5 to G3. The EN_PP3300_DX_LTE_SOC signal, which is controlled by GPIO_78 on the APL platform, remains on during that period. If the system is powered back on before going to G3, the built-in modem won't go through a power cycle as EN_PP3300_DX_LTE_SOC is never de-asserted. Keeping the modem, and indirectly the SIM, powered during a quick system power cycle may sometimes be undesirable. For instance, we would like a SIM with PIN lock enabled to require unlocking each time the system is powered on. After the SIM receives a PIN, it may remain unlocked until its next power cycle. Also, it is often desirable to power cycle the modem when the system goes through a power cycle. For instance, a user may power cycle the system to recover a wedged modem. BUG=b:68365029 TEST=Tested the following on an Astronaunt device: 1. Verify that the modem is powered on after the system boots from cold. 2. Suspend the system to S0ix. Verify that the modem remains powered on when the system is in S0ix. After the system goes back to S0, verify that the SIM with PIN lock enabled doesn't request unlocking, and the modem can quickly reconnect to a network. 3. Configure the system to suspend to S3 instead of S0ix, and then repeat (2). 4. Perform a quick system power cycle, verify that the modem is powered cycle and the SIM with PIN lock enabled requests unlocking. Change-Id: Ie60776d5d9ebc6a69aa9e360bd882f455265dfa2 Signed-off-by: Ben Chan <benchan@chromium.org> Reviewed-on: https://review.coreboot.org/22415 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-11-06mainboard/google/coral: Override VBT selection for astronautren kuo
Current VBT setting for T8 is only 1ms which is under Innolux N116BCA-EA1 panel's spec. Modify T8 to 100ms. (Innolux's panel's spec requires T8 needs to be greater than 80ms) CQ-DEPEND=CL:*496012 BUG=b:67756548 BRANCH=master TEST=emerge-coral depthcharge coreboot chromeos-bootimage Run on DUT and check panel sequence meets spec. Change-Id: I580567decfccd78366c37181255015ac2cd76493 Signed-off-by: Ren Kuo <Ren.Kuo@quantatw.com> Reviewed-on: https://review.coreboot.org/22306 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ren Kuo <ren.kuo@quantatw.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-11-02mainboard/google/coral: Override VBT selection for santaTim Chen
Current VBT setting for T8 is only 1ms which is under Innolux N116BCA-EA1 panel's spec. Modify T8 to 100ms. (Innolux's panel's spec requires T8 needs to be greater than 80ms) BUG=b:67756548 BRANCH=master TEST=emerge-coral depthcharge coreboot chromeos-bootimage Run on DUT and check panel sequence meets spec. CQ-DEPEND=CL:*493633 Change-Id: I7934b0f6d40b15796c55d360995c5eb0c5049222 Signed-off-by: Tim Chen <Tim-Chen@quantatw.com> Reviewed-on: https://review.coreboot.org/22294 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-01mainboard/google/coral: Update touchscreen device ACPI nodesSheng-Liang Pan
For Raydium, export reset GPIO as well as PowerResource. Let EN_PP3300_TOUCHSCREEN signal will goes to low at S3 mode. BUG=b:67879912 BRANCH=coral TEST=emerge-coral coreboot Change-Id: Ibf501b40ecfc957fd8be7ebffd2357dfa0e07757 Signed-off-by: Pan Sheng-Liang <Sheng-Liang.Pan@quantatw.com> Reviewed-on: https://review.coreboot.org/22252 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-10-31mainboard/google/snappy: Update touchscreen device ACPI nodesKevin Chiu
For MELFAS/Raydium, export reset GPIO as well as PowerResource BUG=b:68141940 BRANCH=reef TEST=emerge-snappy coreboot Change-Id: I1915ff8207502b80ecba6b63ce2ce1b866faf4c4 Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/22146 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-23mainboard/google/coral: Add USB2 phy setting override for Astronautren kuo
In order to pass type C USB2 eye diagram for sku Astronaut, USB2 port#1 PHY register needs to be overridden. sku ID:0,1 Astronaut (USB) port#1: PERPORTPETXISET = 7 PERPORTTXISET = 2 sku ID:61,62 Astronaut (LTE) port#1: PERPORTPETXISET = 7 PERPORTTXISET = 5 BUG=b:68120012 BRANCH=master TEST=emerge-coral coreboot chromeos-bootimage Change-Id: Icf5c9e5f4dae15630ec4d6ca6648cae78ca910c6 Signed-off-by: Ren Kuo <ren.kuo@quantatw.com> Reviewed-on: https://review.coreboot.org/22135 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-18google/snappy: Override USB2 strength by SKUIDKevin Chiu
14" BigDaddy needs to override USB2 TxiSet additionally to enhance driving strength. Otherwise EA test will fail on USB2 eye pattern. BUG=b:67820719 BRANCH=reef TEST=emerge-snappy coreboot Change-Id: I674c121a71866a5d44439eeb49e07f917d816de8 Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/22037 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-16google/reef: Add more special cases for coral nasherPatrick Georgi
BUG=b:65386429 BRANCH=none TEST=panel lights up Change-Id: I9871969314b9b64bee2b20332e35bfc6fbd2ddda Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/22002 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-10-06mainboard/google/reef: Override VBT selection in coralPatrick Georgi
Change-Id: I7fd667b1cf0b7c2a5e4ab7ac7748d9636a52ae54 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/21725 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-10-05mb/google/reef: Cache EC's SKU ID on CoralPatrick Georgi
Change-Id: I1925f51d63290b8d08366b622d5df3aab3a7484e Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/21737 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2017-09-27Coral: Add Synaptics touchpad supportPeggy Chuang
We need support two touchpad for Robo project, so adding Synaptices touchpad to coral. BUG=b:63134907 TEST=Compiled, verified by ODM Change-Id: If5a650338d5a7e6f01e9525d28588b871d390e50 Signed-off-by: Peggy Chuang <peggychuang@ami.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/21696 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-26mb/google/*: Use newly added Chrome EC boardid functionFurquan Shaikh
Instead of duplicating code across multiple mainboards, use newly added helper function to read boardid from Chrome EC. Change-Id: I1671c0a0b87d0c4c45da5340e8f17a4a798317ca Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/21682 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-26google/snappy: Override SKU ID by VPDKevin Chiu
Since snappy PCB may have over 9 SKU and current GPIO board ID GP16/GP17 is insufficient to use. Using VPD to control could prevent H/W change. BUG=b:65339688 BRANCH=reef TEST=emerge-snappy coreboot Change-Id: I55ab741354797e022dd945da9c8499ee5e041316 Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/21533 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-09-26mainboard/google/reef: expose sku strapping helper functionAaron Durbin
variant_board_sku() callback exists to allow some of the variants to report the sku id differently based on board implementation. However, there are cases where there are multiple ways to encode the sku id, but the original way should be used as a fallback. As such expose a helper function, sku_strapping_value(), such that there isn't code duplication for the common fallback case. BUG=b:65339688 Change-Id: I1e917733eb89aebc41a483e2001a02acfda31bf4 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/21645 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-09-13google/snappy: Update EC keyboard backlight flag by SKU IDKevin Chiu
Set AP SKU ID by ec command EC_CMD_SET_SKU_ID to update EC keyboard backlight flag. BUG=b:65359225 BRANCH=reef TEST=emerge-snappy coreboot Change-Id: I1153aa0b89250c55f311dd93a01fcef47afd7292 Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/21400 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-28google/Bruce: Add Raydium touch screen supportSheng-Liang Pan
Current coreboot does not create ACPI device for OS to recognize Raydium touchscreen. List the touch screen in the devicetree so that the correct ACPI device are created. BUG=b:64705535 BRANCH=master TEST=emerge-coral coreboot Change-Id: Ifdea897ef66dd10f29a8a0e72f9406d316fbe8c7 Signed-off-by: Pan Sheng-Liang <Sheng-Liang.Pan@quantatw.com> Reviewed-on: https://review.coreboot.org/21233 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-25mainboard/google/coral: Add USB2 phy setting override for SantaTim Chen
In order to pass type C USB2 eye diagram for sku Santa, USB2 port#1 PHY register needs to be overridden. port#1: PERPORTPETXISET = 7 PERPORTTXISET = 2 BUG=b:64880573 BRANCH=master TEST=emerge-coral coreboot chromeos-bootimage Change-Id: I07c0b7b0f08263a348befb7d6fd8d01028314470 Signed-off-by: Tim Chen <Tim-Chen@quantatw.com> Reviewed-on: https://review.coreboot.org/21199 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-24mb/google/coral: Copy devicetree.cb from baseboardTim Chen
It is a copy from baseboard/devicetree.cb (coreboot.org ToT) BUG=b:64880573 BRANCH=master TEST=emerge-coral coreboot chromeos-bootimage Change-Id: I5db730c1974a96547fe7fda63689b7c5bfaefc66 Signed-off-by: Tim Chen <Tim-Chen@quantatw.com> Reviewed-on: https://review.coreboot.org/21130 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-21google/snappy: Add Raydium touch screen supportKevin Chiu
Current coreboot does not create ACPI device for OS to recognize Raydium touchscreen. List the touch screen in the devicetree so that the correct ACPI device are created. BUG=b:64821783 BRANCH=reef TEST=emerge-snappy coreboot Change-Id: I8852e38f01f82b80c2c9718b93baf5894dbd745b Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/21083 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-08-21google/snappy: Add MELFAS touch screen supportKevin Chiu
Current coreboot does not create ACPI device for OS to recognize MELFAS touchscreen. List the touch screen in the devicetree so that the correct ACPI device are created. BUG=b:64779224 BRANCH=reef TEST=emerge-snappy coreboot Change-Id: If2bc910d641e0cf2b120ed883c5788542959f568 Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/21067 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-08-17mainboard/google/coral: Add keyboard backlight supportSheng-Liang Pan
BUG=b:64705535 BRANCH=master TEST=emerge-coral coreboot chromeos-bootimage and verify the keyboard backlight can be bright and alt+f6, alt+f7 function keys can be used. Change-Id: I777247a6b58d3d50b72f12ca2fcab49a06ed5431 Signed-off-by: Pan Sheng-Liang <Sheng-Liang.Pan@quantatw.com> Reviewed-on: https://review.coreboot.org/21027 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-08-15google/coral: Fetch SKU ID from ECPatrick Georgi
BUG=b:64468585 BRANCH=none TEST=with the other sku-id related patches applied, coreboot obtains the right SKU ID from EC Change-Id: I96a0e030bbc5f1c98165e70353340c413f8dc352 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/20947 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-07-24google/reef: Configure EN_PP3300_DX_LTE on coralPatrick Georgi
BUG=b:63876329 BRANCH=none TEST=none Change-Id: I98c700d5b928c031129cf0138d22652a28d1ad1d Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/20752 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-07-24google/reef: copy gpio.c for coralPatrick Georgi
It requires changes to match the hardware. Except for the weak attributes that are now removed in coral's copy, the file is identical to the baseboard version. BUG=b:63876329 BRANCH=none TEST=none Change-Id: Ib0c5f0ecae9919f20631dacef0253416989fb011 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/20751 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-07-24Fix files with multiple newlines at the end.Martin Roth
Change-Id: Iaab26033e947cb9cf299faf1ce6d40a90a9facbe Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/20704 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-07-19google/snappy: Add keyboard backlight supportKevin Chiu
BUG=none BRANCH=reef TEST=emerge-snappy coreboot chromeos-bootimage and verify the keyboard backlight can be bright and alt+f6, alt+f7 function keys can be used. Change-Id: I6d06f72e1ccc66292b4e5f867314d84c309af885 Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/20633 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-12mainboard/google/snappy: Increase PL1 Min to 4.5WWisley Chen
Increase PL1 Min to 4.5W BUG=b:35585781 BRANCH=reef TEST=build, boot on snappy, and verified by thermal team. Change-Id: Ia55c5a57e1475fb605929cf33322728bd36295d4 Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/20473 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-07-01mainboards: Remove unused EC event for thermal overloadDuncan Laurie
The Chrome EC event for "thermal overload" was never implemented and is being repurposed as the EC event mask is out of free bits. Remove this from the boards that were enabling it. BUG=b:36024430 TEST=build coreboot for affected boards Change-Id: I6038389ad73cef8a57aec5041bbb9dea98ed2b6e Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/20424 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-06-05google/reef: Add coralPatrick Georgi
A new variant copied from reef. Allow override of the SKU. Change-Id: Ibe160e75aa23623812f0fb9121d1d8226afc00d8 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/20020 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-05-12mainboard/google/reef: Config needed GPIO for pull-up WALijian Zhao
This change is needed to minimize circuit level stress, by adjusting circuit voltage for proper operation. For mem config GPIO changes: To avoid leakge as those pins have internal 20K pull and 3.3K pull down on mainboard, change internal pull up to none. BUG=b:37998248 TEST=Boot up into OS and enter s0ix. Change-Id: Id82035d8e1fff9fbb8dd3b4125460cdf61a58488 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/19577 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-05-09google/sand: Add keyboard backlight supportKatherine Hsieh
BUG=None TEST=emerge-sand coreboot chromeos-bootimage and verify the keyboard backlight can be bright and alt+f6, alt+f7 function keys can be used. Change-Id: I86a35551a9348ff6ad26dfccd3b2786282d56069 Signed-off-by: Katherine Hsieh <Katherine.Hsieh@quantatw.com> Reviewed-on: https://review.coreboot.org/19479 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-05-05mainboard/google/sand: Update DPTF parameters provided from thermal teamKatherine Hsieh
Update the DPTF parameters based on thermal test result. 1. Update DPTF CPU/TSR0/TSR1/TSR2 passive/critial trigger points. CPU passive point:83, critial point:99 TSR0 passive point:60, critial point:70 TSR1 passive point:50, critial point:90 TSR2 passive point:77, critial point:90 2. Update PL1/PL2 Min Power Limit/Max Power Limit Set PL1 min to 4W, max to 12W, and step size to 0.2W 3. Change thermal relationship table (TRT) setting. Change CPU Throttle Effect on CPU sample rate to 5secs Change CPU Effect on Temp Sensor 0 sample rate to 60secs The TRT of TCHG is TSR1, but real sensor is TSR2. sample rate to 30secs Change Charger Effect on Temp Sensor 2 sample rate to 30secs Change CPU Effect on Temp Sensor 2 sample rate to 120secs BUG=None TEST=build and boot on electro dut Change-Id: I0ea0bab7fa6b0ad75d9ddacbd7cd882f91e4b0db Signed-off-by: Katherine Hsieh <Katherine.Hsieh@quantatw.com> Reviewed-on: https://review.coreboot.org/19538 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-04-13mainboard/google/reef: Configure sdcard card detect (CD) pin GPIO_177Venkateswarlu Vinjamuri
This configures GPIO_177 as native function. This enables OS to boot from sdcard. BUG=b:35648535 TEST=Check OS boot from sdcard. Change-Id: I73901d4a1b39752cbc452f3286d494587dac95d4 Signed-off-by: Venkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri@intel.com> Reviewed-on: https://review.coreboot.org/18948 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Vaibhav Shankar <vaibhav.shankar@intel.com>
2017-04-13mainboard/google/snappy: Increase weida touchscreen reset delayWisley Chen
Weida touchscreen controller needs 130 ms delay after reset BUG=b:35586513 BRANCH=reef TEST=Verified that touchscreen works on power-on and suspend/resume on snappy. Change-Id: I8418e742a69a2d6395baa2799a4da42a9bb5b312 Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/19245 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-04-05mainboard/google/reef: increase trackpad data hold timeAaron Durbin
Even though the i2c spec has no minimum data hold time in fast mode the trackpad vendor indicates 300ns is their minimum. However, the topology of the board uses FET isolation to cross voltage domains. Therefore, the default 300ns which should work isn't reflected on the device side of the voltage isolation circuit. Therefore, increase the data hold time to show an observed data hold time of more than 300ns on the device side. BUG=b:36469182 Change-Id: I1b70f2f53c5a29cc7cfd5035a71ca5811b3bcba0 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/19065 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-03-29mainboard/google/reef: turn off DMIC_CLK_B1 in S0ixSathyanarayana Nujella
Wake On Voice stream capture configuration is mono. It is sufficient to keep DMIC_CLK_A1 on in S0ix; so, turning off DMIC_CLK_B1. Power saving should be visible in the boards which has more than one DMIC connected. BUG=None BRANCH=None TEST=WoV and quad channel DMIC capture works Change-Id: Ic46d4c7b30b945eba47a05d78386f48e4a675a03 Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com> Reviewed-on: https://review.coreboot.org/19018 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Venkateswarlu V Vinjamuri <venkateswarlu.v.vinjamuri@intel.com> Tested-by: build bot (Jenkins)
2017-03-24mainboard/google/snappy: Update DPTF settingsWisley Chen
1. Remove CPU throttling effect of the charger sensor Refers Change-Id I267b6e07fa9def2c91ff9f6035f2d9437faf1965 (mb/google/reef: Remove CPU throttling effect of the charger sensor) to remove CPU throttling effect of the charger sensor since it's not relevant to throttle CPU based on the charger sensor. 2. Change TSR1 influence from 200 to 100 3. Change TSR2 sample period from 120s to 30s BUG=b:35585781 BRANCH=reef TEST=built, and verified on snappy by thermal team. Change-Id: Ic3fc51c4288b24f4e64950e5b148aed4495a1c3b Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/18950 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2017-03-22mainboard/google/reef: add nasher variantYH Lin
Create the initial Nasher variant which refers to the Reef. Nasher is APL board that derives from reference board Reef. BRANCH=master BUG=b:36389286 TEST=Build (as initial setup) Signed-off-by: YH Lin <yueherngl@chromium.org> Change-Id: I7962aa8246890149988c7f02dcd90d820df7b901 Reviewed-on: https://review.coreboot.org/18928 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-21google/pyro: Update DPTF settingsKevin Chiu
1. correct DPTF TCHG target device to TSR2 2. Refers Change-Id I267b6e07fa9def2c91ff9f6035f2d9437faf1965 (mb/google/reef: Remove CPU throttling effect of the charger sensor) to remove CPU throttling effect of the charger sensor since it's not relevant to throttle CPU based on the charger sensor. BUG=b:35586881 BRANCH=reef TEST=emerge-pyro coreboot Change-Id: I4801e0e612e0ddf90764ffe080c679818d33212a Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/18920 Tested-by: build bot (Jenkins) Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-21google/sand: Add Raydium touchscreen deviceKatherine Hsieh
We just support Raydium touchscreen instead of Elan. Thus we have to remove Elan touchscreen device and add Raydium touchsrcreen device. BUG=b:35775065 BRANCH=reef TEST=emerge-sand coreboot Change-Id: I7b33a29287dcb90e379b52cc93825f2988a0d3c9 Signed-off-by: Katherine Hsieh <Katherine.Hsieh@quantatw.com> Reviewed-on: https://review.coreboot.org/18789 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-20mainboard/google/snappy: Update _hid name for weida touchscreenWisley Chen
Change hid name to "WDHT0002" for Weida WDT8752 which is supported by standard hid i2c Linux driver. BUG=b:35586513 BRANCH=reef TEST=build, boot on snappy, and verified acpi node "WDHT0002" created. Change-Id: Ie0cc980aa427b6db1eb14eb7868718619bb1310f Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/18874 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2017-03-19mb/google/reef: Remove CPU throttling effect of the charger sensorSumeet Pawnikar
It's not relevant to throttle CPU based on the charger sensor. So, remove this CPU throttling effect. BUG=b:35908799 BRANCH=master TEST=Built and booted on Electro DUT Change-Id: I267b6e07fa9def2c91ff9f6035f2d9437faf1965 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/18852 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
2017-03-16mainboard/google/reef: Increase PL2 Max to 15WTim Chen
Update the DPTF parameters based on thermal test result. (ZHT_DPTF_DVT_v0.6_20170314.xlsx) 1. Increase PL2 Max to 15W. BUG=b:35583586 BRANCH=reef TEST=build and verify PL2 Max value on electro dut Change-Id: I13167e28267d5827d79a6bde31f077a01f2bd535 Signed-off-by: Tim Chen <Tim-Chen@quantatw.com> Reviewed-on: https://review.coreboot.org/18807 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-14google/sand: Remove support for tablet mode switchKatherine Hsieh
Sand is not convertible and no EC sensor sends event from EC to AP. That event default is tablet mode, we don't have to enable tablet event. Modify the ec.h, is based on <baseboard/ec.h> BUG=b:36108742 BRANCH=reef TEST=emerge-sand coreboot, boot to OS and touchpad and keyboard can work. Change-Id: I6b6b45b5b4daf2c430ed18130f39eab0bd9a9812 Signed-off-by: Katherine Hsieh <Katherine.Hsieh@quantatw.com> Reviewed-on: https://review.coreboot.org/18737 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-10google/sand: Add devicetree.cb file for sandKatherine Hsieh
It is a copy from baseboard/devicetree.cb (coreboot.org ToT) BUG=b:35775065 BRANCH=reef TEST=emerge-sand coreboot Change-Id: I5ba86e54ccfbf5af7bf0e9ad8fe7bf22020e48ee Signed-off-by: Katherine Hsieh <Katherine.Hsieh@quantatw.com> Reviewed-on: https://review.coreboot.org/18703 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-03-10mainboard/google/reef: Modify TCPU, TSR2 and TRT tableTim Chen
Update the DPTF parameters based on thermal test result. (ZHT_DPTF_EVT2_v0.5_20170306.xlsx) 1. Update DPTF TCPU critical trigger point. TCPU critical point: 105 2. Update DPTF TSR2 passive trigger point. TSR2 passive point: 58 3. Change thermal relationship table (TRT) setting. Change CPU Throttle Effect on CPU sample rate to 10secs. Change Charger Effect on Temp Sensor 2 sample rate to 30secs. Change CPU Effect on Temp Sensor 2 sample rate to 60secs. BUG=b:35583586 BRANCH=master TEST=build and boot on electro dut Change-Id: I85564ccdaf327eeaa13bf1f31d9a933609a21582 Signed-off-by: Tim Chen <Tim-Chen@quantatw.com> Reviewed-on: https://review.coreboot.org/18610 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-03-10mainboard/google/reef: Configure SDCARD card detect pinVenkateswarlu Vinjamuri
This configures GPIO_177 as an input pin for SDCARD card detect. This also changes the ownership of the pin from ACPI to GPIO driver. Assign the sdcard card detect pin in devicetree for reef variants. CQ-DEPEND=448173 BUG=chrome-os-partner:63070 TEST=None Change-Id: Ia8aef60bd7d0ea36afb39f76fab051aa46a2ed64 Signed-off-by: Venkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri@intel.com> Reviewed-on: https://review.coreboot.org/18497 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-09google/pyro: Update DPTF settingsKevin Chiu
1. Update DPTF TSR1 passive trigger points. TSR1 passive point: 50 2. Update DPTF PL1 Minimum PL1 min: 2.5W BUG=b:35586881 BRANCH=reef TEST=emerge-pyro coreboot Change-Id: Ia2634f40098d026c4d228fab4b7c05501c1ff05f Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/18699 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-03-08mainboard/google/snappy: Override USB2 phy settingWisley Chen
Fine tune USB2, need to override the following registers. port#1: PERPORTPETXISET=7 PERPORTTXISET=0 BUG=b:35858164 BRANCH=reef TEST=built, measured eye diagram on snappy, and reviewed by intel Change-Id: I461cf8f032b4e70abc9707e6cd3603a62cee448f Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/18590 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-02-25mainboard/google/reef: keep LPSS_UART2_TXD high in suspend stateAaron Durbin
The cr50 part on reef is connected to the SoC's UART lines. However, when the tx signal is low it causes an interrupt to fire on cr50. Therefore, keep the tx signal high in suspend state so that it doesn't cause an interrupt storm on cr50 which prevents cr50 from sleeping. BUG=chrome-os-partner:63283 BRANCH=reef TEST=s0ix no longer causes interrupt storm on cr50. Power consumption normal. Change-Id: Idaeb8e4427c1cec651122de76a43daa15dc54d0f Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/18491 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-02-22acpi: Add ACPI_ prefix to IRQ enum and struct namesFurquan Shaikh
This is done to avoid any conflicts with same IRQ enums defined by other drivers. BUG=None BRANCH=None TEST=Compiles successfully Change-Id: I539831d853286ca45f6c36c3812a6fa9602df24c Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/18444 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-02-20drivers/i2c: Use I2C HID driver for wacom devicesFurquan Shaikh
Wacom I2C driver does the same thing as I2C HID driver, other than defining macros for Wacom HID. Instead of maintaining two separate drivers providing the same functionality, update all wacom devices to use generic I2C HID driver. BUG=None BRANCH=None TEST=Verified that ACPI nodes for wacom devices are unchanged. Change-Id: Ibb3226d1f3934f5c3c5d98b939756775d11b792c Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/18401 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2017-02-15mainboard/google/reef: add sand variantYH Lin
Create the initial Sand variant which refers to the Reef. Sand is APL board that derives from reference board Reef. BRANCH=master BUG=chrome-os-partner:62200 TEST=Build (as initial setup) Signed-off-by: YH Lin <yueherngl@chromium.org> Change-Id: Iba8c5653b6176676c759d2b48063f0c0c6cde625 Reviewed-on: https://review.coreboot.org/18324 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-02-13mainboard/google/snappy: Update DPTF settingsWisley Chen
Update DPTF parameters based on thermal team test result. 1. Update TSR2 trigger points. TSR2 passive point: 70, critical point: 90 2. Set PL2 Max to 15W. BUG=chrome-os-partner:61383 BRANCH=reef TEST=build, boot on snappy, and verified by thermal team Change-Id: I8d01d6c1d7eabd359ceb131f3cd10965d4ac2c42 Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/18318 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>