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Current coreboot does not create ACPI device for OS to recognize Raydium
touchscreen.
List the touch screen in the devicetree so that the correct ACPI device
are created.
BUG=b:64821783
BRANCH=reef
TEST=emerge-snappy coreboot
Change-Id: I8852e38f01f82b80c2c9718b93baf5894dbd745b
Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/21083
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Current coreboot does not create ACPI device for OS to recognize MELFAS
touchscreen.
List the touch screen in the devicetree so that the correct ACPI device
are created.
BUG=b:64779224
BRANCH=reef
TEST=emerge-snappy coreboot
Change-Id: If2bc910d641e0cf2b120ed883c5788542959f568
Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/21067
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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BUG=b:64705535
BRANCH=master
TEST=emerge-coral coreboot chromeos-bootimage and verify the keyboard
backlight can be bright and alt+f6, alt+f7 function keys can be used.
Change-Id: I777247a6b58d3d50b72f12ca2fcab49a06ed5431
Signed-off-by: Pan Sheng-Liang <Sheng-Liang.Pan@quantatw.com>
Reviewed-on: https://review.coreboot.org/21027
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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BUG=b:64468585
BRANCH=none
TEST=with the other sku-id related patches applied, coreboot obtains the
right SKU ID from EC
Change-Id: I96a0e030bbc5f1c98165e70353340c413f8dc352
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/20947
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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BUG=b:63876329
BRANCH=none
TEST=none
Change-Id: I98c700d5b928c031129cf0138d22652a28d1ad1d
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/20752
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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It requires changes to match the hardware. Except for the weak
attributes that are now removed in coral's copy, the file is identical
to the baseboard version.
BUG=b:63876329
BRANCH=none
TEST=none
Change-Id: Ib0c5f0ecae9919f20631dacef0253416989fb011
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/20751
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Change-Id: Iaab26033e947cb9cf299faf1ce6d40a90a9facbe
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20704
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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BUG=none
BRANCH=reef
TEST=emerge-snappy coreboot chromeos-bootimage and verify the keyboard
backlight can be bright and alt+f6, alt+f7 function keys can be used.
Change-Id: I6d06f72e1ccc66292b4e5f867314d84c309af885
Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/20633
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Increase PL1 Min to 4.5W
BUG=b:35585781
BRANCH=reef
TEST=build, boot on snappy, and verified by thermal team.
Change-Id: Ia55c5a57e1475fb605929cf33322728bd36295d4
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/20473
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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The Chrome EC event for "thermal overload" was never implemented and
is being repurposed as the EC event mask is out of free bits.
Remove this from the boards that were enabling it.
BUG=b:36024430
TEST=build coreboot for affected boards
Change-Id: I6038389ad73cef8a57aec5041bbb9dea98ed2b6e
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/20424
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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A new variant copied from reef.
Allow override of the SKU.
Change-Id: Ibe160e75aa23623812f0fb9121d1d8226afc00d8
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/20020
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This change is needed to minimize circuit level stress, by adjusting
circuit voltage for proper operation.
For mem config GPIO changes:
To avoid leakge as those pins have internal 20K pull and 3.3K pull down
on mainboard, change internal pull up to none.
BUG=b:37998248
TEST=Boot up into OS and enter s0ix.
Change-Id: Id82035d8e1fff9fbb8dd3b4125460cdf61a58488
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/19577
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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BUG=None
TEST=emerge-sand coreboot chromeos-bootimage and verify the keyboard
backlight can be bright and alt+f6, alt+f7 function keys can be used.
Change-Id: I86a35551a9348ff6ad26dfccd3b2786282d56069
Signed-off-by: Katherine Hsieh <Katherine.Hsieh@quantatw.com>
Reviewed-on: https://review.coreboot.org/19479
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Update the DPTF parameters based on thermal test result.
1. Update DPTF CPU/TSR0/TSR1/TSR2 passive/critial trigger points.
CPU passive point:83, critial point:99
TSR0 passive point:60, critial point:70
TSR1 passive point:50, critial point:90
TSR2 passive point:77, critial point:90
2. Update PL1/PL2 Min Power Limit/Max Power Limit
Set PL1 min to 4W, max to 12W, and step size to 0.2W
3. Change thermal relationship table (TRT) setting.
Change CPU Throttle Effect on CPU sample rate to 5secs
Change CPU Effect on Temp Sensor 0 sample rate to 60secs
The TRT of TCHG is TSR1, but real sensor is TSR2. sample rate to 30secs
Change Charger Effect on Temp Sensor 2 sample rate to 30secs
Change CPU Effect on Temp Sensor 2 sample rate to 120secs
BUG=None
TEST=build and boot on electro dut
Change-Id: I0ea0bab7fa6b0ad75d9ddacbd7cd882f91e4b0db
Signed-off-by: Katherine Hsieh <Katherine.Hsieh@quantatw.com>
Reviewed-on: https://review.coreboot.org/19538
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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This configures GPIO_177 as native function.
This enables OS to boot from sdcard.
BUG=b:35648535
TEST=Check OS boot from sdcard.
Change-Id: I73901d4a1b39752cbc452f3286d494587dac95d4
Signed-off-by: Venkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri@intel.com>
Reviewed-on: https://review.coreboot.org/18948
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Vaibhav Shankar <vaibhav.shankar@intel.com>
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Weida touchscreen controller needs 130 ms delay after reset
BUG=b:35586513
BRANCH=reef
TEST=Verified that touchscreen works on power-on and suspend/resume
on snappy.
Change-Id: I8418e742a69a2d6395baa2799a4da42a9bb5b312
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/19245
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Even though the i2c spec has no minimum data hold time in fast
mode the trackpad vendor indicates 300ns is their minimum. However,
the topology of the board uses FET isolation to cross voltage
domains. Therefore, the default 300ns which should work isn't reflected
on the device side of the voltage isolation circuit. Therefore,
increase the data hold time to show an observed data hold time of
more than 300ns on the device side.
BUG=b:36469182
Change-Id: I1b70f2f53c5a29cc7cfd5035a71ca5811b3bcba0
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/19065
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Wake On Voice stream capture configuration is mono. It is sufficient
to keep DMIC_CLK_A1 on in S0ix; so, turning off DMIC_CLK_B1.
Power saving should be visible in the boards which has more
than one DMIC connected.
BUG=None
BRANCH=None
TEST=WoV and quad channel DMIC capture works
Change-Id: Ic46d4c7b30b945eba47a05d78386f48e4a675a03
Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com>
Reviewed-on: https://review.coreboot.org/19018
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Venkateswarlu V Vinjamuri <venkateswarlu.v.vinjamuri@intel.com>
Tested-by: build bot (Jenkins)
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1. Remove CPU throttling effect of the charger sensor
Refers Change-Id I267b6e07fa9def2c91ff9f6035f2d9437faf1965
(mb/google/reef: Remove CPU throttling effect of the charger sensor)
to remove CPU throttling effect of the charger sensor
since it's not relevant to throttle CPU based on the charger sensor.
2. Change TSR1 influence from 200 to 100
3. Change TSR2 sample period from 120s to 30s
BUG=b:35585781
BRANCH=reef
TEST=built, and verified on snappy by thermal team.
Change-Id: Ic3fc51c4288b24f4e64950e5b148aed4495a1c3b
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/18950
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
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Create the initial Nasher variant which refers to the Reef.
Nasher is APL board that derives from reference board Reef.
BRANCH=master
BUG=b:36389286
TEST=Build (as initial setup)
Signed-off-by: YH Lin <yueherngl@chromium.org>
Change-Id: I7962aa8246890149988c7f02dcd90d820df7b901
Reviewed-on: https://review.coreboot.org/18928
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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1. correct DPTF TCHG target device to TSR2
2. Refers Change-Id I267b6e07fa9def2c91ff9f6035f2d9437faf1965
(mb/google/reef: Remove CPU throttling effect of the charger sensor)
to remove CPU throttling effect of the charger sensor
since it's not relevant to throttle CPU based on the charger sensor.
BUG=b:35586881
BRANCH=reef
TEST=emerge-pyro coreboot
Change-Id: I4801e0e612e0ddf90764ffe080c679818d33212a
Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/18920
Tested-by: build bot (Jenkins)
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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We just support Raydium touchscreen instead of Elan.
Thus we have to remove Elan touchscreen device
and add Raydium touchsrcreen device.
BUG=b:35775065
BRANCH=reef
TEST=emerge-sand coreboot
Change-Id: I7b33a29287dcb90e379b52cc93825f2988a0d3c9
Signed-off-by: Katherine Hsieh <Katherine.Hsieh@quantatw.com>
Reviewed-on: https://review.coreboot.org/18789
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Change hid name to "WDHT0002" for Weida WDT8752 which is supported by
standard hid i2c Linux driver.
BUG=b:35586513
BRANCH=reef
TEST=build, boot on snappy, and verified acpi node "WDHT0002" created.
Change-Id: Ie0cc980aa427b6db1eb14eb7868718619bb1310f
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/18874
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
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It's not relevant to throttle CPU based on the charger sensor.
So, remove this CPU throttling effect.
BUG=b:35908799
BRANCH=master
TEST=Built and booted on Electro DUT
Change-Id: I267b6e07fa9def2c91ff9f6035f2d9437faf1965
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/18852
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
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Update the DPTF parameters based on thermal test result.
(ZHT_DPTF_DVT_v0.6_20170314.xlsx)
1. Increase PL2 Max to 15W.
BUG=b:35583586
BRANCH=reef
TEST=build and verify PL2 Max value on electro dut
Change-Id: I13167e28267d5827d79a6bde31f077a01f2bd535
Signed-off-by: Tim Chen <Tim-Chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/18807
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Sand is not convertible and no EC sensor sends event from EC to AP.
That event default is tablet mode, we don't have to enable tablet event.
Modify the ec.h, is based on <baseboard/ec.h>
BUG=b:36108742
BRANCH=reef
TEST=emerge-sand coreboot, boot to OS and touchpad and keyboard can work.
Change-Id: I6b6b45b5b4daf2c430ed18130f39eab0bd9a9812
Signed-off-by: Katherine Hsieh <Katherine.Hsieh@quantatw.com>
Reviewed-on: https://review.coreboot.org/18737
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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It is a copy from baseboard/devicetree.cb (coreboot.org ToT)
BUG=b:35775065
BRANCH=reef
TEST=emerge-sand coreboot
Change-Id: I5ba86e54ccfbf5af7bf0e9ad8fe7bf22020e48ee
Signed-off-by: Katherine Hsieh <Katherine.Hsieh@quantatw.com>
Reviewed-on: https://review.coreboot.org/18703
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Update the DPTF parameters based on thermal test result.
(ZHT_DPTF_EVT2_v0.5_20170306.xlsx)
1. Update DPTF TCPU critical trigger point.
TCPU critical point: 105
2. Update DPTF TSR2 passive trigger point.
TSR2 passive point: 58
3. Change thermal relationship table (TRT) setting.
Change CPU Throttle Effect on CPU sample rate to 10secs.
Change Charger Effect on Temp Sensor 2 sample rate to 30secs.
Change CPU Effect on Temp Sensor 2 sample rate to 60secs.
BUG=b:35583586
BRANCH=master
TEST=build and boot on electro dut
Change-Id: I85564ccdaf327eeaa13bf1f31d9a933609a21582
Signed-off-by: Tim Chen <Tim-Chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/18610
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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This configures GPIO_177 as an input pin for SDCARD card
detect. This also changes the ownership of the pin from ACPI
to GPIO driver.
Assign the sdcard card detect pin in devicetree for reef variants.
CQ-DEPEND=448173
BUG=chrome-os-partner:63070
TEST=None
Change-Id: Ia8aef60bd7d0ea36afb39f76fab051aa46a2ed64
Signed-off-by: Venkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri@intel.com>
Reviewed-on: https://review.coreboot.org/18497
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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1. Update DPTF TSR1 passive trigger points.
TSR1 passive point: 50
2. Update DPTF PL1 Minimum
PL1 min: 2.5W
BUG=b:35586881
BRANCH=reef
TEST=emerge-pyro coreboot
Change-Id: Ia2634f40098d026c4d228fab4b7c05501c1ff05f
Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/18699
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Fine tune USB2, need to override the following registers.
port#1:
PERPORTPETXISET=7
PERPORTTXISET=0
BUG=b:35858164
BRANCH=reef
TEST=built, measured eye diagram on snappy, and reviewed by intel
Change-Id: I461cf8f032b4e70abc9707e6cd3603a62cee448f
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/18590
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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The cr50 part on reef is connected to the SoC's UART lines. However,
when the tx signal is low it causes an interrupt to fire on cr50.
Therefore, keep the tx signal high in suspend state so that it doesn't
cause an interrupt storm on cr50 which prevents cr50 from sleeping.
BUG=chrome-os-partner:63283
BRANCH=reef
TEST=s0ix no longer causes interrupt storm on cr50. Power consumption
normal.
Change-Id: Idaeb8e4427c1cec651122de76a43daa15dc54d0f
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/18491
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
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This is done to avoid any conflicts with same IRQ enums defined by other
drivers.
BUG=None
BRANCH=None
TEST=Compiles successfully
Change-Id: I539831d853286ca45f6c36c3812a6fa9602df24c
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/18444
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Wacom I2C driver does the same thing as I2C HID driver, other than
defining macros for Wacom HID. Instead of maintaining two separate
drivers providing the same functionality, update all wacom devices to
use generic I2C HID driver.
BUG=None
BRANCH=None
TEST=Verified that ACPI nodes for wacom devices are unchanged.
Change-Id: Ibb3226d1f3934f5c3c5d98b939756775d11b792c
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/18401
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
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Create the initial Sand variant which refers to the Reef.
Sand is APL board that derives from reference board Reef.
BRANCH=master
BUG=chrome-os-partner:62200
TEST=Build (as initial setup)
Signed-off-by: YH Lin <yueherngl@chromium.org>
Change-Id: Iba8c5653b6176676c759d2b48063f0c0c6cde625
Reviewed-on: https://review.coreboot.org/18324
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Update DPTF parameters based on thermal team test result.
1. Update TSR2 trigger points.
TSR2 passive point: 70, critical point: 90
2. Set PL2 Max to 15W.
BUG=chrome-os-partner:61383
BRANCH=reef
TEST=build, boot on snappy, and verified by thermal team
Change-Id: I8d01d6c1d7eabd359ceb131f3cd10965d4ac2c42
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/18318
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Performance degradation seen with current PL1 throttling rate as 8
seconds for TSR1 sensor with Aquarium workload. After fine tuning PL1
throttling rate to 15 seconds, fps score improved.
BUG=chrome-os-partner:60038
BRANCH=reef
TEST=Built and tested on electro system
Change-Id: I5cdebb08e00f0f28b88f1c6b2b1cafaeb8cdb453
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/18317
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Venkateswarlu V Vinjamuri <venkateswarlu.v.vinjamuri@intel.com>
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Reef is a convertible add support for sending Tablet mode switch
changes from EC to AP.
Change-Id: I6dfddbfdb5a2ffbdfd77c5f49602bf68e9693a06
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://review.coreboot.org/18277
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
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|
Reason for revert:
Pyro has two touchscreen sources: WACOM/ELAN.
It will not have both touchscreen IC in one system at the same time.
So the "probed" property of WACOM i2c device is mandatory to set for kernel
to know whether it exists before driver initializes it.
Otherwise in ELAN case, when driver fails to init WACOM i2c device, ACPI _OFF
will be invoked to set GPIO#152 low to cut off power.
BUG=chrome-os-partner:62371
BRANCH=reef
TEST=emerge-pyro coreboot
Change-Id: I30f467bd8720d959686dc14f7877e6bc11ea6213
Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/18291
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
This patch sets PL2 override value to 15W in RAPL registers.
BUG=chrome-os-partner:62110
BRANCH=reef
TEST=Apply new firmware to evaluate Octane benchmark score.
Change-Id: I51734051586753677129314b5273fb275c74f5d2
Signed-off-by: Harry Pan <harry.pan@intel.com>
Reviewed-on: https://review.coreboot.org/18283
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
|
|
Apollolake boards should use DMIC-4ch configuration in Kernel side and
use CaptureChannelMap in userspace to distinguish boards with different
number of DMIC's. So, NHLT DMIC 1-ch & 2-ch endpoint configuration will
not be required and hence removed.
BUG=chrome-os-partner:60827
TEST=Verify internal mic capture
TEST='arecord -Dhw:0,3 dmic_4ch.wav -f S16_LE -r 48000 -c 4 -d 10' works
Change-Id: Ibe81290906c9e379ae49e437648ee9cd6f123ff8
Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com>
Reviewed-on: https://review.coreboot.org/18252
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
EC sets the logic level based on outstanding wake events. When GPIO_22
is configured as a level triggered interrupt, the events are not
cleared from the interrupt handler. Hence, we'd just be re-signalling
over and over causing an interrupt storm upon lid open. So, GPIO_22
needs to be configured as EDGE_SINGLE instead of LEVEL.
BUG=chrome-os-partner:62458
TEST=Lid close/open. check CPU usage using top. It should
not show 70% CPU usage.
Signed-off-by: Vaibhav Shankar <vaibhav.shankar@intel.com>
Change-Id: I710a690578c6e5b63be34b7fbcb21c703ef56e3a
Reviewed-on: https://review.coreboot.org/18267
Tested-by: build bot (Jenkins)
Reviewed-by: Venkateswarlu V Vinjamuri <venkateswarlu.v.vinjamuri@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
Export PowerResource for WDT touchscreen device.
BUG=chrome-os-partner:62311, chrome-os-partner:60194,
chrome-os-partner:62371
BRANCH=reef
TEST=Compiles successfully.
Change-Id: Icc5be170353753201d3571c39b50e29424d4d6d3
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/18240
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
1. For ELAN, export reset GPIO as well as PowerResource
2. For WCOM, export PowerResource
BUG=chrome-os-partner:62311, chrome-os-partner:60194,
chrome-os-partner:62371
BRANCH=reef
TEST=Verified that touchscreen works on pyro with WCOM device on
power-on as well as after suspend/resume.
Change-Id: I0306e24e19bf821cd3e08fdacc0d78b494c9a92f
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/18239
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Linux kernel expects that power management with ACPI should always be
handled using PowerResource. However, some kernel drivers (e.g. ELAN
touchscreen) check to see if reset gpio is passed in by the BIOS to
decide whether the device loses power in suspend. Thus, until the kernel
has a better way for drivers to query if device lost power in suspend,
we need to allow passing in of GPIOs via _CRS as well as exporting
PowerResource to control power to the device.
Update mainboards to export reset GPIO as well as PowerResource for
ELAN touchscreen device.
BUG=chrome-os-partner:62311,chrome-os-partner:60194
BRANCH=reef
TEST=Verified that touchscreen works on power-on as well as after
suspend-resume.
Change-Id: I3409689cf56bfddd321402ad5dda3fc8762e6bc6
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/18238
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
|
|
I2C data (GPIO_132) and Clk (GPIO_133) lines are pulled low during
standby states S3/S0ix. This causes leakage of power. To reduce the
leakage, we have to pull these lines high during S3/S0ix. This is
done by programming the IOSSTATE to HIz. Also note that we are using
the internal pull ups to keep at SOC at 1.8V and the I2C lines are
not floating.
BUG=chrome-os-partner:62428,chrome-os-partner:61651
TEST=Enter S3/S0ix. Measure trackpad power. It should be less
than 4mW. Also I2c lines should be pulled high in S3/S0ix.
Change-Id: I5570ac37ec3cc41f6463dd6b858fdb56a20a1733
Signed-off-by: Vaibhav Shankar <vaibhav.shankar@intel.com>
Reviewed-on: https://review.coreboot.org/18251
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
|
|
In order to pass type A USB2 eye diagram,
USB2 port#0/#1 PHY register will need to be overridden.
port#0:
PERPORTPETXISET = 7
PERPORTTXISET = 1
IUSBTXEMPHASISEN = 3
PERPORTTXPEHALF = 0
port#1:
PERPORTPETXISET = 7
PERPORTTXISET = 2
IUSBTXEMPHASISEN = 3
PERPORTTXPEHALF = 0
BUG=chrome-os-partner:59491
BRANCH=reef
TEST=emerge-pyro coreboot
Change-Id: I8e67a6f0192d1c0abf6ec4926c2a17e44c818948
Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/18229
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
Wacom touchscreen is i2c hid device and it's the device that always
exists.
So no need to set "probed" property for it.
BUG=chrome-os-partner:61513
BRANCH=reef
TEST=emerge-pyro coreboot
Change-Id: I27fe18ceadd03029b826e0237f80132eda1089b0
Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/18227
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
Follow i2c-hid spec definition, level trigger interrupt is required
for i2c-hid device.
BUG=chrome-os-partner:61513
BRANCH=reef
TEST=emerge-pyro coreboot
Change-Id: Ia825bd0c898e71e2ee2bf411f117a49a8fb411b6
Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/18217
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
1. Update DPTF CPU/TSR1 passive trigger points.
CPU passive point: 80
TSR1 passive point: 46
2. Update DPTF TRT Sample Period
TSR1: 8s
BUG=chrome-os-partner:62133
BRANCH=reef
TEST=emerge-pyro coreboot
Change-Id: I8fcf750ac17b8894ed3c8704eec62f5071d9cf24
Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/18174
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Update the DPTF parameters based on thermal test result.
(ZHT_DPTF_EVT2_v0.4_20170120.xlsx)
1. Update DPTF TSR1 passive trigger point.
TSR1 passive point: 46
BUG=chrome-os-partner:60038
BRANCH=master
TEST=build and boot on electro dut
Change-Id: If35e4cf2dbf7c506534c52a052598f6204d5315a
Signed-off-by: Tim Chen <Tim-Chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/18183
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
The PP1800_S rail is turned off in S3. However, enabling internal
pullups on the pins which are connected to PP1800_S results in
leakage into the P1800_S rail. Fix this by disabling the internal
pullups on PP1800_S rail pins.
BUG=chrome-os-partner:61968
BRANCH=reef
TEST=measured leakage on PP1800_S rail. Gone with this patch.
Change-Id: I5ae92b31c1a633f59d425f4105b8db1c9c18c808
Signed-off-by: Aaron Duribn <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/18189
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
Add weida touchscreen as 2nd touchscreen source
BUG=chrome-os-partner:61865
BRANCH=reef
TEST=emerge-snappy coreboot, and verified that touchscreen works on
snappy.
Change-Id: If76312a62e97da9d5de18ad895e90ee6b0f0c6ae
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/18166
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
ELAN touchscreen device expects firmware to export GPIOs and ACPI
regulators for managing power to the device. Thus, provide the
required ACPI elements for OS driver to properly manage this device.
BUG=None
BRANCH=None
TEST=Verified that touchscreen works properly on boot-up and after
suspend/resume.
Change-Id: I78e0c35f60289afe338d140d90784a433ca534ae
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/18163
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
The following devices i2c6, i2c7, spi1, spi2, uart3 are not used.
BUG=none
BRANCH=master
TEST=emerge-snappy coreboot chromeos-bootimage
Change-Id: I9bacdbdd194ce21686c1618494d113402f2bef6c
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/18140
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Audio DMIC PLL needs to be ON in S0ix to support
Wake on Voice. This requires GPIO_79 and GPIO_80
to be configured as IGNORE IOSSTATE. So DMIC CLKs
will be ON in S0ix.
Change-Id: If91045a8664ce853366b670b9db38d620818fbab
Signed-off-by: Vaibhav Shankar <vaibhav.shankar@intel.com>
Reviewed-on: https://review.coreboot.org/18155
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
This reverts commit 01ba8cf7 (mainboard/google/snappy: Add PowerResource
for ELAN touchscreen)
Change was out of date and broke the build.
Change-Id: Id47631ece1172c3f93bf6f40b8686dfd728842a9
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/18158
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
|
|
SPI controller need to access flash descriptors/SFDP during s0ix exit,
so all fast SPI IO can't be put into IOSTANDBY state. For reef, that
will be FST_SPI_CLK_FB, GPIO_97, GPIO_99, GPIO_100, GPIO_103 and
GPIO_106.
BUG=chrome-os-partner:61370
BRANCH=reef
TEST=Enter s0ix state in OS, after resume run flashrom to read SPI
content.
Change-Id: I5c59601ec00e93c03dd72a99a739add0950c6a51
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/18137
Tested-by: build bot (Jenkins)
Reviewed-by: Vaibhav Shankar <vaibhav.shankar@intel.com>
Reviewed-by: Venkateswarlu V Vinjamuri <venkateswarlu.v.vinjamuri@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Define reset_gpio and enable_gpio for touchscreen device so that
when kernel puts this device into D3, we put the device into reset.
PowerResource _ON and _OFF routines are used to put the device
into D0 and D3 states.
BUG=chrome-os-partner:59034
BRANCH=master
TEST=emerge-snappy coreboot chromeos-bootimage
Change-Id: I08c05d06b2812a33b3fdff9b42b2a8e0653dd8b4
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/17366
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
Current fw does not create ACPI device for
OS to recognize ELAN touchscreen.
List the touch screen in the devicetree so that
the correct ACPI device are created.
BUG=chrome-os-partner:61803
BRANCH=reef
TEST=emerge-pyro coreboot
Change-Id: I9015fa63ef3aba74b682da3608a05ee49c4947c5
Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/18086
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
1. Update DPTF TSR1/TSR2 passive/critial trigger points.
TSR1 passive point:53, critial point:80
TSR2 passive point:90, critial point:100
2. Update PL1 Min to 4W and PL1 Max to 12W
3. Update thermal relationship table (TRT) setting.
BUG=none
BRANCH=master
TEST=build, boot on snappy dut and verified by thermal team member.
Change-Id: I8b4fb178daa7c2e4091a14779a125bd5e943d023
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/17955
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Update the DPTF parameters based on thermal test result.
(ZHT_DPTF_EVT1_v0.3_20161227.xlsx)
1. Update DPTF CPU/TSR1/TSR2 passive/critial trigger points.
CPU critical point:103
TSR1 passive point:45
TSR2 passive point:55, critical point:90
2. Change thermal relationship table (TRT) setting.
Change CPU Throttle Effect on CPU sample rate to 3secs
Change Charger Effect on Temp Sensor 2 sample rate to 60secs
Change CPU Effect on Temp Sensor 1 sample rate to 8secs
BUG=chrome-os-partner:60038
BRANCH=master
TEST=build and boot on electro dut
Change-Id: I3746750f7ea4a2e01153a36c28a5c33140c9e38c
Signed-off-by: Tim Chen <Tim-Chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/17975
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
ELAN touchscreen device expects firmware to export GPIOs and ACPI
regulators for managing power to the device. Thus, provide the
required ACPI elements for OS driver to properly manage this device.
BUG=chrome-os-partner:60194
BRANCH=None
TEST=Verified that touchscreen works properly on boot-up and after
suspend/resume.
Change-Id: I298ca5de9c0ae302309d87e3dffb65f9be1e882e
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17799
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
|
|
Add power management type config option that allows mainboards to
either:
1. Define a power resource that uses the reset and enable gpios to
power on and off the device using _ON and _OFF methods, or
2. Export reset and enable GPIOs in _CRS and _DSD so that the OS can
directly toggle the GPIOs as required.
GPIO type needs to be updated in drivers_i2c_generic_config to use
acpi_gpio type so that it can be used for both the above cases.
BUG=chrome-os-partner:60194
BRANCH=None
TEST=Verified that elan touchscreen works fine on reef using exported
GPIOs.
Change-Id: I4d76f193f615cfc4520869dedc55505c109042f6
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17797
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
|
|
On upcoming boards an optional pull up is applied on GPIO_10
to indicate if the board should have security features locked
down for a shipping system. Provide a weak pull down so that
all boards will indicate a logic 0 until the stronger pull up
resistor is stuffed.
BUG=chrome-os-partner:59951
BRANCH=reef
Change-Id: I6f514a69bccd05ca02480f3c30d0ad503a955b1e
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/17803
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
|
|
This patch sets PL2 override value to 15W in RAPL registers
and sets DPTF PL2 Max to 15W
BUG=none
BRANCH=reef
TEST=emerge-pyro coreboot
Change-Id: Ibadf0fa442f556d018c249b1cf88e29c4d57c97f
Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/17779
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
This patch sets PL2 override value to 15W in RAPL registers.
BUG=chrome-os-partner:60535
TEST=Built, booted on reef and verified PL2 value.
Change-Id: I4ff6a5e7b8686d97134846ee80cdac10916d58ef
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/17730
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Provide the rise and fall times for the i2c buses and let the
library perform the necessary calculations for the i2c
controller registers instead of manually tuning the values.
BUG=chrome-os-partner:58112
BRANCH=master
TEST=emerge-pyro coreboot
Change-Id: I68be9b96dc731eb0084ee5e15921866818637e73
Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/17652
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Independent of Board DMIC configuration, add all DMIC points
i.e. add DMIC-1ch, DMIC-2ch, DMIC-4ch endpoints.
This allows flexibility to userspace to open capture devices as needed.
This is a temporary fix; once upper layers support choosing
particular channels from 4-ch PCM stream, we will limit exposing only
DMIC-4ch endpoint.
BUG=chrome-os-partner:60444
BRANCH=none
TEST=Verify All DMIC blobs are included
Change-Id: I9729a3570c0668f3da4e7986291ebad6fe1de47a
Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com>
Reviewed-on: https://review.coreboot.org/17660
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
In order to mirror the full flexibility of the NHLT library that
allows a caller to set the OEM revision field in the ACPI header
modify the variant callback to override the value.
Change-Id: I16e539b350a50e3c163be1439c8637b82e53a759
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/17651
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
|
|
tune i2c devices clk for snappy:
I2C0: audio
I2C2: TPM H1
I2C3: elan touchscreen
I2C4: elan touchpad
I2C5: wacom digitizer
BUG=chrome-os-partner:59034
BRANCH=master
TEST=emerge-snappy coreboot chromeos-bootimage, and measured on EVT.
audio:
Freq. 393.7kHz
Rise Time 58.8ns
Fall time 12.11ns
TPM H1:
Freq. 398.8kHz
Rise Time 31.71ns
Fall time 13.28ns
elan touchscreen:
Freq. 390.5kHz
Rise Time 235.7ns
Fall time 37.64ns
elan touchpad:
Freq. 393.7kHz
Rise Time 288.8ns
Fall time 51.67ns
wacom digitizer:
Freq. 388.8kHz
Rise Time 124.1ns
Fall time 21.10ns
Change-Id: Ib2be9e1575d4962476423eafa80f9bb10ba40e17
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/17634
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
|
|
The following devices i2c5, i2c6, i2c7, spi1, spi2, uart3
are not used.
BUG=none
BRANCH=master
TEST=emerge-pyro coreboot
Change-Id: I3b7b96e72b82af1885926800ee99beff07755bbc
Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/17589
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
BUG=chrome-os-partner:59034
BRANCH=none
TEST=emerge-snappy coreboot chromeos-bootimage
Change-Id: Ib99ae5357274ad0824d0989888dfddcb32ace7e2
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/17618
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
This pach sets the DPTF passive temperature trip point for CPU back to
95 degree celsius from 61 degree celsius as per previous thermal
optimizations (https://review.coreboot.org/#/c/16766/).
BUG=chrome-os-partner:60038
BRANCH=master
TEST=built, booted on Reef and verified the passive trip point
funtionality.
Change-Id: I83ce69b19a94e4ea8ebedfc06f259579ed6dd5d3
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/17598
Tested-by: build bot (Jenkins)
Reviewed-by: Venkateswarlu V Vinjamuri <venkateswarlu.v.vinjamuri@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Set PL1 maximum power limit value back to 12W
(https://review.coreboot.org/#/c/16596/)
from 6W due to Intel's and thermal team's suggestion.
BUG=chrome-os-partner:60038
BRANCH=master
TEST=build, boot on electro dut and verify by thermal team member
Change-Id: I57ae29180962724fde72d522caa542f0f21d5922
Signed-off-by: Tim Chen <Tim-Chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/17574
Tested-by: build bot (Jenkins)
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Venkateswarlu V Vinjamuri <venkateswarlu.v.vinjamuri@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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1. Update DPTF CPU/TSR1/TSR2 passive/critial trigger points.
CPU passive point:57, critical point:90
TSR1 passive point:55, critial point:70
TSR2 passive point:65, critial point:80
2. Update DPTF TRT Sample Period.
CPU: 5s
TSR0: 50s
TSR1: 55s
TSR2: 120s
BUG=none
BRANCH=master
TEST=emerge-pyro coreboot
Change-Id: Ib1b4b31a49d9396b1c5c9dd8d0b9b9998d01744f
Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/17552
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Update the DPTF parameters based on thermal test result.
1. Update DPTF CPU/TSR0/TSR1/TSR2 passive/critial trigger points.
CPU passive point:61
TSR0 passive point:120, critial point:125
TSR1 passive point:46, critial point:75
TSR2 passive point:100, critial point:125
2. Update PL1/PL2 Min Power Limit/Max Power Limit
Set PL1 min to 3W, and max to 6W
Set PL2 min to 8W
3. Change thermal relationship table (TRT) setting.
Change CPU Throttle Effect on CPU sample rate to 80secs
Change CPU Effect on Temp Sensor 0 sample rate to 120secs
The TRT of TCHG is TSR1, but real sensor is TSR2.
Change Charger Effect on Temp Sensor 2 sample rate to 120secs
Change CPU Effect on Temp Sensor 2 sample rate to 120secs
BUG=chrome-os-partner:60038
BRANCH=master
TEST=build and boot on electro dut
Change-Id: I7a701812cb45f51828a3cbb3343e03817645110e
Signed-off-by: Tim Chen <Tim-Chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/17466
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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1. Update DPTF CPU/TSR1/TSR2 passive/critial trigger points.
CPU passive point:100, critical point:105
TSR1 passive point:48, critial point:65
TSR2 passive point:85, critial point:100
2. Update PL1/PL2 Min Power Limit/Max Power Limit
Set PL1 min to 3W, and max to 6W
Set PL2 min and max to 8W
3. Change thermal relationship table (TRT) setting.
The TRT of TCHG is TSR1, but real sensor is TSR2.
BRANCH=master
BUG=none
TEST= Compiled, verified by thermal team.
Change-Id: Ib197c36eca88e3d05f632025cf3c238e1a2eae23
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/17426
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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The following devices i2c6, i2c7, spi1, spi2, uart3
are not used.
BUG=chrome-os-partner:59880
TEST=Boot to OS and lspci command should
not list the above disabled devices.
Change-Id: I819cdb34709703e6431b49446417ed9d6b3543cd
Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy@intel.com>
Reviewed-on: https://review.coreboot.org/17441
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Provide the rise and fall times for the i2c buses and let the
library perform the necessary calculations for the i2c
controller registers instead of manually tuning the values.
BUG=chrome-os-partner:58889,chrome-os-partner:59565
Change-Id: I0c84658471d90309cdbb850e3128ae01780633af
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/17397
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
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Reef board uses GPIO_17 as DMIC config pin.
This pin distinguishes board with Quad DMIC's or Mono DMIC.
This patch adds necessary DMIC endpoints to support either of
those configurations.
CQ-DEPEND=CL:*304339,CL:409774
BUG=chrome-os-partner:56918
BRANCH=none
TEST=Verify Mono and Quad Channel DMIC record
Change-Id: I5b2825b5f39f8962985a129f8ec65265fb18f0b2
Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com>
Reviewed-on: https://review.coreboot.org/17158
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
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Configure GPIO 122 as PERST. This is to assert WiFi PERST
during s0ix entry.
BUG=chrome-os-partner:59034
BRANCH=master
TEST=emerge-snappy coreboot chromeos-bootimage
Change-Id: If2528632fe65c3ed1af19b2ce6f99e8be0cd1ad9
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/17356
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Maxim98357a speaker amp requires BCLK & SFRM to be active
and stable before it is unmuted. If there is a BLCK and no
SFRM, it results in a pop sound.
sdmode_delay property already exists which facilitates this
configuration. This patch updates "sdmode_delay" to avoid
pop sound.
BUG=chrome-os-partner:59034
BRANCH=master
TEST=emerge-snappy coreboot chromeos-bootimage
Change-Id: Ic9095ae6812ba822c760229e69f5b27c6c244cdf
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/17361
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Snappy is using APL SoC SKU's with 6W TDP max. As Reef,
the energy calculation is wrong with the current VR solution.
Experiments show that SoC TDP max (6W) can be reached
when RAPL PL1 is set to 12W.
Therefore, we've inserted 12W override after reading the fused value (6W)
so that the system can reach the right performance level.
BUG=chrome-os-partner:59034
BRANCH=master
TEST=emerge-snappy coreboot chromeos-bootimage
Change-Id: Idd702077cd05e2b43823542cb804b2d4b42f7116
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/17362
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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BUG=chrome-os-partner:56246
BRANCH=None
TEST=Verified kernel is able to talk to the device. Even without the
digitizer, no issues observed with the kernel.
Change-Id: I894a5f4cd8f6a51e641a2c8f7b1f682ab76712ae
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17343
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
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This brings the I2C frequency down to 400kHz which is spec for fast
I2C.
BUG=chrome-os-partner:56246
BRANCH=None
TEST=Verified frequency in kernel.
Change-Id: Ib83c57eec8644903cb9c4b2ab50c94038eb690c1
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17342
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Wacom I2C driver can be used by devices other than
touchscreen. e.g. digitizer. So there is no need to name the driver
with touchscreen specific attributes. Only a separate descriptor name
is required that needs to be set by mainboard correctly.
BUG=chrome-os-partner:56246
BRANCH=None
TEST=Compiles successfully.
Change-Id: I0d32a4adae477373b3f4c5f3abbe188860701194
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17341
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Pyro is using APL SoC SKU's with 6W TDP max. As Reef,
the energy calculation is wrong with the current VR solution.
Experiments show that SoC TDP max (6W) can be reached
when RAPL PL1 is set to 12W.
Therefore, we've inserted 12W override after reading the fused value (6W)
so that the system can reach the right performance level.
BUG=chrome-os-partner:58112
BRANCH=master
TEST=emerge-pyro coreboot chromeos-bootimage
Change-Id: I6de22d7b2d107f3d26ecfadd4e0904e68318e656
Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/17335
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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tune i2c devices clk for pyro:
I2C0: audio da7219
I2C2: TPM H1
I2C3: wacom touchscreen
I2C4: elan touchpad
BUG=chrome-os-partner:58881
BRANCH=master
TEST=emerge-pyro coreboot chromeos-bootimage
Change-Id: If3c92ed260277c27a94d2fcf7883e9441519e40e
Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/17331
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Maxim98357a speaker amp requires BCLK & SFRM to be active
and stable before it is unmuted. If there is a BLCK and no
SFRM, it results in a pop sound.
sdmode_delay property already exists which facilitates this
configuration. This patch updates "sdmode_delay" to avoid
pop sound.
BUG=chrome-os-partner:58112
BRANCH=master
TEST=emerge-pyro coreboot chromeos-bootimage
Change-Id: I5aee41957c9de7a05f962d3ede74efc6998a78fc
Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/17336
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Configure GPIO 122 as PERST. This is to assert WiFi PERST
during s0ix entry.
BUG=chrome-os-partner:58112
BRANCH=master
TEST=emerge-pyro coreboot chromeos-bootimage
Change-Id: Id760251a1b037feb62ec43199a145e407b074769
Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/17334
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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WACOM request to add a new identifier `WCOMNTN2`,
and use that for the board Pyro with all LCD combinations.
BRANCH=master
BUG=chrome-os-partner:58093
TEST=emerge-pyro vboot_reference coreboot chromeos-bootimage
Signed-off-by: Janice Li <janice.li@quantatw.com>
Change-Id: I95cf357efba958d7e864d2736d324e0aad70e307
Reviewed-on: https://review.coreboot.org/17257
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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CLK_B1(GPIO_80) and DATA_2(GPIO_83) pins needs to be
configured as native mode to use them for DMIC record
on other potential DMIC's.
DMIC blobs configure the clocks. For stereo & quad channel
record, both CLK_A1 and CLK_B1 are enabled.
For mono channel record, only CLK_A1 is enabled.
BUG=chrome-os-partner:56918
BRANCH=None
TEST=During DMIC record, check CLK_B1 and DATA_2 lines
Change-Id: I838009b85190de5360d593238e48c9593c1dc43a
Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com>
Reviewed-on: https://review.coreboot.org/17199
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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This brings the frequency down to 400kHz which is spec for
fast i2c.
BUG=chrome-os-partner:58889
Change-Id: Ibc5f152e55ed618f18ac6425264f086b1f2d1ffa
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/17215
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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This brings the frequency down to 400kHz which is spec for
fast i2c.
BUG=chrome-os-partner:58889
Change-Id: I8689a062b5457aa431eaa7fb688a7170dad83fcf
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/17214
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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In certain cases a board variant may need to override the NHLT
OEM strings in the main NHLT table. Therefore, provide that path.
BUG=chrome-os-partner:56918
Change-Id: I57cc4fd3665698e41ceebb1949180f86bb60b61f
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/17167
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com>
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Going forward GPIO_17 is used to determine the configuration of
the board w.r.t. the number of DMICs on the board.
BUG=chrome-os-partner:56918
Change-Id: I03edb880e0649977030c1b87219ebebac631a519
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/17163
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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In anticipation of getting fixed material remove the disabling of
periodic training for MT53B512M32D2NP and MT53B256M32D1NP.
BUG=chrome-os-partner:59003
Change-Id: Iaadaa979d85cab78dda527db7480420af02fd832
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/17130
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Explain the reasoning for the part_num strings used in the
memory SKU table explaining the necessity of keeping mosys
in sync with the strings used. It's possible that actual part
numbers could change as the higher speed material gets cheaper,
for example.
BUG=chrome-os-partner:58966
Change-Id: If895e52791dc56e283261b3438106116b8b2ea05
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/17129
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
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BUG=chrome-os-partner:57846
Change-Id: Ibd3ef8cebcf99ee2186dfed98b04373dd17e798e
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17093
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins)
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