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path: root/src/mainboard/google/reef/variants/pyro
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2021-01-04mb/google/reef (and variants): add ACPI backlight supportMatt DeVillier
Enables backlight control under Windows 10. Test: build/boot Windows 10 20H2 on google/reef, verify display backlight controls functional. Change-Id: I4ce613badbdcfb9c843f52408df26c6cbb4b82a2 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49057 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-10-13mb, soc/intel: Switch to using drivers/wifi/generic for Intel WiFi devicesFurquan Shaikh
This change switches all mainboard devices to use drivers/wifi/generic instead of drivers/intel/wifi chip driver for Intel WiFi devices. There is no need for two separate chip drivers in coreboot to handle Intel and non-Intel WiFi devices since the differences can be handled at runtime using the PCI vendor ID. This also allows mainboard to easily multi-source WiFi chips and still use the same firmware image without having to distinguish between the chip drivers. BUG=b:169802515 BRANCH=zork Change-Id: Ieac603a970cb2c9bf835021d1fb0fd07fd535280 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46035 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-09-22mb/google: Drop unneeded empty linesElyes HAOUAS
Change-Id: I4151d1a6ce94763432f307fbc8bc4afe229856ea Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44616 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-09-19apollolake boards: Enable CSE in devicetreeSubrata Banik
Enable CSE PCI device Bus 0: Device 0x0f: Function 0x00 to let Intel common cse block code can use this device. Calling me_read_config32(offset) function from ramstage: Without this CL : HECI: Global Reset(Type:1) Command BUG: me_read_config32 requests hidden 00:0f.0 PCI: dev is NULL! With this CL : HECI: Global Reset(Type:1) Command HECI: Global Reset success! Signed-off-by: Subrata Banik <subrata.banik@intel.com> Change-Id: I97d221ae52b4b03ecd859d708847ad77fe4bf465 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45469 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-05-26apollolake: update processor power limits configurationSumeet R Pawnikar
Update processor power limit configuration parameters based on common code base support for Intel Apollo Lake SoC based platforms. BRANCH=None BUG=None TEST=Built and tested on octopus system Change-Id: I609744d165a53c8f91e42a67da1b972de00076a5 Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41233 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-11treewide: Remove "this file is part of" linesPatrick Georgi
Stefan thinks they don't add value. Command used: sed -i -e '/file is part of /d' $(git grep "file is part of " |egrep ":( */\*.*\*/\$|#|;#|-- | *\* )" | cut -d: -f1 |grep -v crossgcc |grep -v gcov | grep -v /elf.h |grep -v nvramtool) The exceptions are for: - crossgcc (patch file) - gcov (imported from gcc) - elf.h (imported from GNU's libc) - nvramtool (more complicated header) The removed lines are: - fmt.Fprintln(f, "/* This file is part of the coreboot project. */") -# This file is part of a set of unofficial pre-commit hooks available -/* This file is part of coreboot */ -# This file is part of msrtool. -/* This file is part of msrtool. */ - * This file is part of ncurses, designed to be appended after curses.h.in -/* This file is part of pgtblgen. */ - * This file is part of the coreboot project. - /* This file is part of the coreboot project. */ -# This file is part of the coreboot project. -# This file is part of the coreboot project. -## This file is part of the coreboot project. --- This file is part of the coreboot project. -/* This file is part of the coreboot project */ -/* This file is part of the coreboot project. */ -;## This file is part of the coreboot project. -# This file is part of the coreboot project. It originated in the - * This file is part of the coreinfo project. -## This file is part of the coreinfo project. - * This file is part of the depthcharge project. -/* This file is part of the depthcharge project. */ -/* This file is part of the ectool project. */ - * This file is part of the GNU C Library. - * This file is part of the libpayload project. -## This file is part of the libpayload project. -/* This file is part of the Linux kernel. */ -## This file is part of the superiotool project. -/* This file is part of the superiotool project */ -/* This file is part of uio_usbdebug */ Change-Id: I82d872b3b337388c93d5f5bf704e9ee9e53ab3a9 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41194 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-04-06mb/google/reef: Use SPDX for GPL-2.0-only filesAngel Pons
Done with sed and God Lines. Only done for C-like code for now. Change-Id: I57e6790e49032902703ba84b68f285749aab2573 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40192 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-03-20drivers/generic/max98357a: Allow custom _HID from configAamir Bohra
Add HID field in max98357a_config and allow mainboards to set it. Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Change-Id: I22d2d078a9a4eb6ab330da8439737ff5133086d4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39286 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-03-18mainboard/google: Remove copyright noticesPatrick Georgi
They're listed in AUTHORS and often incorrect anyway, for example: - What's a "Copyright $year-present"? - Which incarnation of Google (Inc, LLC, ...) is the current copyright holder? - People sometimes have their editor auto-add themselves to files even though they only deleted stuff - Or they let the editor automatically update the copyright year, because why not? - Who is the copyright holder "The coreboot project Authors"? - Or "Generated Code"? Sidestep all these issues by simply not putting these notices in individual files, let's list all copyright holders in AUTHORS instead and use the git history to deal with the rest. Change-Id: I09cc279b1f75952bb397de2c3f2b299255163685 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39607 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2018-06-06soc/intel/common/block: Add common chip config blockSubrata Banik
Adding common chip config structure which will be used to return data to common code. When common code requires soc data, code used to fetch entire soc config structure. With this change, common code will only get the data/structure which is required by common code and not entire config. For now, adding i2c, gspi and lockdown configuration which will be used by common code. BUG=none BRANCH=b:78109109 TEST=compile code for APL/SKL/CNL. Boot using SKL/APL/CNL and check values are returned properly using common structure. Change-Id: I7f1671e064782397d3ace066a08bf1333192b21a Signed-off-by: Subrata Banik <subrata.banik@intel.com> Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/26189 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Hannah Williams <hannah.williams@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-05-24mb/google/reef: Remove unused DPTF_CPU_ACTIVE_ACx definesSumeet Pawnikar
ApolloLake based reef platform is fan-less design. We do not need these DPTF_CPU_ACTIVE_ACx defines. Removing these from all reef variants as those are not being used. Change-Id: Id3cb7f7826a5e02cf447c70ab5cdc9b5d86982ca Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/26468 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-16soc/intel/apollolake and mainboards: Use pcie_rp_clkreq_pin arrayFurquan Shaikh
This change uses an array pcie_rp_clkreq_pin for accepting CLKREQ# from mainboards instead of defining a separate property for each root port. This allows us to use memcpy to copy the entire array into FSP params as well as new properties for PCIe root ports can be added as arrays in future CLs. BUG=b:74633273 BRANCH=reef,coral Change-Id: Ifa05f1e38fcfd95063ec327712e472cdbd12dbb7 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/25186 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-21google/pyro: Update DPTF settingsKevin Chiu
1. correct DPTF TCHG target device to TSR2 2. Refers Change-Id I267b6e07fa9def2c91ff9f6035f2d9437faf1965 (mb/google/reef: Remove CPU throttling effect of the charger sensor) to remove CPU throttling effect of the charger sensor since it's not relevant to throttle CPU based on the charger sensor. BUG=b:35586881 BRANCH=reef TEST=emerge-pyro coreboot Change-Id: I4801e0e612e0ddf90764ffe080c679818d33212a Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/18920 Tested-by: build bot (Jenkins) Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-10mainboard/google/reef: Configure SDCARD card detect pinVenkateswarlu Vinjamuri
This configures GPIO_177 as an input pin for SDCARD card detect. This also changes the ownership of the pin from ACPI to GPIO driver. Assign the sdcard card detect pin in devicetree for reef variants. CQ-DEPEND=448173 BUG=chrome-os-partner:63070 TEST=None Change-Id: Ia8aef60bd7d0ea36afb39f76fab051aa46a2ed64 Signed-off-by: Venkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri@intel.com> Reviewed-on: https://review.coreboot.org/18497 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-09google/pyro: Update DPTF settingsKevin Chiu
1. Update DPTF TSR1 passive trigger points. TSR1 passive point: 50 2. Update DPTF PL1 Minimum PL1 min: 2.5W BUG=b:35586881 BRANCH=reef TEST=emerge-pyro coreboot Change-Id: Ia2634f40098d026c4d228fab4b7c05501c1ff05f Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/18699 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-02-22acpi: Add ACPI_ prefix to IRQ enum and struct namesFurquan Shaikh
This is done to avoid any conflicts with same IRQ enums defined by other drivers. BUG=None BRANCH=None TEST=Compiles successfully Change-Id: I539831d853286ca45f6c36c3812a6fa9602df24c Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/18444 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-02-20drivers/i2c: Use I2C HID driver for wacom devicesFurquan Shaikh
Wacom I2C driver does the same thing as I2C HID driver, other than defining macros for Wacom HID. Instead of maintaining two separate drivers providing the same functionality, update all wacom devices to use generic I2C HID driver. BUG=None BRANCH=None TEST=Verified that ACPI nodes for wacom devices are unchanged. Change-Id: Ibb3226d1f3934f5c3c5d98b939756775d11b792c Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/18401 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2017-02-04Revert "google/pyro: remove Wacom touchscreen probed flag"Kevin Chiu
Reason for revert: Pyro has two touchscreen sources: WACOM/ELAN. It will not have both touchscreen IC in one system at the same time. So the "probed" property of WACOM i2c device is mandatory to set for kernel to know whether it exists before driver initializes it. Otherwise in ELAN case, when driver fails to init WACOM i2c device, ACPI _OFF will be invoked to set GPIO#152 low to cut off power. BUG=chrome-os-partner:62371 BRANCH=reef TEST=emerge-pyro coreboot Change-Id: I30f467bd8720d959686dc14f7877e6bc11ea6213 Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/18291 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-01-29mainboard/google/pryo: Update touchscreen device ACPI nodesFurquan Shaikh
1. For ELAN, export reset GPIO as well as PowerResource 2. For WCOM, export PowerResource BUG=chrome-os-partner:62311, chrome-os-partner:60194, chrome-os-partner:62371 BRANCH=reef TEST=Verified that touchscreen works on pyro with WCOM device on power-on as well as after suspend/resume. Change-Id: I0306e24e19bf821cd3e08fdacc0d78b494c9a92f Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/18239 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-01-26google/pyro: Add USB2 phy setting overrideKevin Chiu
In order to pass type A USB2 eye diagram, USB2 port#0/#1 PHY register will need to be overridden. port#0: PERPORTPETXISET = 7 PERPORTTXISET = 1 IUSBTXEMPHASISEN = 3 PERPORTTXPEHALF = 0 port#1: PERPORTPETXISET = 7 PERPORTTXISET = 2 IUSBTXEMPHASISEN = 3 PERPORTTXPEHALF = 0 BUG=chrome-os-partner:59491 BRANCH=reef TEST=emerge-pyro coreboot Change-Id: I8e67a6f0192d1c0abf6ec4926c2a17e44c818948 Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/18229 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-01-26google/pyro: Disable Wacom touchscreen probedKevin Chiu
Wacom touchscreen is i2c hid device and it's the device that always exists. So no need to set "probed" property for it. BUG=chrome-os-partner:61513 BRANCH=reef TEST=emerge-pyro coreboot Change-Id: I27fe18ceadd03029b826e0237f80132eda1089b0 Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/18227 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-01-25google/pyro: Modify Wacom touchscreen IRQ type to level-triggeredKevin Chiu
Follow i2c-hid spec definition, level trigger interrupt is required for i2c-hid device. BUG=chrome-os-partner:61513 BRANCH=reef TEST=emerge-pyro coreboot Change-Id: Ia825bd0c898e71e2ee2bf411f117a49a8fb411b6 Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/18217 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-01-23google/pyro: Update DPTF settingsKevin Chiu
1. Update DPTF CPU/TSR1 passive trigger points. CPU passive point: 80 TSR1 passive point: 46 2. Update DPTF TRT Sample Period TSR1: 8s BUG=chrome-os-partner:62133 BRANCH=reef TEST=emerge-pyro coreboot Change-Id: I8fcf750ac17b8894ed3c8704eec62f5071d9cf24 Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/18174 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-01-13google/pyro: Add ELAN touch screen supportKevin Chiu
Current fw does not create ACPI device for OS to recognize ELAN touchscreen. List the touch screen in the devicetree so that the correct ACPI device are created. BUG=chrome-os-partner:61803 BRANCH=reef TEST=emerge-pyro coreboot Change-Id: I9015fa63ef3aba74b682da3608a05ee49c4947c5 Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/18086 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-12google/pyro: Set PL2 override to 15000mWKevin Chiu
This patch sets PL2 override value to 15W in RAPL registers and sets DPTF PL2 Max to 15W BUG=none BRANCH=reef TEST=emerge-pyro coreboot Change-Id: Ibadf0fa442f556d018c249b1cf88e29c4d57c97f Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/17779 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-02google/pyro: set i2c bus timings by rise/fall timesKevin Chiu
Provide the rise and fall times for the i2c buses and let the library perform the necessary calculations for the i2c controller registers instead of manually tuning the values. BUG=chrome-os-partner:58112 BRANCH=master TEST=emerge-pyro coreboot Change-Id: I68be9b96dc731eb0084ee5e15921866818637e73 Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/17652 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-29google/pyro: disable unused devicesKevin Chiu
The following devices i2c5, i2c6, i2c7, spi1, spi2, uart3 are not used. BUG=none BRANCH=master TEST=emerge-pyro coreboot Change-Id: I3b7b96e72b82af1885926800ee99beff07755bbc Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/17589 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-11-23google/pyro: Update DPTF settingsKevin Chiu
1. Update DPTF CPU/TSR1/TSR2 passive/critial trigger points. CPU passive point:57, critical point:90 TSR1 passive point:55, critial point:70 TSR2 passive point:65, critial point:80 2. Update DPTF TRT Sample Period. CPU: 5s TSR0: 50s TSR1: 55s TSR2: 120s BUG=none BRANCH=master TEST=emerge-pyro coreboot Change-Id: Ib1b4b31a49d9396b1c5c9dd8d0b9b9998d01744f Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/17552 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-10drivers/i2c/wacom: Make the driver more genericFurquan Shaikh
Wacom I2C driver can be used by devices other than touchscreen. e.g. digitizer. So there is no need to name the driver with touchscreen specific attributes. Only a separate descriptor name is required that needs to be set by mainboard correctly. BUG=chrome-os-partner:56246 BRANCH=None TEST=Compiles successfully. Change-Id: I0d32a4adae477373b3f4c5f3abbe188860701194 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17341 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-11-10mainboard/google/pyro: Set PL1 override to 12000mWKevin Chiu
Pyro is using APL SoC SKU's with 6W TDP max. As Reef, the energy calculation is wrong with the current VR solution. Experiments show that SoC TDP max (6W) can be reached when RAPL PL1 is set to 12W. Therefore, we've inserted 12W override after reading the fused value (6W) so that the system can reach the right performance level. BUG=chrome-os-partner:58112 BRANCH=master TEST=emerge-pyro coreboot chromeos-bootimage Change-Id: I6de22d7b2d107f3d26ecfadd4e0904e68318e656 Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/17335 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-11-10google/pyro: Tune i2c frequency to 400 KhzKevin Chiu
tune i2c devices clk for pyro: I2C0: audio da7219 I2C2: TPM H1 I2C3: wacom touchscreen I2C4: elan touchpad BUG=chrome-os-partner:58881 BRANCH=master TEST=emerge-pyro coreboot chromeos-bootimage Change-Id: If3c92ed260277c27a94d2fcf7883e9441519e40e Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/17331 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-11-10google/pyro: update timing of sdmode togglingKevin Chiu
Maxim98357a speaker amp requires BCLK & SFRM to be active and stable before it is unmuted. If there is a BLCK and no SFRM, it results in a pop sound. sdmode_delay property already exists which facilitates this configuration. This patch updates "sdmode_delay" to avoid pop sound. BUG=chrome-os-partner:58112 BRANCH=master TEST=emerge-pyro coreboot chromeos-bootimage Change-Id: I5aee41957c9de7a05f962d3ede74efc6998a78fc Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/17336 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-11-10mainboard/google/pyro: Configure PERST pinKevin Chiu
Configure GPIO 122 as PERST. This is to assert WiFi PERST during s0ix entry. BUG=chrome-os-partner:58112 BRANCH=master TEST=emerge-pyro coreboot chromeos-bootimage Change-Id: Id760251a1b037feb62ec43199a145e407b074769 Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/17334 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-11-09google/pyro: Update WACOM touchscreen ACPI _HIDJanice Li
WACOM request to add a new identifier `WCOMNTN2`, and use that for the board Pyro with all LCD combinations. BRANCH=master BUG=chrome-os-partner:58093 TEST=emerge-pyro vboot_reference coreboot chromeos-bootimage Signed-off-by: Janice Li <janice.li@quantatw.com> Change-Id: I95cf357efba958d7e864d2736d324e0aad70e307 Reviewed-on: https://review.coreboot.org/17257 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-10-26google/reef/variants/pyro: Use WCOM Touchscreen driverFurquan Shaikh
BUG=chrome-os-partner:57846 Change-Id: Ibd3ef8cebcf99ee2186dfed98b04373dd17e798e Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17093 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins)
2016-10-07google/reef/variants/pyro: Add support for GPIO output polarityMartin Roth
commit 028200f7 - x86/acpi_device: Add support for GPIO output polarity updated ACPI_GPIO_OUTPUT to ACPI_GPIO_OUTPUT_ACTIVE_HIGH for the other boards that needed it, but pyro wasn't in the tree when it was initially pushed. Now that pyro is in the tree, it needs to be updated as well. Change-Id: I617999b06ee584e0543d7ae3232bb2be2ff7429c Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/16930 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins)
2016-10-07mainboard/google/reef: add pyro variant.Kevin Chiu
Create the initial Pyro variant which refers to the Reef. Pyro is APL Chrome board that deviate from reference board Reef. BRANCH=master BUG=None TEST=Build Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Change-Id: I9beed1f6895e8891d3d51b563edfe172f566718b Reviewed-on: https://review.coreboot.org/16855 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
generated by cgit v1.2.3 (git 2.39.1) at 2024-07-27 07:21:31 +0000