summaryrefslogtreecommitdiff
path: root/src/mainboard/google/reef/Kconfig
AgeCommit message (Collapse)Author
2016-11-18google/chromeec: Add common infrastructure for boot-mode switchesFurquan Shaikh
Instead of defining the same functions for reading/clearing boot-mode switches from EC in every mainboard, add a common infrastructure to enable common functions for handling boot-mode switches if GOOGLE_CHROMEEC is being used. Only boards that were not moved to this new infrastructure are those that do not use GOOGLE_CHROMEEC or which rely on some mainboard specific mechanism for reading boot-mode switches. BUG=None BRANCH=None TEST=abuild compiles all boards successfully with and without ChromeOS option. Change-Id: I267aadea9e616464563df04b51a668b877f0d578 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17449 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner <jwerner@chromium.org>
2016-11-16mainboard/google/reef: Add proper DMIC endpoints based on DMIC config pinSathyanarayana Nujella
Reef board uses GPIO_17 as DMIC config pin. This pin distinguishes board with Quad DMIC's or Mono DMIC. This patch adds necessary DMIC endpoints to support either of those configurations. CQ-DEPEND=CL:*304339,CL:409774 BUG=chrome-os-partner:56918 BRANCH=none TEST=Verify Mono and Quad Channel DMIC record Change-Id: I5b2825b5f39f8962985a129f8ec65265fb18f0b2 Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com> Reviewed-on: https://review.coreboot.org/17158 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-11-10drivers/i2c/wacom: Make the driver more genericFurquan Shaikh
Wacom I2C driver can be used by devices other than touchscreen. e.g. digitizer. So there is no need to name the driver with touchscreen specific attributes. Only a separate descriptor name is required that needs to be set by mainboard correctly. BUG=chrome-os-partner:56246 BRANCH=None TEST=Compiles successfully. Change-Id: I0d32a4adae477373b3f4c5f3abbe188860701194 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17341 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-11-10mainboard/google/reef: Add support for RECOVERY_MRC_CACHEFurquan Shaikh
1. Add RECOVERY_MRC_CACHE region to reef FMAP. 2. Implement helper function for getting event for recovery mode with memory retraining. 3. Select HAS_RECOVERY_MRC_CACHE. BUG=chrome-os-partner:59352 BRANCH=None TEST=Verified recovery mode behavior with and without memory training request on reef. Change-Id: I91abc9f8122f1aa3980c6372ab557e56a7a92730 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17243 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-09mainboard/google/reef: use common google smbios mainboard versionAaron Durbin
BUG=chromium:663243 Change-Id: Ic78a6aac11a8e842911245c59e8ced7ed2c4e27a Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17291 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-10-26google/reef/variants/pyro: Use WCOM Touchscreen driverFurquan Shaikh
BUG=chrome-os-partner:57846 Change-Id: Ibd3ef8cebcf99ee2186dfed98b04373dd17e798e Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17093 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins)
2016-10-20mainboard/google/reef: add snappy variantWisley Chen
Create the initial Snappy variant which refers to the Reef device. Snappy, an Apollolake-platform, is deviated from reference board Reef. BRANCH=master BUG=None TEST=Built & booted Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Change-Id: I6f32c0b1a154edbd8c4822acdbdbdbeb4a0098e6 Reviewed-on: https://review.coreboot.org/17043 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-10-07mainboard/google/reef: add pyro variant.Kevin Chiu
Create the initial Pyro variant which refers to the Reef. Pyro is APL Chrome board that deviate from reference board Reef. BRANCH=master BUG=None TEST=Build Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Change-Id: I9beed1f6895e8891d3d51b563edfe172f566718b Reviewed-on: https://review.coreboot.org/16855 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-10-01mainboard/google/reef: unconditionally set MAINBOARD_FAMILYAaron Durbin
For all mainboard variants use the "Google_Reef" family by default which is populated in SMBIOS tables. A variant can provide their own value if needed, but "Google_Reef" can reside as the family without having to add conditions for each variant when MAINBOARD_FAMILY have to be overridden. BUG=chrome-os-partner:56677 Change-Id: Ic214eae1e6473b32f4cb442c09c34355357e1257 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16813 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins)
2016-09-30google/reef: Fix default values in KconfigMartin Roth
These default values weren't being set with the default keyword so were ending up with different values. from the default generated config file before this change: CONFIG_DRIVER_TPM_I2C_BUS=0x9 CONFIG_DRIVER_TPM_I2C_ADDR=0x2 CONFIG_DRIVER_TPM_I2C_IRQ=-1 Change-Id: I19514d0c9b2a9b7e479f003a4d3384e073f4d531 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/16828 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-09-21mainboard/google/reef: Enable cr50 TPM interruptDuncan Laurie
Enable the cr50 TPM and interrupt as GPE0_DW1_28 for use during verstage. The interrupt is left in APIC mode as the GPE is still latched when the GPIO is pulled low. BUG=chrome-os-partner:53336 Change-Id: Ib0247653bdcbaccb645cd16b81d7ec3c38f669af Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/16673 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-19Revert "mainboard/google/reef: Enable cr50 TPM interrupt"Duncan Laurie
This reverts commit 24de342438208d9b843e87627f15b9a272285b0f.
2016-09-19mainboard/google/reef: Enable cr50 TPM interruptDuncan Laurie
Enable the cr50 TPM and interrupt as GPE0_DW1_28 for use during verstage. The interrupt is left in APIC mode as the GPE is still latched when the GPIO is pulled low. BUG=chrome-os-partner:53336 Change-Id: I28ade5ee3bf08fa17d8cabf16287319480f03921 Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
2016-09-08mainboard/google/reef: move devicetree to baseboardAaron Durbin
Move the current devicetree.cb to be under variants/baseboard. New variants can provide their own devicetree as needed. BUG=chrome-os-partner:56677 Change-Id: Ib109ca4be883884b318264500d14aa8d40e3072a Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16510 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-09-06google/reef: Enable I2C TPMDuncan Laurie
Enable the I2C based TPM on the reef board at bus 2 and address 0x50. This makes vboot functional without needing MOCK_TPM and results in the following in the SSDT: Device (TPMI) { Name (_HID, "GOOG0005") // _HID: Hardware ID Name (_UID, Zero) // _UID: Unique ID Name (_DDN, "I2C TPM") // _DDN: DOS Device Name Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) } Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings { I2cSerialBus (0x0050, ControllerInitiated, 0x00061A80, AddressingMode7Bit, "\\_SB.PCI0.I2C2", 0x00, ResourceConsumer) Interrupt (ResourceConsumer, Edge, ActiveLow, Exclusive) { 0x00000039 } }) } Change-Id: Ia9775caabeac3e6a3bd72de38f9611b4cea7cea4 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/16398 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-04mainboard/google/reef: provide baseboard and variant conceptsAaron Durbin
To further the ability of multiple variant boards to share code provide a place to land the split up changes. This patch provides the tooling using a new Kconfig value, VARIANT_DIR, as well as the Make plumbing. The directory layout with a single variant, reef (which is also the baseboard), looks like this: variants/baseboard - code variants/baseboard/include/baseboard - headers variants/reef - code variants/reef/include/variant - headers New boards would then add themselves under their board name within the 'variants' directory. No split has been done with providing different logic yet. This is purely a organizational change. BUG=chrome-os-partner:56677 Change-Id: Ib73a3c8a3729546257623171ef6d8fa7a9f16514 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16418 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-09-04mainboard/google/reef: prepare sharing directory for variantsAaron Durbin
Instead of completely duplicating the a reference board's directory when doing a variant or follower device start providing a means to share code within a single directory. This change just starts the process from the Kconfig side, but subsequent patches will follow which disentangles the board specific pieces from and common logic. BUG=chrome-os-partner:56677 Change-Id: I96628920d78012e488ec008e35daac9c1be0cf79 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16417 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-08-31mainboard/*/Kconfig: Set GBB_HWID where missingPatrick Georgi
Provide GBB's hardware ID (used on Chrome OS devices) because it will be dropped from depthcharge. BRANCH=none BUG=none TEST=none Change-Id: I4851c1bdb21863983277d3283105c88b85a6166b Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: 705251d2899bc006e21ff3e34a3fc3eba2dd4d00 Original-Change-Id: I7488533b83b8119f8c85cbf2c2eeddabb8e9487d Original-Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/372579 Original-Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Original-Tested-by: Patrick Georgi <pgeorgi@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16363 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-08-18Kconfig: rename BOOT_MEDIA_SPI_BUS to BOOT_DEVICE_SPI_FLASH_BUSAaron Durbin
Provide a default value of 0 in drivers/spi as there weren't default values aside from specific mainboards and arch/x86. Remove any default 0 values while noting to keep the option's default to 0. BUG=chrome-os-partner:56151 Change-Id: If9ef585e011a46b5cd152a03e41d545b36355a61 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16192 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Martin Roth <martinroth@google.com>
2016-07-25apollolake: Move CHROMEOS config to SoCFurquan Shaikh
All the mainboards share the same config options for CHROMEOS. Instead of duplicating those in every mainboard, move the CHROMEOS config to SoC and make it dependent on MAINBOARD_HAS_CHROMEOS. BUG=chrome-os-partner:55431 Change-Id: I2d54ff6beac9fca7596a8f104e3c1447cada5c05 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/15821 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-07-24google/reef: Enable PS/2 keyboard driver by defaultDuncan Laurie
This device has a built-in keyboard that should be enabled by default or it will not work in firmware. This was tested to ensure that TAB (display info) and Ctrl+D (enter developer mode) are functional at the Chrome OS recovery screen. BUG=chrome-os-partner:55549 Change-Id: I60156f1fc001b88deac69e03e02e9d8277fbc38d Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/15782 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-19mainboard/google/reef: explicitly set shipping Chrome OS optionsAaron Durbin
The Chrome OS options that will be shipped on this platform were being set in the chromium repo with an external config file. Set the options in the mainboard Kconfig file so there's no discrepancy as to what will be used. Change-Id: I05f0d1245611c16f54273728519a08e6edff3429 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15733 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-07-08mainboard/google/reef: Use device driver for DA7219 configurationDuncan Laurie
Use the device driver for DA7219 device configuration in the SSDT and remove the static copy in the DSDT. Tested on reef to ensure that the generated SSDT contents are equivalent to the current DSDT contents. Change-Id: I288eb05d0cb3f5310c4dca4aa1eab5a029f216af Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/15539 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-08google/reef: Add Maxim98357a supportHarsha Priya
Adds Maxim98357a support for reef using the generic driver in drivers/generic/max98357 Change-Id: I333d4e810e42309ac76dd90c19f05cf3e3a517e0 Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com> Reviewed-on: https://review.coreboot.org/15435 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-02google/reef: ACPI: Move touchpad to SSDT and remove TPMDuncan Laurie
Instantiate the touchpad using the drivers/i2c/generic device driver to generate the ACPI object in the SSDT. There is not currently a separate wake pin for this device, this will be added in EVT hardware. This was tested on the reef board by ensuring that the touchpad device continues to work in the OS. Also remove the LPC TPM from the DSDT as it is not present. Change-Id: I3151a28f628e66f63033398d6fab9fd8f5dfc37b Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/15481 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-01mainboard/google/reef: Use common NHLTSaurabh Satija
Add ACPI NHLT table generation that the current hardware supports. Reef supports two audio codecs, Dialog 7219 for headsets and Maxim 98357 for speakers. Change-Id: Ie39947960c86b8f65140834e31f9ed9f1b578485 Signed-off-by: Saurabh Satija <saurabh.satija@intel.com> Reviewed-on: https://review.coreboot.org/15440 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-22mainboard: Remove use of IFD_BIOS_START/IFD_BIOS_ENDFurquan Shaikh
BUG=chrome-os-partner:54563 Change-Id: If07710333cbb84ce70d6d4fa40602a74c898c08a Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/15293 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-06-16google/reef: Update flash size to 16MiBFurquan Shaikh
Use entire 16MiB flash size on reef. Adjust SIGN_CSE region accordingly. BUG=chrome-os-partner:54390 Change-Id: I94de509bdb2aa94625814123bf4d9758bfa37fc9 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/15191 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-06-02google/reef: Select UART_FOR_CONSOLE for reefFurquan Shaikh
Change-Id: I714af8ab552dc1923a1b64e0c502d6c7b96dd444 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/15044 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-05-27mainboard/google/reef: increase BIOS region sizeAaron Durbin
An updated descriptor expands the BIOS region while descreasing the 'device expansion region' utilized by the CSE. Update the end region marker to reflect this new size as well as the chromeos.fmd file which needs to be adjusted for logical boot parition 2 requirement which resides halfway through the BIOS region. The GBB was moved and shunk to accommodate the change. Change-Id: I7baa5282d7c608af648b5773c4dfa123060a6e45 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/14974 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins)
2016-05-13mainboard/google: add reef reference boardAaron Durbin
This adds the initial scaffolding for the reef reference board. One big thing missing is the GPIO configuration. Change-Id: I8e2d275df296bb397bb33dbd0c66fc87c82ff10f Signed-off-by: Aaron Durbni <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/14798 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@google.com> Reviewed-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-30 06:35:07 +0000