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path: root/src/mainboard/google/rauru
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2024-11-06soc/mediatek/mt8196: Disable irq2axi featureRunyang Chen
Irq2axi translates wire-based interrupt into message signal interrupt. Since MT8196 uses legacy wire-based interrupt, this feature needs to be disabled. If the interrupt is not handled, it will cause the system fail to boot. TEST=Build pass, check irq2axi_disable log and the interrupt can be correctly handled by checking /proc/interrupts. BUG=b:317009620 Signed-off-by: Runyang Chen <runyang.chen@mediatek.corp-partner.google.com> Change-Id: I0e89a0ee75e574a4b9e8df0a0f6a5f6e03bba2d6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/84896 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-11-06mb/google/rauru: Complete PCIe reset in romstageYidi Lin
De-assert PERST# at romstage to reduce the waiting time in ramstage. BUG=b:361728592 TEST=The boot time improves 62ms Change-Id: I2cd5cd59e7513b6e4036c3e8013a3c7322d2f787 Signed-off-by: Yidi Lin <yidilin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84895 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@google.com>
2024-10-31mb/google/rauru: Pre-initialize PCIe at the bootblock stageJianjun Wang
According to the PCIe CEM specification, the deassertion of PERST# should occur at least 100ms after the assertion. Right now we simply wait for 100ms in ramstage for that. To speed up the boot time, pre-initialize PCIe by asserting PERST# earlier in the bootblock stage. The pre-initialization time is stored in the early init data region, so that the PCIe initialization in ramstage could make sure the required 100ms delay is still reached. This pre-initialization will speed up the boot time by 100ms on rauru. TEST=Build pass, show pcie init pass log: mtk_pcie_domain_enable: PCIe link up success (1) BUG=b:317009620 Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com> Change-Id: I2b84c25ae3ea9069fd38fa6b20b8235a7fc3a484 Reviewed-on: https://review.coreboot.org/c/coreboot/+/84699 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2024-10-28mb/google/rauru: Add PCIe domain supportJianjun Wang
Add PCIe domain support. TEST=Build pass, show pcie init pass log: mtk_pcie_domain_enable: PCIe link up success (1) BUG=b:317009620 Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com> Change-Id: I3e06dfaf79924cd5352348afaa526fc7dedbb540 Reviewed-on: https://review.coreboot.org/c/coreboot/+/84700 Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-10-28mb/google/rauru: Add mainboard_needs_pcie_initJianjun Wang
Add a trivial mainboard_needs_pcie_init implementation that always return true. For now, the storage types of rauru SKUs are still unknown. TEST=Build pass, show pcie init pass log: mtk_pcie_domain_enable: PCIe link up success (1) BUG=b:317009620 Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com> Change-Id: I6b4f08e15f62da18aa37226075894f2827a9e7ba Reviewed-on: https://review.coreboot.org/c/coreboot/+/84697 Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-10-19mb/google/rauru: Add new board variant NaviLeo Chou
Add a new Rauru follower 'Navi'. BUG=b:341210522 TEST=emerge-cherry coreboot Change-Id: Ia2a6c1c09b3cedc0ef7f51ec93fdabf2c07c8885 Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84694 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-10-19mb/google/rauru: Add NAU8318 supportAmanda Huang
NAU8318 supports beep function via GPIO control. Configure the GPIO pins and pass them to the payload. BUG=b:343143718 TEST=Verify beep function through CLI in depthcharge successfully. We can test with: firmware-shell: badusbbeep firmware-shell: devbeep Change-Id: I79277bc1947dab517dea5aba583c5b4e0ac81bc4 Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84693 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-10-19mb/google/rauru: Configure the fingerprint pinsYidi Lin
There is no powering-on control in the fingerprint kernel driver. The fingerprint team of ChromeOS suggests powering-on FP MCU in the FW. Follow trogdor to pull down FP_RST_1V8_S3_L, AP_FP_FW_UP_STRAP, EN_PWR_FP and pull up EN_PWR_FP in ramstage for power rail to be stable. BUG=b:340401582 TEST=measure waveform and the fingerprint works on ChromeOS Change-Id: I05600d90fdf922faeb778a36d8a08f68c1bb4125 Signed-off-by: Yidi Lin <yidilin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84692 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yidi Lin <yidilin@google.com>
2024-10-19mb/google/rauru: Pass XHCI_INIT_DONE to the payloadYidi Lin
Configure GPIO EINT28 (XHCI_INIT_DONE) as output, so that payloads (for example depthcharge) can assert it to notify EC to enable USB VBUS. BUG=b:317009620 TEST=emerge-rauru coreboot Change-Id: I5950974435b56997626886b16d371cd8e6472e3c Signed-off-by: Yidi Lin <yidilin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84691 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yidi Lin <yidilin@google.com>
2024-08-29mb/google/rauru: Reset USB hub in bootblockYidi Lin
We have to reset the USB hub as early as possible. Otherwise the USB3 hub may not be usable in the payload. This design has been introduced since Cherry. TEST=build pass. BUG=b:317009620 Change-Id: Iea793b4b04bd009d0354e2331604bccf30466a23 Signed-off-by: Jarried Lin <jarried.lin@mediatek.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84024 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-08-29mb/google/rauru: Setup USB host in ramstageMingjin Ge
Add usb host function support. TEST=read usb data successfully. BUG=b:317009620 Signed-off-by: Mingjin Ge <mingjin.ge@mediatek.corp-partner.google.com> Change-Id: I5d081ff3e7367b87fab5ebdcb148c9005ab583f5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/84022 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2024-08-24mb/google/rauru: Initialize flash controller in bootblockJarried Lin
Initialize SPI NOR Flash Controller (SNFC) in the bootblock. TEST=read nor flash data successfully. BUG=b:317009620 Change-Id: I88960ce7a50f67ea6f402884b714cb205836a6d8 Signed-off-by: Noah Shen <noah.shen@mediatek.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83924 Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-07-23mb/google/rauru: Add MediaTek MT8196 reference boardJarried Lin
Add mainboard folder and drivers for new reference board 'Rauru'. TEST=saw the coreboot uart log to bootblock BUG=b:317009620 Signed-off-by: Jarried Lin <jarried.lin@mediatek.corp-partner.google.com> Change-Id: I789b622dcda999635f7aa2ce40adea6db28afa0e Reviewed-on: https://review.coreboot.org/c/coreboot/+/83573 Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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