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2014-05-07rambi: Remove outdated commentPatrick Georgi
Change-Id: Ic555d23a9112677a784dd814601f8202d4d17261 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/5691 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins)
2014-05-07rambi: handle single channel configsAaron Durbin
Some 1.5 boards have a single channel ram configuration. Accomodate such configs. BUG=chrome-os-partner:22865 BRANCH=None TEST=Built and booted ChromeOS. Change-Id: I513327e47b9211d2dd1ea960d7da671a3773cb91 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/178340 Reviewed-by: Nick Sanders <nsanders@chromium.org> Tested-by: Bernie Thompson <bhthompson@chromium.org> Tested-by: Nick Sanders <nsanders@chromium.org> Reviewed-on: http://review.coreboot.org/4983 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-07rambi: use SERIRQ pad as keyboard irq in gpio modeAaron Durbin
The level shifting between 3.3V and 1.8V for the SERIRQ signal is not working. Instead use the SERIRQ pad as a gpio which is used as a direct IRQ signal for the keyboard interupt. BUG=chrome-os-partner:23965 BRANCH=None TEST=Built and booted rambi. Keyboard works with associated EC change. CQ-DEPEND=CL:177189 Change-Id: Ifc270ca38207828a6d4711551d4bde9121559cca Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/177223 Tested-by: Bernie Thompson <bhthompson@chromium.org> Reviewed-on: http://review.coreboot.org/4979 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-07rambi: make ramids non-legacy gpio inputsAaron Durbin
The romstage code for rambi uses the mmio way of reading inputs. However, this is a problem is the GPIOs are set up as legacy mode. Subsequent warm resets mean the ram_id is read incorrectly. Ensure the ram_id is read consistently by keeping the GPIOs for ram_id in mmio mode. BUG=chrome-os-partner:24085 BRANCH=None TEST=Built and booted. And rebooted. Now seeing consistent ram_id values on warm resets. Change-Id: Ieff98c000be80998854f325754f1e819975d2be5 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/177230 Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: http://review.coreboot.org/4977 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-07rambi: distribute IRQs away from PIRQA on pci devicesAaron Durbin
Some of the drivers in the kernel were not so happy about having shared IRQs. Also, sharing IRQs means more code needs to be run in interrupt context to determine if the IRQ was meant for a particular device. Fix this. No more 'mmc1: got irq while runtime suspended' messages. BUG=chrome-os-partner:24056 BRANCH=None TEST=Built and booted. Looked at /proc/interrupts and noted no more sharing between pci devices. Change-Id: Ie5da102204ffe3156dd55ab17af77df245a57c97 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/176792 Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: http://review.coreboot.org/4973 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-07rambi: fixup settings so trackpad can be found in kernelAaron Durbin
The kernel chromeos_laptop driver nomenclature expects the board name to not be in all caps. Fix this as well as the i2c address for the trackpad. BUG=chrome-os-partner:24307 BRANCH=None TEST=Built and booted. trackpad device is found. IRQs still not working yet. Change-Id: Id6be8ee4bce2835e303ea4fe63944be80d2d7ec2 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/176680 Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: http://review.coreboot.org/4970 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-07rambi: Add DIRQs for trackpad and touchscreenShawn Nematbakhsh
Also add the relevant info about these pins to the ASL tables + add SMBIOS type 41 data for these parts. BUG=chrome-os-partner:22863 TEST=Manual on Rambi. Set some pins to GPIO_DIRQ, and then verify DIRQ regwrites w/ GPIO_DEBUG look correct. Change-Id: Id40655f9fb2ea7b10e1ff58d0b2a8b4cc6f05ff8 Reviewed-on: https://chromium-review.googlesource.com/176299 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Commit-Queue: Shawn Nematbakhsh <shawnn@chromium.org> Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Tested-by: Shawn Nematbakhsh <shawnn@chromium.org> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4963 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-06rambi: disable HDA deviceAaron Durbin
For some reason HDA can now be disabled. It's unclear what changes in the baytrail code allowed this to happen, sadly. BUG=chrome-os-partner:22871 BRANCH=None TEST=Noted hda is not in lspci. Change-Id: I64e2560533be6f701fa66cd53c906b62b09012ed Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/176394 Reviewed-on: http://review.coreboot.org/4961 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-06rambi: enable SCI and SMI gpiosAaron Durbin
Rambi has 3 pins that need to be configured for SCI and SMI: 1. GPIO_CORE[0] - runtime SCI pin 2. GPIO_SUS[7] - SMI for firmware lid events 3. GPIO_SUS[0] - wake pin for S3 wakes from EC. Configure these pins now that the rest of the infrastructure is in place. The one thing that is yet to work is runtime SCI for lid events once booted. BUG=chrome-os-partner:23505 BRANCH=None TEST=built and booted. lid close at rec screen works. And wake from S3 with a keyboard press works. Change-Id: I5f8e38ec5f4cf1a8ef7aa7fcee9abc344d9b184f Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/176393 Reviewed-on: http://review.coreboot.org/4960 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-06rambi: mainboard EC - SCI and SMI fixesAaron Durbin
As rambi is a baytrail board it doesn't have a dedicated wake pin. Therefore, one needs to enable the proper GPIO to wake up the sytem before going into S3. BUG=chrome-os-partner:23505 BRANCH=None TEST=Put system into S3. Keyboard press created wake event. Also, typed 'lidclose' on EC console while at recovery screen. Machine properly shutdown. Change-Id: Ic67b6bce93d57c620f498505d83197e4ae34a07d Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/176392 Reviewed-on: http://review.coreboot.org/4959 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-06rambi: include the EC devices normally on superioAaron Durbin
The superio.asl file allows for the mainboard to hang devices off of the LPC bus in ACPI. Include the keyboard controller, EC memory map, and host interface's resources. BUG=chrome-os-partner:23505 BRANCH=None TEST=Built and booted. Noted resource reservations in dmesg. Change-Id: Ida6481cd4c4725b5d3946bc64179ee99c93b0106 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/176134 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/4950 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-06rambi: update EC supportAaron Durbin
Fix the SMI and SCI gpios for Rambi. Also, add in the EC callbacks for the SMI handler. Note that the handler for GPI SMIs has not been tested yet as baytrail chipset code doesn't yet support setting up those configurations yet. BUG=chrome-os-partner:23505 BRANCH=None TEST=Noted that SCI was enabled in /sys/firmware/acpi/interrupts for the EC's SCI GPI. Also was able to see Chrome EC messages with CONFIG_DEBUG_SMI and powering down at the dev screen. Change-Id: I67b278fd38e1c09271d2c1e16e42f6e8c49e3a70 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/176077 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/4948 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-06baytrail: configure acpi SCI irqAaron Durbin
Baytrail has a configurable SCI irq. Add support for properly configuring SCI irq. Note that it is currently fixed to IRQ9, but the code supports setting it to the other supported values. The current mainboards using baytrail defer the madt IRQ override information to the chipset. BUG=chrome-os-partner:23505 BRANCH=None TEST=Built and booted. Noted 'SCI is IRQ9' message. Change-Id: I7b307bd58f9de944f0cb4c116107a15345499f2e Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/176075 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/4946 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-06rambi: mirror bayleybay's eMMC gpio setupAaron Durbin
These changes to the eMMC pads allows the kernel to see the eMMC device. One is able to install onto the eMMC device, and the kernel is loaded and booted from eMMC device. Note, that it may not fully boot because of other issues such as not-completely working ACPI support. BUG=chrome-os-partner:22580 BRANCH=None TEST=booted off of usb drive. can see eMMC device. Change-Id: I9c088398297a0b559383bdf4a389dd19a1110e0f Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/176073 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/4945 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-06rambi: Fix eDP panel functionalityDuncan Laurie
For some mysterious reason GPIO_S0_NC22 is making the eDP panel go entirely white when it is configured with internal pullup. Since these (supposedly XDP related) pins are unknown functionality lets set them to GPIO_DEFAULT instead of GPIO_NC. Additionally the VBIOS is being changed to issue int15 callback to determine the boot graphics device. If we list both LFP and EFP then the dev/rec screens will show on the panel when HDMI is not attached and otherwise will display on HDMI. BUG=chrome-os-partner:23507 BRANCH=rambi TEST=build and boot on rambi, see firmware/kernel screens on the panel when HDMI is not attached, and firmware screens on the panel and kernel screens on both when HDMI is attached. Change-Id: Ieb05a591d63c4f8e09fa154eeb76004d32579508 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/175952 Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4944 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-05baytrail: fix up FADTAaron Durbin
The FADT for baytrail had incorrect offsets leading to the kernel spewing a huge mess of ACPI errors. Fix these offsets to be initialized in the chipset code. BUG=chrome-os-partner:23505 BRANCH=None TEST=Built and booted into kernel on rambi. Login screen comes up. Change-Id: I89fc2a4fd800ff01cedf89b51cfb1369aceb9f03 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/175663 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/4941 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-05baytrail: interrupt routing supportAaron Durbin
This provides the initial support for interrupt routing in bay trail. It includes both acpi changes and board changes to ensure the interdependencies are met with the current ASL code. The PIRQ routing is handled by the mainboard exporting an irqroute.h header that describes the per device and PIRQ PCI settings. There are still a lot of ACPI errors in the kernel with this change, though. BUG=chrome-os-partner:23505 BRANCH=None TEST=Built and booted rambi into kernel. Signed-off-by: Aaron Durbin <adurbin@chromium.org> Change-Id: Id8a865a24fc8d49743c0b54efdb64aaef52fcd8e Reviewed-on: https://chromium-review.googlesource.com/175700 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/4940 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-03Move ARCH_* from board/Kconfig to cpu or soc Kconfig.Furquan Shaikh
CONFIG_ARCH is a property of the cpu or soc rather than a property of the board. Hence, move ARCH_* from every single board to respective cpu or soc Kconfigs. Also update abuild to ignore ARCH_ from mainboards. Change-Id: I6ec1206de5a20601c32d001a384a47f46e6ce479 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: http://review.coreboot.org/5570 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-01ChromeOS: Use common fill_lb_gpio()Kyösti Mälkki
Change-Id: I2ba7a1c2b2e6ce2c00c9a2916141bed67930ba2d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5586 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-05-01ChromeOS: Remove oprom_is_loadedKyösti Mälkki
A global flag oprom_is_loaded was used to indicate to U-boot that VGA option ROM was loaded and run, or that native VGA init was completed on GMA device. Implement this feature without dependency to CHROMEOS option and replace use of global variable oprom_is_loaded with call to gfx_get_init_done(). Change-Id: I7e1afd752f18e5346dabdee62e4f7ea08ada5faf Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/4309 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-04-30baytrail: Clean up NVS regionDuncan Laurie
There is a lot of NVS allocated to things that are not really used. Most of these are removed and some are moved around. Thermals are expected to be handled with DPTF so I've removed that bit of code but have not yet cleaned up the thermal zone. I left in the SIO BARs since I think we will need those still even though they may need work still. BUG=chrome-os-partner:23505 BRANCH=rambi TEST=build and boot on rambi Change-Id: Id16ee67e6b3709a303c001afd72947147f938127 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/175626 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4936 Tested-by: build bot (Jenkins)
2014-04-30baytrail: Add reserved MMIO regions to ACPIDuncan Laurie
Add a length define for all the reserved MMIO regions and use them in the ACPI code to reserve the regions there. Add a region for the "abort page" documented in the EDS. BUG=chrome-os-partner:23505 BRANCH=rambi TEST=build and boot on rambi Change-Id: I2060dca0636a2fdc0533ddd0826f94add2c272c3 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/175624 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4934 Tested-by: build bot (Jenkins)
2014-04-30baytrail: Fix XHCI problems and re-enableDuncan Laurie
- a few clock gating bits were set improperly and were preventing the system from transitioning out of S0 state. - the XHCC registers were not getting the top byte set properly which includes things like DMA write request size and request boundary crossing control. This was causing memory corruption. BUG=chrome-os-partner:23635 BRANCH=rambi TEST=build and boot kernel from USB on rambi with XHCI driver Change-Id: I8e8135a793dfbaa1f163766702e3a8f19bba9703 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/175558 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4933 Tested-by: build bot (Jenkins)
2014-03-28mainboard/*/*/ec.c: Do not include `chromeos/chromeos.h`Paul Menzel
It's not needed and causes build failures without CONFIG_CHROMEOS. Change-Id: I7923717bfc5c84698044008e5f2441206041e0dd Reported-by: Idwer Vollering <vidwer@gmail.com> Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/5398 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-03-11rambi: Enable USB boot with EHCI controllerDuncan Laurie
This adds the EHCI driver back to libpayload and configures the devicetree to route ports to EHCI. This is hopefully just temporary until the issues with XHCI can be worked out. BUG=chrome-os-partner:23635 BRANCH=rambi TEST=build and boot from USB on rambi Change-Id: I0549661f5e5fd83477f4839a05e7e21175b24b64 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/175513 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4931 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-02-27baytrail: fix uninitialized acpi structuresAaron Durbin
The callers of the following functions assume the storage area provided by the pointers is initialized. That's not the case as these were just place holders. - void acpi_create_intel_hpet(acpi_hpet_t * hpet); - void acpi_create_serialio_ssdt(acpi_header_t *ssdt); To fix this properly initialize the hpet entry, and just remove the serialio_ssdt function entirely. BUG=chrome-os-partner:23505 BRANCH=None TEST=Built and booted through depthcharge on rambi. Noted no more ACPI errors relating to invalid length. Change-Id: If56ab033562ef2d755e9c9de42f507c95d291aba Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/174716 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/4917 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-02-27rambi: Enable internal keyboardDuncan Laurie
The EC LPC init function needs to run to enable the internal keyboard. I needed this to confirm that it is just USB keyboards that are causing all sorts of issues. BUG=chrome-os-partner:23635 BRANCH=rambi TEST=boot to recovery screen and hit tab Change-Id: Iea0fc66ba62ea7da71ef83c26e25ae32bef102bd Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/175207 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4915 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
2014-02-27rambi: Enable SATA portShawn Nematbakhsh
Enable first SATA port in Rambi device tree. BUG=chrome-os-partner:23643 TEST=TEST=Manual, in dev mode. Verify on rambi that SATA disk is detected, and kernel is found + booted. Change-Id: Ic0cb5f9ff17ca0f6cc7941f203b9338df200811d Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/174916 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4914 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
2014-02-27rambi: add all on-board devicesAaron Durbin
Add the on-board devices in the SoC to the device tree. Also, disable the unused devices aside from TXE and HDA. Those particular devices cause the system to shut down when they are disabled. BUG=chrome-os-partner:22871 BRANCH=None TEST=Built and booted through depthcharge. Noted the calls to the southcluster disable function. Change-Id: I482c1c9609833054aeb2948144af54b57d3df086 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/174645 Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: http://review.coreboot.org/4912 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
2014-02-24rambi: add chromeos EC supportAaron Durbin
As rambi has the ChromeOS EC on it the EC needs to be configured properly. Do this along with updating the ChromeOS support for passing on write protect state, recovery mode and developer mode. BUG=chrome-os-partner:23387 BRANCH=None TEST=Built and booted to depthcharge. EC software sync appears to work correctly. Additionaly, 'mainboard_ec_init' appears in the console output. Change-Id: I40c5c9410b4acaba662c2b18b261dd4514a7410a Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/174714 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/4905 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-02-17rambi: Set VBOOT_RAMSTAGE_INDEX to point to ramstage imageShawn Nematbakhsh
The ramstage image is the third image in the partition (after ECRW hash and depthcharge image). TEST=Manual. Boot rambi, verify that ramstage image is correctly found: "RW ramstage image at 0xffb1dc70, 0x0000f391 bytes" BUG=None. Change-Id: I628db3daf0b109106c51693960487a0c83b4e9f4 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/174540 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4899 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-02-16rambi: add BSP lapic deviceAaron Durbin
There's some baked in assumptions internal to coreboot that the BSP's cpu device exists in the device tree. Therefore provide one in the device tree. BUG=chrome-os-partner:22862 BRANCH=None TEST=Compiled and booted with other changes. Change-Id: I22ba10964760ee8efbc5bbd5d4ce65daf31b3839 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/173702 Reviewed-on: http://review.coreboot.org/4887 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-02-16rambi: disable internal pullups on ram_id[2:0]Aaron Durbin
The ram_id[2:0] signals have stuffing options for pull up/down with values of 10K. However, the default pulldown values for these pads are 20K. Therefore, one can't read a high value because of the high voltage threshold is 0.65 * Vref. Therefore the high signals are marginal at best. Fix this issue by disabling the internal pull for the pads connected to ram_id[2:0]. BUG=chrome-os-partner:23350 BRANCH=None TEST=Built and checked that ram_id[2:0] is properly read now. Change-Id: Ib414d5798b472574337d1b71b87a4cf92f40c762 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/173211 Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-by: Bernie Thompson <bhthompson@chromium.org> Reviewed-on: http://review.coreboot.org/4885 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-02-14google/rambi: Do not select CHROMEOS in KconfigAlexandru Gagniuc
CHROMEOS is the meant to be selected by the user. The correct variable for a mainboard to select is MAINBOARD_HAS_CHROMEOS. This will then default to a CHROMEOS build, but when the mainboard selects CHROMEOS, the user can no longer disable CHROMEOS. Change-Id: I78fb15a0a9fef733e2de064d6c09cf774b7bce78 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/5218 Reviewed-by: Aaron Durbin <adurbin@google.com> Tested-by: build bot (Jenkins)
2014-02-12google boards: Do not hardcode location of spd.binAlexandru Gagniuc
spd.bin can reside anywhere in CBFS, and we only use CBFS APIs to access and read it. As such, there is no need to hardcode it, and it can collide with mrc.bin or mrc.cache on some boards. Do not use a specific position for spd.bin, but instead let cbfstool find the optimal placement. Change-Id: I496094d3c0de708813494095b7ac4be8addb4112 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/5210 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-02-11rambi: Add platform GPIO configuration tablesShawn Nematbakhsh
Configure GPIOs according to function on board. TEST=compile only. BUG=chrome-os-partner:22863 Change-Id: Ic38eeb64149606f2d7a19cc7a0144cc7e24807b8 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/172657 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4875 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-02-11rambi: Add ncore GPIO config tablesShawn Nematbakhsh
gpncore config tables were previously missing -- add them. Also, make the baytrail GPIO/PAD LUTs easier to read. TEST=Manual. Build + boot on bayleybay. BUG=chrome-os-partner:22865 Change-Id: I49a1b23c7ad4fb5f4c86618e8c78ea9a1a42f79d Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/172510 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4874 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-02-11rambi: add per-sku SPD supportAaron Durbin
There are currently 4 SKUs: 0b000 - 4GiB total - 2 x 2GiB Micron MT41K256M16HA-125:E 1600MHz 0b001 - 4GiB total - 2 x 2GiB Hynix H5TC4G63AFR-PBA 1600MHz 0b010 - 2GiB total - 2 x 1GiB Micron MT41K128M16JT-125:K 1600MHz 0b011 - 2GiB total - 2 x 1GiB Hynix H5TC2G63FFR-PBA 1600MHz Add each of the 4 spds to the build, and use the proper parameters to MRC to use the in-memory SPD information. BUG=chrome-os-partner:22865 BRANCH=None TEST=Built. Noted 1024 bytes of SPD content. Change-Id: Ife96650f9b0032b6bd0d1bdd63b8970e29868365 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/172280 Reviewed-on: http://review.coreboot.org/4872 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-02-06MTRR: Mark all prefetchable resources as WRCOMB.Vladimir Serbinenko
Change-Id: I2ecfd9733b65b6160bc2232d22db7b16692a847f Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/5149 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-02-05mainboard/google: add initial rambi mainboard supportAaron Durbin
BUG=chrome-os-partner:23121 BRANCH=None TEST=None Change-Id: I283415be326e2d92e1e1bf7866954f17a7266edb Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/171940 Reviewed-by: Bernie Thompson <bhthompson@chromium.org> Reviewed-on: http://review.coreboot.org/4865 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>