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This patch renames cbfs_boot_map_with_leak() and cbfs_boot_load_file()
to cbfs_map() and cbfs_load() respectively. This is supposed to be the
start of a new, better organized CBFS API where the most common
operations have the most simple and straight-forward names. Less
commonly used variants of these operations (e.g. cbfs_ro_load() or
cbfs_region_load()) can be introduced later. It seems unnecessary to
keep carrying around "boot" in the names of most CBFS APIs if the vast
majority of accesses go to the boot CBFS (instead, more unusual
operations should have longer names that describe how they diverge from
the common ones).
cbfs_map() is paired with a new cbfs_unmap() to allow callers to cleanly
reap mappings when desired. A few new cbfs_unmap() calls are added to
generic code where it makes sense, but it seems unnecessary to introduce
this everywhere in platform or architecture specific code where the boot
medium is known to be memory-mapped anyway. In fact, even for
non-memory-mapped platforms, sometimes leaking a mapping to the CBFS
cache is a much cleaner solution than jumping through hoops to provide
some other storage for some long-lived file object, and it shouldn't be
outright forbidden when it makes sense.
Additionally, remove the type arguments from these function signatures.
The goal is to eventually remove type arguments for lookup from the
whole CBFS API. Filenames already uniquely identify CBFS files. The type
field is just informational, and there should be APIs to allow callers
to check it when desired, but it's not clear what we gain from forcing
this as a parameter into every single CBFS access when the vast majority
of the time it provides no additional value and is just clutter.
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: Ib24325400815a9c3d25f66c61829a24a239bb88e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39304
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-by: Mariusz Szafrański <mariuszx.szafranski@intel.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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unused includes of <stdin.h> found using following commande:
diff <(git grep -l '#include <stdint.h>' -- src/) <(git grep -l
'int8_t\|uint8_t\|int16_t\|uint16_t\|int32_t\|uint32_t\|int64_t\|
uint64_t\|intptr_t\|uintptr_t\|intmax_t\|uintmax_t\|s8\|u8\|s16\|
u16\|s32\|u32\|s64\|u64\|INT8_MIN\|INT8_MAX\|UINT8_MAX\|INT16_MIN\
|INT16_MAX\|UINT16_MAX\|INT32_MIN\|INT32_MAX\|UINT32_MAX\|INT64_MIN\
|INT64_MAX\|UINT64_MAX\|INTMAX_MIN\|INTMAX_MAX\|UINTMAX_MAX' -- src/)
|grep '<' |grep -v vendor |grep -vF '.h'
Change-Id: Icb9b54c6abfb18d1e263665981968a4d7cccabeb
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41148
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Stefan thinks they don't add value.
Command used:
sed -i -e '/file is part of /d' $(git grep "file is part of " |egrep ":( */\*.*\*/\$|#|;#|-- | *\* )" | cut -d: -f1 |grep -v crossgcc |grep -v gcov | grep -v /elf.h |grep -v nvramtool)
The exceptions are for:
- crossgcc (patch file)
- gcov (imported from gcc)
- elf.h (imported from GNU's libc)
- nvramtool (more complicated header)
The removed lines are:
- fmt.Fprintln(f, "/* This file is part of the coreboot project. */")
-# This file is part of a set of unofficial pre-commit hooks available
-/* This file is part of coreboot */
-# This file is part of msrtool.
-/* This file is part of msrtool. */
- * This file is part of ncurses, designed to be appended after curses.h.in
-/* This file is part of pgtblgen. */
- * This file is part of the coreboot project.
- /* This file is part of the coreboot project. */
-# This file is part of the coreboot project.
-# This file is part of the coreboot project.
-## This file is part of the coreboot project.
--- This file is part of the coreboot project.
-/* This file is part of the coreboot project */
-/* This file is part of the coreboot project. */
-;## This file is part of the coreboot project.
-# This file is part of the coreboot project. It originated in the
- * This file is part of the coreinfo project.
-## This file is part of the coreinfo project.
- * This file is part of the depthcharge project.
-/* This file is part of the depthcharge project. */
-/* This file is part of the ectool project. */
- * This file is part of the GNU C Library.
- * This file is part of the libpayload project.
-## This file is part of the libpayload project.
-/* This file is part of the Linux kernel. */
-## This file is part of the superiotool project.
-/* This file is part of the superiotool project */
-/* This file is part of uio_usbdebug */
Change-Id: I82d872b3b337388c93d5f5bf704e9ee9e53ab3a9
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41194
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Done with sed and God Lines. Only done for C-like code for now.
Change-Id: I0dea26da28a2879e34593907fef6f984317c347f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40191
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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They're listed in AUTHORS and often incorrect anyway, for example:
- What's a "Copyright $year-present"?
- Which incarnation of Google (Inc, LLC, ...) is the current
copyright holder?
- People sometimes have their editor auto-add themselves to files even
though they only deleted stuff
- Or they let the editor automatically update the copyright year,
because why not?
- Who is the copyright holder "The coreboot project Authors"?
- Or "Generated Code"?
Sidestep all these issues by simply not putting these notices in
individual files, let's list all copyright holders in AUTHORS instead
and use the git history to deal with the rest.
Change-Id: I09cc279b1f75952bb397de2c3f2b299255163685
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39607
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
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Change-Id: I99440539d7b7586df66395776dcd0b4f72f66818
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34964
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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These platforms use different signature for this function, so
declare them with different name to make room in global namespace.
Change-Id: I77be9099bf20e00ae6770e9ffe12301eda028819
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34909
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Drop 'include <string.h>' when it is not used and
add it when it is missing.
Also extra lines removed, or added just before local includes.
Change-Id: Iccac4dbaa2dd4144fc347af36ecfc9747da3de20
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31966
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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Change-Id: If450a68e98261ffba4afadbce47c156c7e89e7e4
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26460
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Some variants need the internal pull resistor on GPIO_SSUS_40
set explicitly to pull down rather than disabling the pull,
in order for the ram-id to be read correctly via GPIO.
Correct this by adding a function to enable and set the internal pull
and define its use as needed in the board's variant.h.
Chromium source:
branch: firmware-gnawty-5216.239.B
/src/soc/intel/baytrail/baytrail/gpio.h#418
/src/mainboard/google/gnawty/romstage.c#60
Test: boot 4GB Candy board and observe correct RAM id, amount detected
Change-Id: I8823c27385f4422184b5afa57f6048f7ff2a25ab
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/18309
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Add new ChromeOS devices banjo, candy, clapper, glimmer, gnawty,
heli, kip, orco, quawks, squawks, sumo, swanky, and winky using
their common reference board (rambi) as a base.
Chromium sources used:
firmware-banjo-5216.334.B 32ec493 [chromeos: vboot_loader: Set...]
firmware-candy-5216.310.B 519ff11 [baytrail: Preserve VbNv around...]
firmware-clapper-5216.199.B 80d55e3 [baytrail: add code for...]
firmware-glimmer-5216.198.B fae0770 [baytrail: add code for...]
firmware-gnawty-5216.239.B 952adb7 [Gnawty/Olay: Add 2nd source...]
firmware-heli-5216.392.B f1f3604 [helis: Lock ME / TXE section...]
firmware-kip-5216.227.B db3c5d9 [kip: update spd for for MT41K256M16*]
firmware-orco-5216.362.B 76f1651 [Orco: Adjust rx delay for norm.]
firmware-quawks-5216.204.B edb60c9 [Quawks: Update SPD data]
firmware-squawks-5216.152.B c6573dc [Squawks: Update SPD data]
firmware-sumo-5216.382.B c62b6f23 [Ninja, Sumo: Add SPD source...]
firmware-swanky-5216.238.B 233b2a7 [Swanky: update SPD table]
firmware-winky-5216.265.B ce91ffc [Add to support HT Micron...]
The same basic cleanup/changes are made here as with the initial BYT
variant commit:
- remove unused ACPI trackpad/touchscreen devices
- correct I2C addresses in SMBIOS entries
- clean up comment formatting
- remove ACPI device for unused light sensor
- switch I2C ACPI devices from edge to level triggered interrupts,
for better compatibility/functionality (and to be consistent
with other recently-upstreamed ChromeOS devices)
- Micron 2GB SPD file for kip with updated values renamed to distinguish
from same file used by other boards
Change-Id: Ic66f9b539afb5aff32c4c1a8563f6612f5a2927c
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/18164
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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Combine existing boards google/enguarde and google/ninja using
their common reference board google/rambi as a baseboard.
Variants contain board specific data:
- DPTF ACPI components
- I2C ACPI devices
- RAM config / SPD data
- devicetree config
- GPIOs
- board-specific HW components (e.g., LAN)
Additionally, some minor cleanup/changes were made:
- remove unused ACPI trackpad/touchscreen devices
- correct I2C addresses in SMBIOS entries
- clean up comment formatting
- remove ACPI device for unused light sensor
- switch I2C ACPI devices from edge to level triggered interrupts,
for better compatibility/functionality (and to be consistent
with other recently-upstreamed ChromeOS devices)
The existing enguarde and ninja boards are removed.
Variant setup modeled after google/auron
Change-Id: Iae7855af9a224fd4cb948b854494e39b545ad449
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/18129
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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It encourages users from writing to the FSF without giving an address.
Linux also prefers to drop that and their checkpatch.pl (that we
imported) looks out for that.
This is the result of util/scripts/no-fsf-addresses.sh with no further
editing.
Change-Id: Ie96faea295fe001911d77dbc51e9a6789558fbd6
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/11888
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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A new CBFS API is introduced to allow making CBFS access
easier for providing multiple CBFS sources. That is achieved
by decoupling the cbfs source from a CBFS file. A CBFS
source is described by a descriptor. It contains the necessary
properties for walking a CBFS to locate a file. The CBFS
file is then decoupled from the CBFS descriptor in that it's
no longer needed to access the contents of the file.
All of this is accomplished using the regions infrastructure
by repsenting CBFS sources and files as region_devices. Because
region_devices can be chained together forming subregions this
allows one to decouple a CBFS source from a file. This also allows
one to provide CBFS files that came from other sources for
payload and/or stage loading.
The program loading takes advantage of those very properties
by allowing multiple sources for locating a program. Because of
this we can reduce the overhead of loading programs because
it's all done in the common code paths. Only locating the
program is per source.
Change-Id: I339b84fce95f03d1dbb63a0f54a26be5eb07f7c8
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9134
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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As per discussion with lawyers[tm], it's not a good idea to
shorten the license header too much - not for legal reasons
but because there are tools that look for them, and giving
them a standard pattern simplifies things.
However, we got confirmation that we don't have to update
every file ever added to coreboot whenever the FSF gets a
new lease, but can drop the address instead.
util/kconfig is excluded because that's imported code that
we may want to synchronize every now and then.
$ find * -type f -exec sed -i "s:Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, *MA[, ]*02110-1301[, ]*USA:Foundation, Inc.:" {} +
$ find * -type f -exec sed -i "s:Foundation, Inc., 51 Franklin Street, Suite 500, Boston, MA 02110-1335, USA:Foundation, Inc.:" {} +
$ find * -type f -exec sed -i "s:Foundation, Inc., 59 Temple Place[-, ]*Suite 330, Boston, MA *02111-1307[, ]*USA:Foundation, Inc.:" {} +
$ find * -type f -exec sed -i "s:Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.:Foundation, Inc.:" {} +
$ find * -type f
-a \! -name \*.patch \
-a \! -name \*_shipped \
-a \! -name LICENSE_GPL \
-a \! -name LGPL.txt \
-a \! -name COPYING \
-a \! -name DISCLAIMER \
-exec sed -i "/Foundation, Inc./ N;s:Foundation, Inc.* USA\.* *:Foundation, Inc. :;s:Foundation, Inc. $:Foundation, Inc.:" {} +
Change-Id: Icc968a5a5f3a5df8d32b940f9cdb35350654bef9
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/9233
Tested-by: build bot (Jenkins)
Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
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This patch aligns baytrail to the new SoC header include scheme.
BUG=None
TEST=Tested with whole series. Compiled Rambi.
Change-Id: I0f0a894f6f33449756582eefa0b50bae545220db
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 1216a86538517c03a7e5bca547d08ff3dbcaa083
Original-Change-Id: If5d2a609354b3d773aa3d482e682ab97422fd9d5
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/222026
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9363
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@google.com>
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baytrail: combine SPI configuration in romstage
Reviewed-on: https://chromium-review.googlesource.com/185140
(cherry picked from commit 4e7f0e8ae1138e478ae7106d54719cf05e13b402)
baytrail: lock down registers before handoff
Reviewed-on: https://chromium-review.googlesource.com/185200
(cherry picked from commit 82cce4d2b46ccc554b71efa179b5d95756e2ad5e)
baytrail: invoke SMM finalization on handoff
Reviewed-on: https://chromium-review.googlesource.com/185201
(cherry picked from commit 1b50affb1fdda52a5986c9429713930ed517a86a)
rambi: don't invoke SMM finalization
Reviewed-on: https://chromium-review.googlesource.com/185202
(cherry picked from commit 6eff475dae7f4536eb846ccf6d51fce262b8ffef)
rambi: remove handling of APM_CNT_FINALIZE
Reviewed-on: https://chromium-review.googlesource.com/185203
(cherry picked from commit 9fc310d7e2730466cc7fcc84999502a2d4d08bab)
baytrail: don't increment boot count on S3 resume
Reviewed-on: https://chromium-review.googlesource.com/185381
(cherry picked from commit 940a0fa4df1ce335229eb6f80143b93a84ba358c)
rambi: enable HDA device
Reviewed-on: https://chromium-review.googlesource.com/184574
(cherry picked from commit 334f2a5c7c6540e744b6aaf7e1da0b55e1368196)
baytrail: lock down spi controller according to mainboard
Reviewed-on: https://chromium-review.googlesource.com/185631
(cherry picked from commit 696ece68cb6d522c248e800f168e675e4b4a7317)
rambi: implement mainboard_get_spi_config() to lock dow spi controller
Reviewed-on: https://chromium-review.googlesource.com/185632
(cherry picked from commit 1d9ba15858fd421a4fe5a47f7171273128e89524)
baytrail: introduce ssus_disable_internal_pull()
Reviewed-on: https://chromium-review.googlesource.com/185740
(cherry picked from commit 9d6056dd70b27183dab6a4656f4f9612ae870a4d)
rambi: fix write-protect gpio reading at romstage
Reviewed-on: https://chromium-review.googlesource.com/185741
(cherry picked from commit c64627689b1afec59be6fdab323d5492046f0bc7)
baytrail: DPTF: implement charger current limit
Reviewed-on: https://chromium-review.googlesource.com/185759
(cherry picked from commit 287e8936613a7a83281ff692b20383dacf7fcaf6)
rambi: Enable charger participant and define states
Reviewed-on: https://chromium-review.googlesource.com/185760
(cherry picked from commit 2f62a11927ecf10cb2c76a9f5d368d4050404137)
baytrail: increase command wait timeout
Reviewed-on: https://chromium-review.googlesource.com/185874
(cherry picked from commit 962a79ef72169b5d52fc746d1889d3b652fd9bcc)
baytrail: make caching MRC data more robust
Reviewed-on: https://chromium-review.googlesource.com/185875
(cherry picked from commit b5e10ad47b9e4f330caaee4faf69702f24d6bdd8)
baytrail: upgrade MRC wrapper header
Reviewed-on: https://chromium-review.googlesource.com/186391
(cherry picked from commit 8c1a62f1f4261d4f38aacbbb353c9d6218ec2885)
rambi: instruct MRC to use weaker memory ODT settings
Reviewed-on: https://chromium-review.googlesource.com/186420
(cherry picked from commit b9329126ca08d20ce1d8c5db0fcabd39140c7292)
rambi: Move touch wakeup resource GPIO to separate device
Reviewed-on: https://chromium-review.googlesource.com/186932
(cherry picked from commit ba44e2e04f9469c629cb61a911c8cd339f52b0ef)
baytrail: Set some MSRs related to turbo power
Reviewed-on: https://chromium-review.googlesource.com/186933
(cherry picked from commit 76b25df5a31914ae58d47d17af448216011e425c)
baytrail: change power consumption number for ACPI_C3/C6FS.
Reviewed-on: https://chromium-review.googlesource.com/186934
(cherry picked from commit 5192e2464fbb88ea6fc117070240c9733e34f065)
baytrail: Fix use of ConcatenateResTemplate() in ACPI LPE device
Reviewed-on: https://chromium-review.googlesource.com/186928
(cherry picked from commit 8d1ab5de1d43b0790d140f6d0e36a990a5049ece)
baytrail: Disable P-state HW coordination on 4-core SKU
Reviewed-on: https://chromium-review.googlesource.com/187575
(cherry picked from commit c19c0f1d7cb3cb2635766c186ba9598933424a78)
baytrail: DPTF: Enable mainboard-specific _PDL
Reviewed-on: https://chromium-review.googlesource.com/187576
(cherry picked from commit 5412ac5c07bee22017a0ee6d1e2433917b98ea87)
rambi: Apply DPTF tuning parameters
Reviewed-on: https://chromium-review.googlesource.com/187577
(cherry picked from commit 932a5a3803ceaf430ad2934b371ac0886c25efca)
rambi : change lpe_codec_clk_freq to 19.2
Reviewed-on: https://chromium-review.googlesource.com/187594
(cherry picked from commit f64cb1ae77076ad5ec994670f4a83dc561ea80c4)
Squashed 25 commits for baytrail/rambi.
Change-Id: Ibe628ac974d117a09361f7f3131a488911ddd27d
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6933
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
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Change-Id: Ic555d23a9112677a784dd814601f8202d4d17261
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/5691
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins)
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Some 1.5 boards have a single channel ram configuration.
Accomodate such configs.
BUG=chrome-os-partner:22865
BRANCH=None
TEST=Built and booted ChromeOS.
Change-Id: I513327e47b9211d2dd1ea960d7da671a3773cb91
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/178340
Reviewed-by: Nick Sanders <nsanders@chromium.org>
Tested-by: Bernie Thompson <bhthompson@chromium.org>
Tested-by: Nick Sanders <nsanders@chromium.org>
Reviewed-on: http://review.coreboot.org/4983
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
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The ram_id[2:0] signals have stuffing options for pull up/down
with values of 10K. However, the default pulldown values for these
pads are 20K. Therefore, one can't read a high value because of
the high voltage threshold is 0.65 * Vref. Therefore the high
signals are marginal at best.
Fix this issue by disabling the internal pull for the pads connected
to ram_id[2:0].
BUG=chrome-os-partner:23350
BRANCH=None
TEST=Built and checked that ram_id[2:0] is properly read now.
Change-Id: Ib414d5798b472574337d1b71b87a4cf92f40c762
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/173211
Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-by: Bernie Thompson <bhthompson@chromium.org>
Reviewed-on: http://review.coreboot.org/4885
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
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There are currently 4 SKUs:
0b000 - 4GiB total - 2 x 2GiB Micron MT41K256M16HA-125:E 1600MHz
0b001 - 4GiB total - 2 x 2GiB Hynix H5TC4G63AFR-PBA 1600MHz
0b010 - 2GiB total - 2 x 1GiB Micron MT41K128M16JT-125:K 1600MHz
0b011 - 2GiB total - 2 x 1GiB Hynix H5TC2G63FFR-PBA 1600MHz
Add each of the 4 spds to the build, and use the proper
parameters to MRC to use the in-memory SPD information.
BUG=chrome-os-partner:22865
BRANCH=None
TEST=Built. Noted 1024 bytes of SPD content.
Change-Id: Ife96650f9b0032b6bd0d1bdd63b8970e29868365
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/172280
Reviewed-on: http://review.coreboot.org/4872
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
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BUG=chrome-os-partner:23121
BRANCH=None
TEST=None
Change-Id: I283415be326e2d92e1e1bf7866954f17a7266edb
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/171940
Reviewed-by: Bernie Thompson <bhthompson@chromium.org>
Reviewed-on: http://review.coreboot.org/4865
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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