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path: root/src/mainboard/google/rambi/gpio.c
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2014-05-15rambi: Add ACPI devices and interrupts for codec and ALSDuncan Laurie
The Codec and ALS both have interrupt sources that can be configured. The ALS kernel driver currently does not try to use it but the codec driver does for things like jack detect. ACPI Devices are added, but as with other ACPI devices the HID may need to be updated once more official strings are decided. BUG=chrome-os-partner:24380 BRANCH=baytrail TEST=manual: build and boot on rambi and check for functional lightsensor Change-Id: Ib51a2aaf32d5597926fcbe9183947e9ac53e1468 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/182366 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/5049 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-15rambi: disable SERIRQ native functionalityAaron Durbin
Nothing can actually use this as the EC cannot speak using baytrail's SERIRQ protocol. Also, the voltage bridge is going away so nothing will be hooked up to it. Therefore disable this it. BUG=chrome-os-partner:24693 BRANCH=rambi TEST=Built and booted. Change-Id: I406bb9c227578ec0a75eaf67143b3b27cb7880ae Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/182082 Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: http://review.coreboot.org/5042 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-13rambi: Move KBD_IRQ pin for Rambi 2.0 boardShawn Nematbakhsh
KBD_IRQ# is moved to GPIO SC101, with SC50 going back to its original SERIRQ function. Note that this change breaks Rambi 1.5 keyboard functionality. BUG=chrome-os-partner:24424 TEST=Manual on Rambi 2.0. Verify KB functions in OS with SC50 / SERIRQ KB interrupt toggling removed from EC code. BRANCH=Rambi, Glimmer, Clapper Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: I3fa40441741ea9d52a6e2ff15925570510b5b82b Reviewed-on: https://chromium-review.googlesource.com/181757 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/5030 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-12Rambi: Enable 32k SUSCLK signalKyösti Mälkki
The SoC needs to provide a 32k clock signal SUSCLK for some modems to work properly, so this enables the signal. BUG=chrome-os-partner:24425 TEST=Manual, check SUSCLK pin with a scope. Change-Id: Ibc0d5bb38a2c3e16f381dfc256097fdced67fd1c Reviewed-on: https://chromium-review.googlesource.com/180101 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Commit-Queue: Bernie Thompson <bhthompson@chromium.org> Signed-off-by: Bernie Thompson <bhthompson@chromium.org> Tested-by: Bernie Thompson <bhthompson@chromium.org> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5722 Reviewed-by: Aaron Durbin <adurbin@gmail.com> Tested-by: build bot (Jenkins)
2014-05-12rambi: Make eMMC CLK pull-down and change pull strengths to 20KShawn Nematbakhsh
eMMC CLK was incorrectly configured as PULL_UP, but should have been PULL_DOWN. 2K pulls somehow masked this problem. BUG=chrome-os-partner:24353 TEST=Verify eMMC is bootable on Rambi on boards that previously failed with an all-20K, all-PU eMMC pin configuration. BRANCH=None Change-Id: I0cbb6ebbb6818f83402b99330728266b09a0f5d6 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/181034 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/5026 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins)
2014-05-09rambi: change SD card pulls to 20KAaron Durbin
Now that the SD card controller is limited to the SD card 2.0 spec it's possible to use 20K pulls for the pads. BUG=chrome-os-partner:24423 BUG=chrome-os-partner:24312 BRANCH=None TEST=Built and booted. Able to dd to/from /dev/mmcblk1 without any errors. Change-Id: Id5396c55330a84bf7a09d227507d2bfcde66a1a4 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/179423 Reviewed-on: http://review.coreboot.org/4999 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins)
2014-05-08rambi: Make ec_in_rw a legacy GPIOShawn Nematbakhsh
ec_in_rw needs to be read by depthcharge, which only supports legacy GPIOs. BUG=chrome-os-partner:24408 TEST=Manual on Rambi. Cold + warm boot device, verify that depthcharge detects the proper ec_in_ro state. BRANCH=None Change-Id: I25802b445c795eb85580c22d880efee8eeb21318 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/179228 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4993 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins)
2014-05-08rambi: Change eMMC pin PUs to 2KShawn Nematbakhsh
Strengthen PUs on all eMMC pins to fix problems with eMMC not coming up on certain boards. BUG=chrome-os-partner:24353 TEST=Manual. Burn FW on board that previously failed to boot eMMC, verify chromeos can now install + boot from eMMC. BRANCH=none Change-Id: I7a9742968b8b8c2c42285ffc21de46aed9c87fb7 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/178917 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4991 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins)
2014-05-08rambi: configure SD card signalsAaron Durbin
Rambi 1.5 boards use the native SD card controller on baytrail. Therefore, enable those signals. The CLK, D*, and CMD pins use 2K pulls as these were shown to not exhibit any errors when doing reads or writes to a DDR50 sd card. Note that if a servo is connected on needs to enable the sd_vref_sel rail to pp1800 as this causes issues with card detect if it is not set to pp1800. BUG=chrome-os-partner:24312 BRANCH=None TEST=Built and booted. Tested sd card read and write works in kernel. Also noted that write protect detection works as well. Change-Id: I520e2808acbd8494534fcb710411dbc0e12fc874 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/178961 Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: http://review.coreboot.org/4990 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins)
2014-05-07rambi: use SERIRQ pad as keyboard irq in gpio modeAaron Durbin
The level shifting between 3.3V and 1.8V for the SERIRQ signal is not working. Instead use the SERIRQ pad as a gpio which is used as a direct IRQ signal for the keyboard interupt. BUG=chrome-os-partner:23965 BRANCH=None TEST=Built and booted rambi. Keyboard works with associated EC change. CQ-DEPEND=CL:177189 Change-Id: Ifc270ca38207828a6d4711551d4bde9121559cca Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/177223 Tested-by: Bernie Thompson <bhthompson@chromium.org> Reviewed-on: http://review.coreboot.org/4979 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-07rambi: make ramids non-legacy gpio inputsAaron Durbin
The romstage code for rambi uses the mmio way of reading inputs. However, this is a problem is the GPIOs are set up as legacy mode. Subsequent warm resets mean the ram_id is read incorrectly. Ensure the ram_id is read consistently by keeping the GPIOs for ram_id in mmio mode. BUG=chrome-os-partner:24085 BRANCH=None TEST=Built and booted. And rebooted. Now seeing consistent ram_id values on warm resets. Change-Id: Ieff98c000be80998854f325754f1e819975d2be5 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/177230 Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: http://review.coreboot.org/4977 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-07rambi: Add DIRQs for trackpad and touchscreenShawn Nematbakhsh
Also add the relevant info about these pins to the ASL tables + add SMBIOS type 41 data for these parts. BUG=chrome-os-partner:22863 TEST=Manual on Rambi. Set some pins to GPIO_DIRQ, and then verify DIRQ regwrites w/ GPIO_DEBUG look correct. Change-Id: Id40655f9fb2ea7b10e1ff58d0b2a8b4cc6f05ff8 Reviewed-on: https://chromium-review.googlesource.com/176299 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Commit-Queue: Shawn Nematbakhsh <shawnn@chromium.org> Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Tested-by: Shawn Nematbakhsh <shawnn@chromium.org> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4963 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-06rambi: enable SCI and SMI gpiosAaron Durbin
Rambi has 3 pins that need to be configured for SCI and SMI: 1. GPIO_CORE[0] - runtime SCI pin 2. GPIO_SUS[7] - SMI for firmware lid events 3. GPIO_SUS[0] - wake pin for S3 wakes from EC. Configure these pins now that the rest of the infrastructure is in place. The one thing that is yet to work is runtime SCI for lid events once booted. BUG=chrome-os-partner:23505 BRANCH=None TEST=built and booted. lid close at rec screen works. And wake from S3 with a keyboard press works. Change-Id: I5f8e38ec5f4cf1a8ef7aa7fcee9abc344d9b184f Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/176393 Reviewed-on: http://review.coreboot.org/4960 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-06rambi: mirror bayleybay's eMMC gpio setupAaron Durbin
These changes to the eMMC pads allows the kernel to see the eMMC device. One is able to install onto the eMMC device, and the kernel is loaded and booted from eMMC device. Note, that it may not fully boot because of other issues such as not-completely working ACPI support. BUG=chrome-os-partner:22580 BRANCH=None TEST=booted off of usb drive. can see eMMC device. Change-Id: I9c088398297a0b559383bdf4a389dd19a1110e0f Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/176073 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/4945 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-06rambi: Fix eDP panel functionalityDuncan Laurie
For some mysterious reason GPIO_S0_NC22 is making the eDP panel go entirely white when it is configured with internal pullup. Since these (supposedly XDP related) pins are unknown functionality lets set them to GPIO_DEFAULT instead of GPIO_NC. Additionally the VBIOS is being changed to issue int15 callback to determine the boot graphics device. If we list both LFP and EFP then the dev/rec screens will show on the panel when HDMI is not attached and otherwise will display on HDMI. BUG=chrome-os-partner:23507 BRANCH=rambi TEST=build and boot on rambi, see firmware/kernel screens on the panel when HDMI is not attached, and firmware screens on the panel and kernel screens on both when HDMI is attached. Change-Id: Ieb05a591d63c4f8e09fa154eeb76004d32579508 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/175952 Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4944 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-02-11rambi: Add platform GPIO configuration tablesShawn Nematbakhsh
Configure GPIOs according to function on board. TEST=compile only. BUG=chrome-os-partner:22863 Change-Id: Ic38eeb64149606f2d7a19cc7a0144cc7e24807b8 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/172657 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4875 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-02-11rambi: Add ncore GPIO config tablesShawn Nematbakhsh
gpncore config tables were previously missing -- add them. Also, make the baytrail GPIO/PAD LUTs easier to read. TEST=Manual. Build + boot on bayleybay. BUG=chrome-os-partner:22865 Change-Id: I49a1b23c7ad4fb5f4c86618e8c78ea9a1a42f79d Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/172510 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4874 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-02-05mainboard/google: add initial rambi mainboard supportAaron Durbin
BUG=chrome-os-partner:23121 BRANCH=None TEST=None Change-Id: I283415be326e2d92e1e1bf7866954f17a7266edb Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/171940 Reviewed-by: Bernie Thompson <bhthompson@chromium.org> Reviewed-on: http://review.coreboot.org/4865 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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