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2017-04-19mainboard/google/poppy: Provide nhlt variant APIFurquan Shaikh
Move current NHLT configuration implementation to baseboard so that variants can leverage it or provide their own configuration. BUG=b:37375693 Change-Id: I2a4317c112f9e3614bd01eb6809727b73328d29d Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19326 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-04-19mainboard/google/poppy: Provide memory configuration variant APIFurquan Shaikh
Add support for memory configuration by providing weak implementation from the baseboard. All SPD files are present under spd/ directory. SPD_SOURCES must be provided by the variants to ensure that required SPD hex files are included in the SPD binary. BUG=b:37375693 Change-Id: Ic9bcc03d5a35bebd14061680f264ac072b3c0634 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19325 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-04-19mainboard/google/poppy: Provide cros_gpio variant APIFurquan Shaikh
Add support for ChromeOS GPIO ACPI table information by providing weak implementation from the baseboard. BUG=b:37375693 Change-Id: I641afe6bb45f106ddebde081a8ac2c64278ebeb9 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19324 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-04-19mainboard/google/poppy: Add variant API for board_id and gpioFurquan Shaikh
Provide APIs for board_id() and gpio table functionality. Default weak implementations are provided from the baseboard. BUG=b:37375693 Change-Id: Ic3c946e6cb12b3c8ef3e83a1037ed0fc8cffbded Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19323 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-04-19mainboard/google/poppy: Provide baseboard and variant conceptsFurquan Shaikh
In order to be able to share code across different poppy variants, provide the concept of baseboard and variants. New directory layout: variants/baseboard - code variants/baseboard/include/baseboard - headers variants/poppy - code variants/poppy/include/variant - headers New boards would then add themselves under their board name within "variants" directory. This is purely an organizational change. BUG=b:37375693 Change-Id: If6c1c5f479cfffe768abf27495d379744104e2dc Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19322 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-04-19mainboard/google/poppy: Prepare sharing directory for variantsFurquan Shaikh
Clean up Kconfig file in order to support variants for poppy. Add BOARD_GOOGLE_BASEBOARD_POPPY that can be set by various poppy variants to use the common baseboard configs. BUG=b:37375693 Change-Id: I399ecc8c3efb3af26e1fcf60fe2c75b24769fc0f Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19321 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-04-19mb/google/poppy: Add camera supportV Sowmya
Add camera related support * Enable the SA Imaging Unit and CIO2 devices. * Enable TPS68470 PMIC and populate related ACPI objects. * Enable OV cameras and populate related ACPI objects. * Enable Dongwoon AF DAC and populate related ACPI objects. BUG=b:36580624 BRANCH=none TEST=Build and boot poppy. Dump and verify that ACPI tables have the required entries for all the camera devices. Change-Id: Ifbe878bb6b25fc976e935fee16c4d59fadd47fe2 Signed-off-by: Sowmya V <v.sowmya@intel.com> Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/18969 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2017-04-19mb/google/poppy: Add Image Processing Unit ASLSowmya
This patch includes ipu.asl file in the main DSDT definition to add ACPI entries for IMGU and CIO2 devices. BUG=b:36580624 BRANCH=none TEST=Build and boot poppy. Dump and verify that DSDT table has the entries for IMGU and CIO2 devices. Change-Id: Ib7485315cb9468da7c6aa090862657a265121493 Signed-off-by: Sowmya V <v.sowmya@intel.com> Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/19110 Tested-by: build bot (Jenkins) Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-04-18mainboard/google/poppy: Clean up gpio.h fileFurquan Shaikh
1. Update formatting of gpio table to fit everything within 80 column limit. 2. PEN_RESET gpio is non-existent. Get rid of it. BUG=b:37375693 Change-Id: I1bcc4168659f365547e5f7227df8659e4bc7f243 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19320 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-04-18mainboard/google/poppy: Enable deep S3 in DC modeFurquan Shaikh
Enable lower power state when running on battery. Deep S3 is not enabled when in AC mode to support standard "docked" config. BUG=b:36087058,b:36723679 TEST=Verified following behavior with USB mouse: 1. If AC is connected when entering S3, USB mouse is able to wake up. 2. If AC is not connected when entering S3, USB mouse does not wake up. 3. If AC is connected when entering S3 and removed after entering S3, USB mouse does not wake up. 4. If AC is not connected when entering S3 and attached after entering S3, USB mouse does not wake up. Change-Id: I141a8d4779de004e27fcd9357cef787a38a27b24 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19276 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-04-13soc/intel/skylake: Split AC/DC settings for Deep Sx configDuncan Laurie
Currently when enabling Deep S3 or Deep S5 it unconditionally gets enabled in both DC and AC states. However since using Deep S3 disables some expected features like wake-on-USB it is not always desired to enable the same state in both modes. To address this split the setting and add a separate config for Deep Sx in AC and DC states. All motherboards that set this config were updated, but there is no actual change in behavior in this commit. BUG=b:36723679 BRANCH=none TEST=This commit has no runtime visible changes, I verified on Eve that the Deep SX config registers are unchanged, and it compiles for all affected boards. Change-Id: I590f145847785b5a7687f235304e988888fcea8a Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/19239 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-04-13mainboard/google/poppy: Enable internal pull-down on USB_C{0,1}_DP_HPDFurquan Shaikh
These lines act as inputs to both EC and AP. Thus, add internal pull-downs to prevent them from floating. BUG=b:35648530 Change-Id: I42326c810775d5449e99e52e81870970247ce335 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19243 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-04-13mainboard/google/poppy: Add support for cr50 SPI TPMFurquan Shaikh
Put all configs required for enabling cr50 SPI TPM on poppy under POPPY_USE_SPI_TPM so that it can be enabled any time for testing SPI TPM on this board. Also, add required callback for irq status and devicetree config for GSPI0. BUG=b:36873582 Change-Id: I67793093c006c1325fc16f669a96126525f83243 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19238 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-04-05mainboard/google/poppy: Change SD card detect to GPP_E15Furquan Shaikh
SD card detect pin is moved to GPP_E15 in the next build. Update device tree and gpio config accordingly. BUG=b:36012095 Change-Id: Ic0ff72cdcb0f1ca27abc7eb8da9ccd8a21b28522 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/19107 Tested-by: build bot (Jenkins) Reviewed-by: Naresh Solanki <naresh.solanki@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Pratikkumar Prajapati <pratikkumar.v.prajapati@intel.corp-partner.google.com>
2017-03-28vboot: Move remaining features out of vendorcode/google/chromeosJulius Werner
This patch attempts to finish the separation between CONFIG_VBOOT and CONFIG_CHROMEOS by moving the remaining options and code (including image generation code for things like FWID and GBB flags, which are intrinsic to vboot itself) from src/vendorcode/google/chromeos to src/vboot. Also taking this opportunity to namespace all VBOOT Kconfig options, and clean up menuconfig visibility for them (i.e. some options were visible even though they were tied to the hardware while others were invisible even though it might make sense to change them). CQ-DEPEND=CL:459088 Change-Id: I3e2e31150ebf5a96b6fe507ebeb53a41ecf88122 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/18984 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-28vboot: Assume EC_SOFTWARE_SYNC and VIRTUAL_DEV_SWITCH by defaultJulius Werner
The virtualized developer switch was invented five years ago and has been used on every vboot system ever since. We shouldn't need to specify it again and again for every new board. This patch flips the Kconfig logic around and replaces CONFIG_VIRTUAL_DEV_SWITCH with CONFIG_PHYSICAL_DEV_SWITCH, so that only a few ancient boards need to set it and it fits better with CONFIG_PHYSICAL_REC_SWITCH. (Also set the latter for Lumpy which seems to have been omitted incorrectly, and hide it from menuconfig since it's a hardware parameter that shouldn't be configurable.) Since almost all our developer switches are virtual, it doesn't make sense for every board to pass a non-existent or non-functional developer mode switch in the coreboot tables, so let's get rid of that. It's also dangerously confusing for many boards to define a get_developer_mode() function that reads an actual pin (often from a debug header) which will not be honored by coreboot because CONFIG_PHYSICAL_DEV_SWITCH isn't set. Therefore, this patch removes all those non-functional instances of that function. In the future, either the board has a physical dev switch and must define it, or it doesn't and must not. In a similar sense (and since I'm touching so many board configs anyway), it's annoying that we have to keep selecting EC_SOFTWARE_SYNC. Instead, it should just be assumed by default whenever a Chrome EC is present in the system. This way, it can also still be overridden by menuconfig. CQ-DEPEND=CL:459701 Change-Id: If9cbaa7df530580a97f00ef238e3d9a8a86a4a7f Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/18980 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-21mainboard/google/poppy: Use sideband IRQ for SD Card DetectFurquan Shaikh
Since SD card controller is expected to enter D3hot by runtime power management if there is no card inserted, we need to use a sideband IRQ pin which is not under the control of the controller. Thus, configure GPP_A7 as the sideband IRQ pin and pass it to OS as the card detect pin. BUG=b:35586693 BRANCH=None TEST=Verified on a reworked poppy board that card detect works fine. Change-Id: I4512f5d7829583e27c9750463396eaffbc5702b4 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/18926 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-03-17mainboard/google/poppy: Enable EC SW syncFurquan Shaikh
Now that EC on poppy is stable, it is time to switch on EC SW sync. BUG=b:36178824 BRANCH=None TEST=Verified that EC SW sync is done properly and device boots to OS. Change-Id: I1395ad8af73128a8dd220351f5b5da157659b19e Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/18838 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-16google/poppy: Use rt5663 interrupt as GpioInt instead of PIRQRizwan Qureshi
The kernel driver for rt5663 expects to get an interrupt on both a rising and falling edge, and using a legacy interrupt doesn't provide that flexibility. Instead configure this pin as a GPIO and use the interrupt through the GPIO controller. This allows using GpioInt() with ActiveBoth setting and results in correct operation of the headset jack. This is a clone of Duncan's patch for eve at I6f181ec560fe9d34efc023ef6e78e33cb0b4c529 BUG=none BRANCH=none TEST=test on poppy that headset jack detect is read properly at boot, and that plugging in and removing both generate a single interrupt event in the driver. Change-Id: I4aaa4164cb277a98ab5d5f033632f5e16bfb779e Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/18853 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-15intel/skylake: Fix bug in VR configuration with FSP 2.0Duncan Laurie
With the move to FSP 2.0 the number of VR types supported was reduced to 4, and the VR_RING type is no longer present. This means all existing boards using FSP 2.0 are incorrectly passing VR configuration into FSP as the values corresponding to "GT Sliced" and "GT Unsliced" have changed. Fix this by updating the skylake SOC VR handling to account for changes in the FSP configuration and no longer provide VR_RING type when using FSP 2.0. BUG=b:36228330 BRANCH=none TEST=manual: build and boot on Eve Change-Id: I59eea9fba006a4c235d7b42d07fdc6e4f44f7351 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/18818 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins)
2017-03-12google/poppy: Enable internal pull-up on PWRBTN#Shobhit Srivastava
Enable an internal pull-up on the power button input as short press is resulting in power button override being asserted. BUG=b:36111214 BRANCH=none TEST=tested on poppy board to ensure quick power button press does not result in a shutdown due to power button override. Change-Id: I3a25b78562e2302b6f7575e64c87ae8142690701 Signed-off-by: Shobhit Srivastava <shobhit.srivastava@intel.com> Reviewed-on: https://review.coreboot.org/18734 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-03-09google/poppy: Configure SRCCLKREQ4 as No ConnectNaresh G Solanki
SRCCLKREQ4 is unused, so configure SRCCLKREQ4 as NC (No Connect). Change-Id: I6e265b9c9faa0df20208bb82278cadbbbbe6c537 Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/18589 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-03-09mainboard/google/poppy: Enable cros_ec_keyb deviceFurquan Shaikh
This is required to transmit button information from EC to kernel. BUG=b:35774934 BRANCH=None TEST=Verified using evtest that kernel is able to get button press/release information from EC. Change-Id: I8f380f935c2945de9d8e72eafc877562987d02db Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/18642 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2017-03-08mainboard/google/poppy: Add EC_HOST_EVENT_MODE_CHANGE to wakeup sourceFurquan Shaikh
Allow EC mode change event to wake AP up in S3. BUG=b:35775085 BRANCH=None TEST=Compiles successfully for poppy. Change-Id: I6f1546c60aef6620e22cdce2fab3a2709e6556a1 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/18608 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-03-07google/poppy: fix finger print sensor interrupt gpio configurationRizwan Qureshi
Configure the right GPIOs for finger print sensor interrupt and reset lines. As per the schematics GPP_C8 is for sensor interrupt and GPP_C9 is for sensor reset. Change-Id: Ib25c68ec2fe20b1302b6170d67ceab7e8cca1a83 Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/18389 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-03-02mainboard/google/poppy: Disable deep S3 on poppyFurquan Shaikh
BUG=chrome-os-partner:62963 BRANCH=None TEST=Compiles successfully Change-Id: Icb929262fd67362b8e5c5cf31dce04ab1f496695 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/18467 Tested-by: build bot (Jenkins) Reviewed-by: Rajat Jain <rajatja@google.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2017-02-24mainboard/google/poppy: Change touchscreen IRQ to level-triggeredFurquan Shaikh
BUG=chrome-os-partner:62967 BRANCH=None TEST=Verified that touchscreen works on power-on and after suspend-resume as well. Change-Id: Id674cbcc2d524a6ed2883bf9f0e9e076890f9a85 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/18466 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-02-23mb/google/poppy: Enable support for DPTFSumeet Pawnikar
This patch adds the DPTF settings specfic to the mainboard and enables the CPU and other thermal sensors as participant device for poppy. It enables the DPTF flag in the device tree for poppy. It also includes the DPTF specific ASL file in the main DSDT definition. BUG=None BRANCH=None TEST=Built for poppy. Change-Id: If44b01dd3c17fea06681ccf50e8e9f406e642e36 Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/17926 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2017-02-22acpi: Add ACPI_ prefix to IRQ enum and struct namesFurquan Shaikh
This is done to avoid any conflicts with same IRQ enums defined by other drivers. BUG=None BRANCH=None TEST=Compiles successfully Change-Id: I539831d853286ca45f6c36c3812a6fa9602df24c Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/18444 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-02-21mainboard/google/poppy: Enable Realtek 5663 supportRizwan Qureshi
Enable Realtek RT5663 codec i2c device and add required SSDT parameters. BUG=chrome-os-partner:62051 BRANCH=None TEST=With required driver support in kernel verify audio on headset Change-Id: I9b9eb1e7edca56870f5be0e4fd603c9b0dc7f9de Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/18216 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Martin Roth <martinroth@google.com>
2017-02-21mainboard/google/poppy: Enable Maxim MAX98927 codecRizwan Qureshi
Enable Maxim 98927 codec i2c device and add required SSDT parameters. BUG=chrome-os-partner:62051 BRANCH=None TEST=with required driver support in kernel verify audio on poppy on-board speakers. Change-Id: Id731de42d77204d59f32ac4c33a245837d6e2107 Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Signed-off-by: Dylan Reid <dgreid@chromium.org> Reviewed-on: https://review.coreboot.org/18215 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Martin Roth <martinroth@google.com>
2017-02-21mainboard/google/poppy: Generate required nhlt tableRizwan Qureshi
poppy board uses Maxim 98927 speaker codec and Realtek RT5663 for headset. Select the apropriate NHLT blobs to be packaged in CBFS. Also, generate the required ACPI NHLT table for codec and the supported topology in poppy. BUG=chrome-os-partner:62051 BRANCH=None TEST=With the required driver support in kernel verify that the Audio plays on on-board speakers and headset, recording works from on-board mics and headset mics. Change-Id: I98c65038b35fe99a661807de0766e6eac2c80eed Signed-off-by: M Naveen <naveen.m@intel.com> Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/18214 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2017-02-20drivers/i2c: Use I2C HID driver for wacom devicesFurquan Shaikh
Wacom I2C driver does the same thing as I2C HID driver, other than defining macros for Wacom HID. Instead of maintaining two separate drivers providing the same functionality, update all wacom devices to use generic I2C HID driver. BUG=None BRANCH=None TEST=Verified that ACPI nodes for wacom devices are unchanged. Change-Id: Ibb3226d1f3934f5c3c5d98b939756775d11b792c Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/18401 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2017-02-20mainboard/{google,intel}: Change config option selectionFurquan Shaikh
Change config option selection from "config xyz default y" to "select xyz" if the config option has no dependencies. BUG=None BRANCH=None TEST=Verified that config option selection remains unchanged. Change-Id: I259ae40623b7f4d5589e2caa0988419ba4fefda4 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/18400 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2017-02-17mainboard/poppy: select SOC_INTEL_KABYLAKERizwan Qureshi
poppy is based on Kabylake SoC hence select the appropriate config. Change-Id: Ie339a3991eeccb8a7dba983a2b5ab5d1c996ce9d Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/18313 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-02-17mainboard/google/poppy: Generate digitizer node in SSDTFurquan Shaikh
Add support for generating digitizer node in SSDT using wacom i2c driver. BUG=None BRANCH=None TEST=Verified that the node shows up in SSDT. Change-Id: If7e1e2463778c2ff7263eff995def149457edcde Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/18373 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-02-14google/poppy: select NO_FADT_8042Jenny TC
Poppy doesn't support 8042 keyboard. Select NO_FADT_8042 to disable 8042 in FADT header. Kernel will not try to access 8042 region if 8042.FADT=0 BUG=chrome-os-partner:61858 TEST=Boot OS and verify FADT 8042 flag Change-Id: I00182eb4b059d4d9f0705d349dc98651e3955f0d Signed-off-by: Jenny TC <jenny.tc@intel.com> Reviewed-on: https://review.coreboot.org/18311 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-02-04google/poppy: Set GPIO GPP_D22 highRizwan Qureshi
same change as I49935e659bf67225d3f5db1b06acc2cd046dcd74 this is required for poppy board as well. GPIO GPP_D22 controls the I2S buffer for isolating the I2S signals when doing GPIO-driven I2S. This needs to be high by default so the DSP can drive these signals, instead of low where it is enabled for GPIO-driven I2S and the DSP cannot drive these signals. BUG=None BRANCH=None TEST=play test sound in OS over internal speaker Change-Id: I1695e9198f8f78e9c5ad6df6c1ac073ac1762c6b Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/18282 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-01-16mainboard/google/poppy: SD card changesFurquan Shaikh
1. Disable WP 2. Pass SD card detect info in ACPI BUG=chrome-os-partner:60713 BRANCH=None TEST=Verified that OS is able to detect SD card and read/write to it. Change-Id: Ide84d4b86c0fac50a07520dfd76d6d3a921f2ecc Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/18138 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-01-16mainboard/google/poppy: Update DQS and DQ Byte mappings for poppyRizwan Qureshi
poppy schematics have undergone change after review, update DQS and DQ Byte mappings based on the new schematics. BUG=chrome-os-partner:61856 BRANCH=None TEST= Build and boot all the poppy proto SKUs to OS. Change-Id: Ie4532035f37c25540abb26122234f6e3346ede69 Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/18133 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-01-13mainboard/google/poppy: Disable EC SW syncFurquan Shaikh
BUG=chrome-os-partner:60513 BRANCH=None TEST=Verified that EC SW sync is disabled Change-Id: I399b26aa64084f5d5e91a2e585281dc48fa81c89 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/18114 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-01-13mainboard/google/poppy: Enable touchscreen in ACPIFurquan Shaikh
BUG=chrome-os-partner:60513 BRANCH=None TEST=Verified that touchscreen works on poppy. Change-Id: I0fd605048b91b126ca5b5f8c1c4d6d3f46f866a3 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/18113 Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: Martin Roth <martinroth@google.com>
2017-01-13mainboard/google/poppy: Correct the index for SPD binariesFurquan Shaikh
BUG=chrome-os-partner:60513 BRANCH=None TEST=Picks up correct SPD for index. Change-Id: Iac683ab3b8151747940b0ad7e257da3d9b0ac622 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/18112 Tested-by: build bot (Jenkins) Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-01-13mainboard/google/poppy: Enable SD cardFurquan Shaikh
BUG=chrome-os-partner:60713 BRANCH=None TEST=sdcard is detected. Change-Id: I9ec0cabff0ed7973f5e7dd2c1eae346ae6a1aa99 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/18111 Tested-by: build bot (Jenkins) Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-19google/poppy: Add new boardFurquan Shaikh
Add poppy board files using kabylake and FSP 2.0. BUG=chrome-os-partner:60713 BRANCH=None TEST=Compiles successfully Change-Id: Ic9aa5093b319690ae893a21cab98d9b843000e6c Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17866 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-09 22:02:00 +0000