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2019-12-31mb/**/dsdt.asl: Remove outdated sleepstates.asl commentAngel Pons
Previously, each Intel chipset had its own sleepstates.asl file. However, this is no longer the case, so drop these comments. Change-Id: I50aba6e74f41e2fa498375b5eb6b7e993d06bcac Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37855 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2019-12-21mb/**/dsdt.asl: Remove "Some generic macros" commentAngel Pons
It provides no useful information, so it might as well vanish. Change-Id: I0df6f4639a16058486c2e2d40fe4067d65670731 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37856 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2019-12-20src/mainboard: Remove unused '#include <device/pci.h>'Elyes HAOUAS
Change-Id: I5791fddec8b2387df5979adbb1a0fa64c5dd23ea Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37522 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2019-12-12mb/google/nocturne: adjust VBT boot resolutionMatt DeVillier
On nocturne, the VBT specifies that the native panel resolution (3000x2000) is to be used by FSP/GOP init, which makes payload and grub menus extremely difficult to read. Change the default POST resolution specified by the VBT to 1500x1000 instead (200% scaling) which is much more legible. Test: build/boot nocturne with GOP init and Tianocore payload, observe menu text is actually readable. Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Change-Id: I767a2b8319c7673e3460acfad534140409bf1d57 Reviewed-on: https://review.coreboot.org/c/coreboot/+/37621 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-09mb/google/poppy: set detachable system type for nocturne/sorakaMatt DeVillier
Set the SMBIOS system type to detachable for nocturne and soraka variants, to allow the OS to correctly process events. Change-Id: Ie0ee5ea6666542c0bca2c264b2ed2e6135b78658 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37540 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-12-02mb/google/poppy: Remove useless ifs around voltage and GPIO direction ↵Sakari Ailus
configuration The methods generally tested OP region settings and only changed them if they were not in their desired values. Instead, assign them directly without checking them. BUG=chromium:959232 Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Tested-by: Jacopo Mondi <jacopo@jmondi.org> Change-Id: I3ceca4bd51c4410c7020431f4fd682c4ca925110 Reviewed-on: https://review.coreboot.org/c/coreboot/+/36746 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-02mb/google/poppy: Remove redundant mutexSakari Ailus
The mutex is only used in one method and that method is serialised. Remove the mutex. BUG=chromium:959232 Reported-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Tested-by: Jacopo Mondi <jacopo@jmondi.org> Change-Id: Ic173d557f4b49cc9e860d13b782fc4940fd80869 Reviewed-on: https://review.coreboot.org/c/coreboot/+/36745 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-02mb/google/poppy: Rework OV13858 power on sequenceSakari Ailus
In particular: - Set voltage before enabling regulators - Enable regulators and the clock without any sleeping in between. There's no need to wait there. - Sleep 1 ms in order to wait for regulator voltages settling before lifting xshutdown. BUG=chromium:959232 Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Tested-by: Jacopo Mondi <jacopo@jmondi.org> Change-Id: I0f8857ae369d5038f293a0e2c48c681df535ad86 Reviewed-on: https://review.coreboot.org/c/coreboot/+/36744 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-12-02mb/google/poppy: Rework OV5670 power on sequenceSakari Ailus
In particular: - Enable regulators *after* configuring the voltage - Allow 1 ms for the voltages to settle - Enable clock after powering on regulators - Remove extra delays between enabling things. The sensor requires 8192 clock cycles after the reset is lifted before I²C access, so 1 ms is enough. - Make the delay after lifting xshutdown 10 ms. This guarantees that streaming will only start once the sensor has had enough time to settle after lifting the reset. BUG=chromium:959232 Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Tested-by: Jacopo Mondi <jacopo@jmondi.org> Change-Id: I4589a7d7ec324f4520572a406cc11ad3feec8b21 Reviewed-on: https://review.coreboot.org/c/coreboot/+/36723 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-12-02mb/google/poppy: Power on PMIC before accessing its opregionSakari Ailus
The PMIC opregion is used to change the direction of two GPIOs for I²C daisy chain operation. Do this after the PMIC is powered on, not before. BUG=chromium:959232 Reported-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Tested-by: Jacopo Mondi <jacopo@jmondi.org> Change-Id: I923987ef21a971df9e32ca03f2da4dccdac07843 Reviewed-on: https://review.coreboot.org/c/coreboot/+/36722 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-12-02mb/google/poppy: Declare output GPIOs as pull-downsSakari Ailus
The pull direction is used to determine the initial state of the pin. If no pull direction is specified, the pin will remain as input. Fix this. BUG=chromium:959232 Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Tested-by: Jacopo Mondi <jacopo@jmondi.org> Change-Id: I1158bc8aaa447b223e8ce25d808348e758de28c5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/36721 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-12-02mb/google/rammus: add libgfxinit supportMatt DeVillier
Add libgfxinit support for rammus. Use panel init values from VBT. Test: build/boot rammus with libgfxinit and Tianocore payload Change-Id: I4775a36d83bd67a0064a162effaf96649e9c186d Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37312 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-12-02mb/google/poppy: add VBTs for remaining variantsMatt DeVillier
Add VBT files for Atlas, Nocturne, Rammus, and Soraka variants. Extracted from ChromeOS recovery images for the respective boards. Select INTEL_GMA_HAVE_VBT for all variants except Poppy, since it doesn't have a VBT (or a recovery image from which to extract one). Change-Id: Icba2741e0b7309c22c027f956cd20cec78f34052 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37311 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-11-01soc/intel/{IA-CPU/SOC}: Move sleepstates.asl into southbridge/intel/common/acpiSubrata Banik
This patch creates a common instance of sleepstates.asl inside intel common code (southbridge/intel/common/acpi) and asks all IA CPU/SOC code to refer sleepstates.asl from common code block. TEST=Able to build and boot Hatch and ICL DE system. Dump DSDT.asl to verify S0/S3/S4/S5 entries after booting to OS. Change-Id: Ie2132189f91211df74f8b5546da63ded4fdf687a Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36463 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-27mb/google/poppy/variant/nocturne: don't invert GPP_D17Nick Vaccaro
This change removes an inversion of GPP_D17 that caused the device to get stuck in a reboot loop because the kernel was crashing within the first couple seconds of kernel boot. BUG=b:142515200 BRANCH=none TEST=Flash and boot nocturne, verify boot is stable and that device doesn't reboot after jumping into kernel, and that it passes the 'tast -verbose run <ip> hardware.SensorRing' test. Change-Id: Ia1408ef6ea92f6b31a9f3eee8720954af3a7c382 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35967 Reviewed-by: Yicheng Li <yichengli@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-25mb/google/{poppy,eve,fizz}: Configure GPIOs in mainboard chip->init()Furquan Shaikh
mainboard_silicon_init_params() is supposed to be used for only overriding any FSP params as per mainboard configuration. GPIOs should be configured by mainboard as part of its chip init(). This ensures proper ordering w.r.t. any common operations that the SoC code might want to perform e.g. snapshot ITSS polarities. This change moves the configuration of GPIOs from mainboard_silicon_init_params() to mainboard chip->init(). Change-Id: Ied0201b954894acd3503801e7739b91a2cc9b4a8 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36268 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-10-21google/poppy: add VBT for nautilus variantMatt DeVillier
Add data.vbt and modify Kconfig appropriately; allows use of FSP/GOP display init. VBT extracted from stock ChromeOS firmware. Change-Id: I8a2d093ad96f72fb420b94aafa790e3ba900d905 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36106 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-10-09mb/[google/intel/lenovo]/*: fix posix shell bug with SPD filesGreg V
FreeBSD's sh (basic posix shell) did not interpret the '\%o' escape in the same way bash/zsh do. As a result, the decoded files ended up with ASCII numbers instead of the decoded binary data. Change-Id: I95b414d959e5cd4479fcf100adcf390562032c68 Signed-off-by: Greg V <greg@unrelenting.technology> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35867 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-10-03mb/[google/intel]/*: Specify Chrome EC bus - LPC or ESPIMartin Roth
Previously all boards using eSPI for the Chrome EC just called it LPC as the code for the chrome EC is the same between the two busses. I'm adding a new Kconfig symbol to specify eSPI, so switch the boards that actually use eSPI to that symbol and add the LPC symbol to all the others. The EC_GOOGLE_CHROMEEC_LPC symbol will no longer default to enabled for x86 platforms, so one symbol or the other needs to be specified for each platform. BUG=b:140055300 TEST=Build tested only. Change-Id: Icf242ca2b7d8b1470feda4e44b47a2cdc20680f2 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35153 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-10-02soc/intel: Replace config_of_path() with config_of_soc()Kyösti Mälkki
The previously provided device path made no difference, all integrated PCI devices point back to the same chip_info structure. Change reduces the exposure of various SA_DEVFN_xx and PCH_DEVFN_xx from (ugly) soc/pci_devs.h. Change-Id: Ibf13645fdd3ef7fd3d5c8217bb24d7ede045c790 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35656 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-09-30mb: remove test-only HWIDsHung-Te Lin
The CONFIG_GBB_HWID can be generated automatically now so we can remove the test-only HWIDs set in board config files. BUG=b:140067412 TEST=Built few boards (kukui, cheza, octopus) and checked HWID: futility gbb -g coreboot.rom Change-Id: I4070f09d29c5601dff1587fed8c60714eb2558b7 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35635 Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-10mb/google/poppy/variant/nocturne: add EC_SYNC_GPIONick Vaccaro
Setup EC_PCH_ARCORE_INT_L, tied to GPP_D17, and define as EC_SYNC_GPIO.. - change GPP_D17 definition to PAD_CFG_GPI_APIC_INVERT as EC_PCH_ARCORE_INT_L is active low - add EC_SYNC_GPIO to the group of chromeos_gpios for use by depthcharge BUG=b:139384979 BRANCH=none TEST="emerge_nocturne coreboot depthcharge chromeos-bootimage", flash & boot nocturne in dev mode, verify that volume up and down buttons work in the dev screen and that the device boots properly into the kernel. Change-Id: Ia43c622710fde8686c60b836fb8318931d79eb61 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35174 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-08-28mb/google/poppy/variant/nami: add sku ids of bard/ekkoRen Kuo
add sku ids of bard/ekko BUG=b:139886622 TEST=emerge-nami coreboot Change-Id: Iabc3d587c3839e4a3121cea8504c50e2dc4f9699 Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35115 Reviewed-by: Vincent Wang <vwang@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: YH Lin <yueherngl@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-15mainboard/google: Fix indirect includesKyösti Mälkki
Change-Id: Ie79702efab519b16cff45ccad61b95e7d8c2fbac Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34854 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-02soc/intel/skylake: Make use of common thermal code for SKLSubrata Banik
This patch ensures skylake soc is using common thermal code from intel common block. TEST=Build and boot soraka Change-Id: I0812daa3536051918ccac973fde8d7f4f949609d Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34648 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-25mb/google/poppy/variant/nami: add sku ids of bardRen Kuo
add two sku ids of bard: 0x1009CE0 0x1009CE2 BUG=b:137892804 TEST=emerge-nami coreboot Change-Id: I299ccb36739d83e38f37e0b2cbba44c34343c975 Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34430 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-07-25mb/*/chromeos.c: Remove some ENV_RAMSTAGE and __SIMPLE_DEVICE__Kyösti Mälkki
Use explicit simple PCI config accessors here. Change-Id: Ifa3814fdd7795479ca5fdbfc4deb3fe8db9805f3 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34519 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-07-21soc/intel: Expand SA_DEV_ROOT for ramstageKyösti Mälkki
We do not want to disguise somewhat complex function calls as simple macros. Change-Id: I298f7f9a1c6a64cfba454e919eeaedc7bb2d4801 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34411 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-07-19google/nocturne: Add MKBP events as a wake sourceAseda Aboagye
We would like to wake nocturne up in suspend from an MKBP event. On Nocturne, MKBP events are notified to the host via a GPIO from the EC, EC_INT_L. However, the AP cannot wake from suspend from this GPIO. Therefore, we'll use the host event interface to wake the system instead. This commit simply enables MKBP events to wake the system in suspend. BUG=chromium:786721 BRANCH=firmware-nocturne-10984.B TEST=Build and flash nocturne, generate MKBP events on the EC and verify that the system wakes up in suspend. Change-Id: I6aff4d38051c939257533229fd0085e42c01d02f Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34388 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2019-07-18soc/intel: Use config_of_path(SA_DEVFN_ROOT)Kyösti Mälkki
We do not want to disguise somewhat complex function calls as simple macros. Change-Id: I53324603c9ece1334c6e09d51338084166f7a585 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34299 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: David Guckian Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-09arch/x86: Avoid HAVE_SMI_HANDLER conditional with smm-classKyösti Mälkki
Build of the entire smm-class is skipped if we have HAVE_SMI_HANDLER=n. Change-Id: I10b4300ddd18b1673c404b45fd9642488ab3186c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34125 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Lance Zhao <lance.zhao@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-25atlas: enable GEO_SARCaveh Jalali
BUG=b:131634035 BRANCH=none TEST=verified SAR data shows up in ACPI SSDT table. Change-Id: I65ef59c9616b1cae3fa4c4b18bbfe4ed098d2891 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33791 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-06-21soc/intel/skylake: Clean up KconfigArthur Heymans
This does the following: - select MAINBOARD_USES_FSP2_0 on Kabylake (does not support FSP1.1) - Remove stale Kconfig option on intel/saddlebrook - select SOC_INTEL_KABYLAKE on intel/kblrvp Change-Id: I64f48eeb00150aea039d533b0ac471fdd8483b90 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33561 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-06-17mb/google/poppy/variants/atlas: Update DPTF parameterPuthikorn Voravootivat
The temperature delta between on-board thermistor and surface temp change, so update DPTF parameter accordingly. BUG=b:113101335 TEST=Tested in thermal chamber by thermal team. See comment 148 / 153 in the bug. Change-Id: Ie18be94fc1e7476755fb0e6947cce559854a82dd Signed-off-by: Puthikorn Voravootivat <puthik@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33180 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Caveh Jalali <caveh@google.com> Reviewed-by: Bob Moragues <moragues@google.com>
2019-06-14mb/google/poppy/var/nami: Ensure SPD index is non-zeroJacob Garber
Memory id's are 1-indexed for DDR4, so we need to check that the SPD index is non-zero before converting it to the 0-indexed value in the bitmap. Change-Id: Icc542239d91c39b89c23f31856c28e7c20b2fc4d Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Found-by: Coverity CID 1387028 Reviewed-on: https://review.coreboot.org/c/coreboot/+/33183 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-06-12Revert "mb/google/poppy/variants/atlas: enable NVMe"caveh jalali
This reverts commit 41979d862a972375d6800afdf2b8b52d408fd220. Reason for revert: NVMe is no longer supported. BUG=b:134752066 Change-Id: I95f2e5f5efe2417700d458f0efd3c793fd8ce8c3 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33307 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Bob Moragues <moragues@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-06-10mb/google/poppy/variants/nami: remove redundant breakEric Lai
Break never comes after return, remove it. BUG=N/A BRANCH=firmware-nami-10775.108.B TEST=N/A Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I005918d6a04cd21df496dea0f2cb1ed6108675af Reviewed-on: https://review.coreboot.org/c/coreboot/+/33299 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-06-03mb/google/poppy/variants/nami: Add fallthrough commentJacob Garber
This fallthrough is intentional (see commit 2257a35862 - Perform PL2 setting for syndra), so add a comment to make that explicit. Change-Id: I57fe1e08f59aed12544cd2a71f1e0464f432f03b Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Found-by: Coverity CID 1397063 Reviewed-on: https://review.coreboot.org/c/coreboot/+/33156 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-05-29mb/google/poppy/variants/nami: Disable FPMCU for non-fingerprint variantsIvy Jian
Even fingerprint device probe failed on non-fingerpint boards,the CRFP driver still register the device that cause the GPE#1 as wake source every time. Override devicetree for non-fingerpirnt variants to avoid unexpected wake event(GPE#1). BUG=b:129650040 BRANCH=firmware-nami-10775.108.B TEST=Boots to OS and check no GPE#1 wake event from eventlog when S0ix exit. Signed-off-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com> Change-Id: I6fa96e04a34e296889414b96a8c604fc61b8a236 Reviewed-on: https://review.coreboot.org/c/coreboot/+/33017 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: John Su <john_su@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-15mb/google/poppy/variants/atlas: Remove B0D4 _PSVPuthikorn Voravootivat
Per Intel, the internal thermal protection is working better than putting B0D4 _PSV in dptf. BUG=b:131251533 TEST=Get ~10% better Octane score. Correct TCC and TCC offset in MSR register. Change-Id: If85afdc673687477ec85a47efcb264a7e5d6ae45 Signed-off-by: Puthikorn Voravootivat <puthik@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32779 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Caveh Jalali <caveh@google.com>
2019-05-15mb/google/poppy/variants/rammus: Support new onboard Hynix memoryKane Chen
Add hynix_dimm_H9CCNNNCLGALAR-NVD for new onboard memory support. BUG=b:130337306 BRANCH=firmware-rammus-11275.B TEST=emerge-rammus coreboot chromeos-ec chromeos-bootimage Flash FW to DUT, and make sure system boots up. Signed-off-by: YanRu Chen <kane_chen@pegatron.corp-partner.google.com> Change-Id: Ibd02953d0c6ac62fa4d7751fd8b103b74433aa73 Reviewed-on: https://review.coreboot.org/c/coreboot/+/32674 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-05-14mb/google/poppy/variant/atlas: Add SPDs for Samsung D-die chipsCaveh Jalali
This adds the SPDs for Samsung D-die 16Gbit and 32Gbit LPDDR3-2133 chips. BUG=b:132206809 TEST=boots on atlas with C-die and D-die memory chips localhost ~ # mosys memory spd print all 0 | LPDDR3 | SO-DIMM 1 | LPDDR3 | SO-DIMM 0 | 1-78: Samsung | 00000000 | K4EBE304ED-EGCG 1 | 1-78: Samsung | 00000000 | K4EBE304ED-EGCG 0 | 8192 | 2 | 64 1 | 8192 | 2 | 64 0 | LPDDR3-800, LPDDR3-1066, LPDDR3-1333, LPDDR3-1600, LPDDR3-1866, LPDDR3-2133 1 | LPDDR3-800, LPDDR3-1066, LPDDR3-1333, LPDDR3-1600, LPDDR3-1866, LPDDR3-2133 localhost ~ # Change-Id: I8ba000aeeb77f07d7f18bda86b3c07f5b50478b8 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32780 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-05-14mb/google/poppy/vr/atlas: Add a W/A for Samsung memory init errorGaggery Tsai
This patch adds a workaround for Samsung C-die 2G/4G memory chips. For unknown reasons, some boards with Samsung LP3 memory chips could not pass early CS/CMD training. MRC has to change the granularity from 16 ticks to 8 ticks, which implies bad margin with this memory chip. Another way is to enhance the drive strength for CS. This patch is to enhance the drive strength for CS and CMD. Enhancing the drive strength for CMD could gain margin abaout 3 more ticks. Root cause needs to be further investigated with memory vendor. BUG=b:131177542 BRANCH=None TEST=USE=fw_debug emerge-atlas chromeos-mrc coreboot chromeos-bootimage & check the MRC log to ensure correct Rcomp values are passed to MRC. Tested with board ID #8 and #11. Change-Id: I9ea3ceda8dc8bf781063d3c16c7c2d9b44e5ddd6 Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32695 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Caveh Jalali <caveh@google.com>
2019-05-13mainboard: remove "recovery" gpio, selectively add "presence" gpio.Matt Delco
The gpio table is only used by depthcharge, and depthcharge rarely has a need for the "recovery" gpio. On a few boards it does use the gpio as a signal for confirming physical presence, so on that boards we'll advertise the board as "presence". All these strings probably should have been #defines to help avoid typos (e.g., the "ec_in_rw" in stout seems questionable since everybody else uses "EC in RW"). Cq-Depend: chromium:1580454 BUG=b:129471321 BRANCH=None TEST=Local compile and flash (with corresponding changes to depthcharge) to 2 systems, one with a "presence" gpio and another without. Confirmed that both systems could enter dev mode. Change-Id: Id6d62d9e48d3e6646cbc1277ea53f0ca95dd849e Signed-off-by: Matt Delco <delco@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32718 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-05-10mb/google/nami: Add VBT blobs and include them in cbfsArthur Heymans
Add vbt files for nami variants and select Kconfig option to utilize them. The default vbt is automatically added by the Kconfig selection and so does not need to be specified in the makefile with the others. Test: boot vayne and akali nami variants, verify display functional and correct vbt loaded. Change-Id: Iaf49bdee7ae82a0a61192327351267f098eb5ab1 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/30427 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-05-03mb/google/poppy/variant/atlas: enable USB acpiGaggery Tsai
Main objective for this change is to export the bluetooth reset gpio to the kernel for use in an rf-kill operation. To do so, we enable USB acpi and define all of the USB2 devices, which includes bluetooth's reset gpio information. BUG=b:122540489 BRANCH=None TEST=emerge-atlas coreboot chromeos-bootimage $cat sys/firmware/acpi/tables/SSDT > /tmp/ssdt.dat & retrieve ssdt.dat from DUT & $iasl -d ./ssdt.dat & check the HS03 node is with "reset-gpio" under _DSD object Change-Id: I411ef707782655361bd1b8ac2b914b8ae64defeb Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/30754 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Caveh Jalali <caveh@google.com>
2019-04-26mb/google/poppy/variants/atlas: Revise AC/DC loadlineGaggery Tsai
This patch revises the AC/DC loadline settings because some major layout changes between proto and evt boards. BUG=b:130740639 BRANCH=None TEST=emerge-atlas coreboot chromeos-bootimage and boot to the OS. Change-Id: Iea12c621e7fab427a0de8f43f0290bf01d0c5a09 Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32359 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: caveh jalali <caveh@chromium.org> Reviewed-by: Caveh Jalali <caveh@google.com>
2019-04-23src: Use include <console/console.h> when appropriateElyes HAOUAS
Change-Id: Iddba5b03fc554a6edc4b26458d834e47958a6b08 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32214 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: David Guckian
2019-04-23src: Add missing include 'console.h'Elyes HAOUAS
Change-Id: Ie21c390ab04adb5b05d5f9760d227d2a175ccb56 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32122 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2019-04-06{mb,soc/intel/skylake}: remove unused InternalGfxMaxim Polyakov
The InternalGfx option in devicetree.cb is not used to enable iGPU. The patch removes this option from chip.h and mb/*/devicetree.cb files for all boards with skl/kbl processor. Change-Id: I41ecca3fdfb1d4b20ee634a13263ff481dcf440e Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32171 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-04-02mb/google/poppy/variants/nami: update sku_ids for PantheonFrank Wu
The sku ids are updated for Pantheon. Sync'ing the sku_ids list in the master sku sheet for Pantheon. BUG=b:121207221 BRANCH=firmware-nami-10775.B TEST=emerge-nami coreboot chromeos-bootimage Change-Id: Ibf683ca8219b2980ea9d9c40b06db264d58440b0 Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32098 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
2019-03-27mb/google/poppy/variants/rammus: Support new onboard Micron memoryKane Chen
Add micron_dimm_MT52L256M32D1PF-107 for new onboard memory support. BUG=none BRANCH=firmware-rammus-11275.B TEST=emerge-rammus coreboot chromeos-ec chromeos-bootimage Flash FW to DUT, and make sure system boots up. Signed-off-by: YanRu Chen <kane_chen@pegatron.corp-partner.google.com> Change-Id: Iaec4147a64313dcd461affb492805c0453e8703d Reviewed-on: https://review.coreboot.org/c/coreboot/+/32046 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-22mb/google/poppy/variants/atlas: DPTF tuning v2Puthikorn Voravootivat
We have more test data now so update the DPTF accordingly. * Change passive temp to 50/57/55/52 C * Change critical temp to 75C * All interval to 20 secs BUG=b:113101335 TEST=temp/perf looks better in thermal chamber test. Change-Id: I872c3f1875d0cbac148c44c449954e6871c9d0b0 Signed-off-by: Puthikorn Voravootivat <puthik@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32018 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-03-16x86/smbios: Untangle system and board tablesNico Huber
We were used to set the same values in the system and board tables. We'll keep the mainboard values as defaults for the system tables, so nothing changes unless somebody overrides the system table hooks. Change-Id: I3c9c95a1307529c3137647a161a698a4c3daa0ae Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/29477 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-03-08coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)Julius Werner
This patch is a raw application of find src/ -type f | xargs sed -i -e 's/IS_ENABLED\s*(CONFIG_/CONFIG(/g' Change-Id: I6262d6d5c23cabe23c242b4f38d446b74fe16b88 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31774 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-03-06mb/google/poppy/variants/nami: Use Pantheon VBTJohn Su
Add new Pantheon sku-id for loading vbt-pantheon.bin BUG=b:78663963 BRANCH=firmware-nami-10775.B TEST=Boots to OS and display comes up. Change-Id: Icd56905e1e04de6f307393ae23f741b93ff23a4c Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31747 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-03-05mainboard: Enable PRESERVE flag in all vboot/chromeos FMD filesHung-Te Lin
For Chrome OS (or vboot), The PRESERVE flags should be applied on following sections: RO_PRESERVE, RO_VPD, RW_PRESERVE, RW_ELOG, RW_NVRAM, RW_SMMSTORE, RW_VPD, RO_FSG (b:116326638), SI_GBE (chromium:936768), SI_PDR (chromium:936768) With the new PRESERVE flag, we don't need RO_PRESERVE and RW_PRESERVE in the future. But it's still no harm to use it if there are multiple sections all needing to be preserved. BUG=chromium:936768 TEST=Builds google/eve and google/kukui inside Chrome OS source tree. Also boots successfully on eve and kukui devices. Change-Id: I6664ae3d955001ed14374e2788d400ba5fb9b7f8 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31709 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-03-04arch/io.h: Add missing includesKyösti Mälkki
Fixes indirect includes that would break with followup work. Change-Id: I37ca01b904a0b422a4d09475377e755e167a6ab3 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/31697 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-03-04Revert "mb/google/poppy/variants/atlas: Update DPTF parameters"Puthikorn Voravootivat
This reverts commit 5e90ef8c356099e42612bc97976c67092d0810ff. Reason for revert: The 1s interval causes early throttle in usage spike. (log in b/123895423#comment3) BUG=b:113101335 BRANCH=None TEST=learning from Nocturne Change-Id: Id6467b51eb937b89b4c08641f36266544c8fa176 Signed-off-by: Puthikorn Voravootivat <puthik@chromium.org> Reviewed-on: https://review.coreboot.org/c/31655 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2019-03-01device/pci: Fix PCI accessor headersKyösti Mälkki
PCI config accessors are no longer indirectly included from <arch/io.h> use <device/pci_ops.h> instead. Change-Id: I2adf46430a33bc52ef69d1bf7dca4655fc8475bd Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/31675 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-03-01soc/intel/skylake: Unify serial IRQ optionsNico Huber
We had two ways to configure the serial IRQ mode. One time in the devicetree for FSP and one time through Kconfig for coreboot. We'll use `enum serirq_mode` from soc/intel/common/ as a devicetree option instead. As the default is `quiet mode` here and that is the most common mode, this saves us a lot of lines. In four cases kblrvp8, 11 and librem 13v2, 15v3, we had conflicting settings in devicetree and Kconfig. We'll maintain the `continuous` selection, although it might be that coreboot overrode this earlier on the kblrvps. Note: A lot of Google boards have serial IRQ enabled, while the pin seems to be unconnected? Change-Id: I79f0cd302e335d8dcf8bf6bc32f3d40ca6713e5c Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/31596 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-02-28mb/google/poppy/variants/atlas: Update DPTF parametersPuthikorn Voravootivat
Preliminary dptf change for Atlas - Throttle charger using all temp sensors (not just ambient) - Throttle charger with higher priority than CPU - Update throttle temperature using data from surface thermistor in thermal chamber test BUG=b:113101335 BRANCH=None TEST=based on preliminary data from thermal chamber test Change-Id: Ic1ab72f569e8a4f7bffc5560518fb703d32f4b21 Signed-off-by: Puthikorn Voravootivat <puthik@chromium.org> Reviewed-on: https://review.coreboot.org/c/31628 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Caveh Jalali <caveh@google.com>
2019-02-28mb/google/poppy/variants/atlas: Add tdp_pl1_override valuePuthikorn Voravootivat
Use 7w PL1 with DPTF throttle to enable better performance for atlas. BUG=b:113101335 BRANCH=None TEST=Recommend setting from thermal team. Build coreboot on atlas Change-Id: Idcf44f213259634a507a013b31b410ed322e9479 Signed-off-by: Puthikorn Voravootivat <puthik@chromium.org> Reviewed-on: https://review.coreboot.org/c/31627 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Caveh Jalali <caveh@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-22mb/google/poppy/variants/atlas: move WiFi wake to GPP_B7Caveh Jalali
The latest rev. of the atlas board moves the WiFi wake source from WAKE# to GPP_B7. The original GPP_A0 in the device tree is just wrong. This also reconfigures DW1 to the GPP_B group so we can use GPP_B7 as a wake source. GPP_B7 is still configured as a no-connect in gpio.c, so this doesn't actually enable WiFi wake. We'll follow up with another patch to set up GPP_B7 properly on boards that support it. BUG=b:122327852 BRANCH=none TEST=atlas still boots Change-Id: I1816500dd0ab6186fd51aa6945faf73d00c152fe Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://review.coreboot.org/c/31211 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-02-18soc/intel/skylake: Use real common code for VMX initNico Huber
Use the common VMX implementation, and set IA32_FEATURE_CONTROL lock bit per Kconfig *after* SGX is configured (as SGX also sets bits on the IA32_FEATURE_CONTROL register). As it is now correctly based on a Kconfig, the `VmxEnable` devicetree setting vanishes. Test: build/boot google/[chell,fizz], observe Virtualization enabled under Windows 10 when VMX enabled and lock bit set. Change-Id: Iea598cf74ba542a650433719f29cb5c9df700c0f Signed-off-by: Nico Huber <nico.h@gmx.de> Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/29682 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-02-13mb/google/poppy/var/rammus: Enable mode change wake source for S3/S0ixFurquan Shaikh
This change enables mode change as a wake source for S3 and S0ix. Change-Id: I2e7f9997776b1e024ea417eb69e6c2ffa8c62580 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/31296 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Zhuohao Lee <zhuohao@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-02-05mb/google/poppy/variants/atlas: config GPP_D1 as no-connectCaveh Jalali
This reconfigures the GPP_D1 GPIO pin as a no-connect. It really doesn't go anywhere today or on previous revs of the board. BUG=b:110614620 BRANCH=none TEST=atlas still boots Change-Id: Iea53cf909f8f060c4e0f14e8b4ad579b838b7caa Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://review.coreboot.org/c/31210 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-02-05Revert "mb/google/poppy/variant/atlas: I2C: run trackpad at 1MHz"Caveh Jalali
This reverts commit 7696290004b6490c7ef8027d7ddf67b163e7dad8. We're seeing trackpad problems on some units with the I2C bus running at 1MHz but not at 400KHz. So, revert back to 400KHz until we understand how to make 1MHz operation more robust. BUG=b:123650686 Change-Id: Ifb06afece9eee0c153240d35e6c3001f5b74f310 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://review.coreboot.org/c/31212 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-01-23mb/google/poppy/variant/nami: disable unused usb2 portsRen Kuo
disable unused usb2 ports of bard and ekko skus BUG=120874946 TEST=build a test firmware and run lsusb to check usb ports Change-Id: I2ef3cd17ada8b65c96bc80675650905949f235e1 Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/30986 Reviewed-by: Vincent Wang <vwang@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-23mb/google/poppy/variants/nami: close the FP power in S5Ren Kuo
close the FP module power in power off (s5) BUG=122887366 BRANCH=Nami TEST= build test firmware and measure the fp power enable pin Change-Id: I80ddfbf1edf7c6435d263d5f5e0edb8b8701817d Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/30910 Reviewed-by: Shelley Chen <shchen@google.com> Reviewed-by: Vincent Wang <vwang@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-01-16buildsystem: Promote rules.h to default includeKyösti Mälkki
Does not fix 3rdparty/, *.S or *.ld or yet. Change-Id: I66b48013dd89540b35ab219d2b64bc13f5f19cda Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/17656 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-01-15mb/google/atlas: Enable camera module NVMChen, JasonX Z
Enable at24 EEPROM by adding ASL of nvm BUG=b:122583978 BRANCH=master TEST=Build and run for basic camera functions Change-Id: Ifc2060c2ceb7d1a8ef490f36f484deb425a37c95 Signed-off-by: Chen, JasonX Z <jasonx.z.chen@intel.com> Reviewed-on: https://review.coreboot.org/c/30795 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
2019-01-14/src/mb/google/poppy/variants/atlas: Revise SPK resetGaggery Tsai
This patch revises the pad reset config of speaker reset GPIO pin from RSMRST to PLTRST. Audio engineer suggested to reset the amps with warm reset. BUG=b:122441567 BRANCH=None TEST=warm & cold reset & suspend_stress_test -c 10 and ensure the speakers are working well. Change-Id: I87c554b186b068da93e1662a97afaf01dddae0ef Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com> Reviewed-on: https://review.coreboot.org/c/30866 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2019-01-11soc/mainboard: Update mainboard UART KconfigLijian Zhao
After f5ca922 (Untangle CBFS microcode updates) got merged, all mainboard using intel apollolake, cannonlake, coffeelake, glk, kabylake, skylake, icelake and whiskeylake get affected. Using INTEL_LPSS_UART_FOR_CONSOLE instead of UART_DEBUG and set default console for each platform. BUG=N/A TEST=Build and test on Sarien platform, by default we can still get console from cbmem, and enable CONSOLE_SERIAL can get logs from UART port 2. Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Change-Id: I550a00144cff21420537bb161c64e7a132c5d2de Reviewed-on: https://review.coreboot.org/c/30853 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-01-07mb/google/poppy/variant/rammus: enable USB acpimarxwang
Main objective for this change is to export the bluetooth reset gpio to the kernel for use in an rf-kill operation. To do so, we enable USB acpi and define all of the USB2 devices, which includes bluetooth's reset gpio information. BUG=b:119899987 TEST=build and flash to rammus, log into rammus and 'cat /sys/firmware/acpi/tables/SSDT > /tmp/ssdt.dml', copy that ssdt.dsml to /tmp/ssdt.dml on host machine, 'iasl -d /tmp/ssdt.dml', then verify that "reset gpio" shows up in the HS03 node's _DSD package in the table. Signed-off-by: marxwang <marx.wang@intel.com> Change-Id: Ieadb3609c7634a20e96c7c4dfb96f5e3f23e468b Reviewed-on: https://review.coreboot.org/c/30607 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Zhuohao Lee <zhuohao@google.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2019-01-06device: Use pcidev_path_on_root()Kyösti Mälkki
Change-Id: I2e28b9f4ecaf258bff8a062b5a54cb3d8e2bb9b0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/30400 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-01-03mb/google/poppy/variants/nami: Add sku_ids for PantheonFrank Wu
Sync'ing the sku_ids list in the master sku sheet for Pantheon. BUG=b:121207221 BRANCH=firmware-nami-10775.B TEST=emerge-nami coreboot chromeos-bootimage Change-Id: Ic03c3a6fe238f2692ce15c45016115087380c0ca Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/30412 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2019-01-03src/mainboard: Use smm-$(CONFIG_HAVE_SMI_HANDLER)Elyes HAOUAS
Use smm-$(CONFIG_HAVE_SMI_HANDLER) instead of smm-y Change-Id: I0f91bc3e6c8ab31d837ab89af62d700b35c1e01b Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/30485 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-12-28mb/google/poppy/variant/nami: add the vbt setting for bard skuRen Kuo
Modify the vbios's eDP signal setting from level0(0dB) to level1 (3.5dB) for bard Add VBT blobs and include it in cbfs BUG=b:119448457 TEST=Test & measure eDP signal Change-Id: I0b854a6adad43844282aed61d26e798727b5cb62 Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/30375 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-28mainboard/google/poppy/variants/rammus: Fixed touchscreen function failedKane Chenffd
According to issue tracker b:119238959 #4 & #6. Hardware modify design to make GPP_E3 to be a switch of touchscreen I2C CLK and SDA. Control GPP_E3 to make touchscreen I2C CLK and SDA keep low during power on initialization to avoid data transfer during this time. After touchscreen IC initial complete, control GPP_E3 to high to make touchscreen I2C CLK and SDA work normally. Depending on touchscreen IC specification, device take 105ms for power on initialization. Change delay time from 120ms to 105ms. BUG=b:119238959 BRANCH=firmware-rammus-11275.B TEST=emerge-rammus coreboot chromeos-ec chromeos-bootimage Flash FW to DUT, run S5 stress test and verify the result Signed-off-by: YanRu Chen <kane_chen@pegatron.corp-partner.google.com> Change-Id: I86452c1445243c499aeaf931dba286db169c5628 Reviewed-on: https://review.coreboot.org/c/30180 Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-21mb/google/poppy/variants/atlas: Remove duplicate entry of dptf_enableSumeet Pawnikar
Remove duplicate entry of dptf_enable. BRANCH=None BUG=None TEST=None Change-Id: I3ddd6a702180624d31c5c58c71acdce8f627c925 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/30338 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-12-21mb/google/poppy/variants/nami: Add micron_dimm_MT40A512M16TB-062EJ SPDFrank Wu
Add SPD file for micron_dimm_MT40A512M16TB-062EJ (ram id: 12) BUG=b:121217853 BRANCH=firmware-nami-10775.B TEST=emerge-nami coreboot chromeos-bootimage Change-Id: I45e6a7a183556fb085f5442cd6bb429d79ef4235 Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/30327 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-12-21mb/google/poppy/variants/nami: Add micron_dimm_MT40A256M16LY-075F SPDIvy Jian
Add SPD file for sdp micron_dimm_MT40A256M16LY-075F (ram id: 11) BUG=b:120884302 BRANCH=firmware-nami-10775.B TEST=emerge-nami coreboot chromeos-bootimage Change-Id: Icf731bfefd550e9b94b6404bc870d4d76451deb1 Signed-off-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/30183 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-12-20Revert "mb/google/poppy/variants/nocturne: Add DMIC properties to ACPI DSD"Jenny TC
This reverts commit 999b916015ea0558e3821bdb51501b43a60b5ed6. The DMIC doesn't have an ACPI id. The patch which enables ACPI device with id DMIC may create conflict in the feature. Also the ACPI id "DMIC" doesn't comply with ACPI naming conventions. The issue for which the patch was introduced, is already addressed in kernel DMIC driver and the patches are upstreamed in to the Linux kernel. Change-Id: I42cb076700dcb5906599471bebfcd5b265b17644 Signed-off-by: Jenny TC <jenny.tc@intel.com> Reviewed-on: https://review.coreboot.org/c/30151 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2018-12-19mb/google/variant/nocturne: set CONFIG_NO_FADT_8042Nick Vaccaro
Set CONFIG_NO_FADT_8042 to avoid probing for the 8042 controller. This speeds up boot on nocturne by 1.3 seconds: Before change: [2.162266] EXT4-fs (mmcblk0p3): mounting ext2 file system using the ext4 subsystem After change: [0.867735] EXT4-fs (mmcblk0p3): mounting ext2 file system using the ext4 subsystem BUG=b:120960844 BRANCH=none TEST=build, flash, and boot nocturne; check dmesg to verify that boot is faster and that you don't see the following log in dmesg: [0.671501] i8042: Probing ports directly. Change-Id: I62a16e6de5e74fa17970d9967f6d1628497ec1d3 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/30283 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-18mb/google/poppy/variants/nami: Add sku_ids for SyndraAmanda Huang
Sync'ing the sku_ids list in the master sku sheet. BUG=b:112876867 Change-Id: I658e8dc67679b5b528ab267861a1151f50e42414 Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/30265 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-12-17mb/google/poppy/variants/nami: perform PL2 setting for bard/ekkoRen Kuo
According to bard/ekko cpu types, PL2 need to set the values 1. KBL_U PL2 is 25w. 2. KBL_R PL2 is 29w. BUG=b:120874861 TEST=power on and check the DUT can boot up well Change-Id: I5f9d672c4244c363a7cfb362653663a065259fc0 Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/30178 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-12-11mb/google/poppy/variants/nami: Modify SPD for hynix memory partRen Kuo
correct memory part name form hynix_dimm_H5ANAG6NCMR-VKC to hynix_dimm_H5AN4G6NAFR-UHC BUG=b:113983573 BRANCH=Nami TEST=emerge-nami coreboot chromeos-bootimage Change-Id: I0c33343eb1269919fba324333897805da1d1ff9b Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/30076 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2018-12-06rammus: ELAN touchpad I2C special timing requirementkane_chen
According to issue tracker b:119899090. https://partnerissuetracker.corp.google.com/issues/119899090 We modify rammus devicetree.cb .i2c[1] configuration to meet ELAN touchpad I2C special timing requirement. BUG=b:119899090 BRANCH=firmware-rammus-11275.B TEST=emerge-rammus coreboot chromeos-ec chromeos-bootimage Flash FW to DUT, and check touchpad I2C characteristics meet requirement Signed-off-by: YanRu chen <kane_chen@pegatron.corp-partner.google.com> Change-Id: Ifeb08c2530e6a7674f23f7d48cefa16cfc59cb13 Reviewed-on: https://review.coreboot.org/c/29922 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-04mb/google/poppy/variant/nocturne: adjust RcompTarget to fix DRAM corruptionNick Vaccaro
BUG=b:111812662 TEST=flash to nocturne, boot nocturne, run "memtester 1g" and verify it passes. Change-Id: Iefc3957f915a39a47ad6018459e65b70d1b34091 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/29361 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2018-12-04mb/google/poppy/variants/nami: update bard/ekko sku idsRen Kuo
update the new sku ids of bard/ekko BUG=b:120257865 BRANCH=Nami TEST=emerge-nami coreboot chromeos-bootimage write the new sku id in cbi and verify the fw to check it can get the correct settings by the sku id Change-Id: I3579d3d8042a270d8ea8e2f7b5612ff8e2cdfa7b Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/30031 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-03mb/google/poppy/variant/nocturne: increase touch panel power-on delayNick Vaccaro
The WACOM 5C01 touch panel power-up delay of 10mS is too aggressive and causes "failed to change power setting" errors in the kernel, so this change increases the power-up delay to 20mS which allows enough time for the WACOM device's i2c controller to wake up. BUG=b:120090384 BRANCH=none TEST=flash and boot nocturne, log into kernel, execute the following command and make sure the string is not found : dmesg | grep "failed to change power setting" Change-Id: I1db0b3f5ce666b79d8ada2939ec865233ce52a56 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/29988 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-03mb/poppy/variant/nami: Move FPMCU_INT_L gpios to B groupShelley Chen
We discovered that the gpios previously used for FPMCU_INT_L were in two different groups with two different voltages (C group was at 3.3V and D group was at 1.8V). Moving both to B group which is at 3.3V. BUG=b:119447525 BRANCH=Nami TEST=unlock OS with fingerprint register fingerprint run powerd_dbus_suspend and see if it goes int s0ix Change-Id: I2332b0eb7a2f74e8178b95a23c8ac2091027a071 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/29872 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-11-30cpu/intel/common: Use a common acpi/cpu.asl fileArthur Heymans
Change-Id: Ifa5a3a22771ff2e0efa14fb765603fd5e0440d59 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/29894 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: David Guckian
2018-11-27mb/google/poppy/variants/nami: Enable g2touch touchscreen deviceCrystal Lin
This change adds ACPI properties for GTCH7503 device. BUG=b:119169362 BRANCH=firmware-nami-10775.B TEST=Verify touchscreen works with this change Change-Id: I26e16b7e118121b3dd9a88c76d04898b97753df0 Signed-off-by: Crystal Lin <crystal_lin@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/29768 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-23mb: Set coreboot as DSDT's manufacturer model IDElyes HAOUAS
Field 'OEMID' & "OEM Table ID" are related to DSDT table not to mainboard. So use macro to set them respectvely to "COREv4" and "COREBOOT". Change-Id: I060e07a730e721df4a86128ee89bfe168c69f31e Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/29790 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: David Guckian
2018-11-22mb/google/poppy/variant/nocturne: enable USB acpiNick Vaccaro
Main objective for this change is to export the bluetooth reset gpio to the kernel for use in an rf-kill operation. To do so, we enable USB acpi and define all of the USB2 devices, which includes bluetooth's reset gpio information. This change produces the following nodes in the SSDT : Scope (\_SB.PCI0.XHCI.RHUB.HS01) { Name (_DDN, "USB Type C Port 1") // _DDN: DOS Device Name Name (_UPC, Package (0x04) // _UPC: USB Port Capabilities { 0xFF, 0x09, Zero, Zero }) Name (_PLD, ToPLD ( PLD_Revision = 0x2, PLD_IgnoreColor = 0x1, PLD_Red = 0x0, PLD_Green = 0x0, PLD_Blue = 0x0, PLD_Width = 0x0, PLD_Height = 0x0, PLD_UserVisible = 0x1, PLD_Dock = 0x0, PLD_Lid = 0x0, PLD_Panel = "UNKNOWN", PLD_VerticalPosition = "CENTER", PLD_HorizontalPosition = "CENTER", PLD_Shape = "OVAL", PLD_GroupOrientation = 0x0, PLD_GroupToken = 0x0, PLD_GroupPosition = 0x0, PLD_Bay = 0x0, PLD_Ejectable = 0x0, PLD_EjectRequired = 0x0, PLD_CabinetNumber = 0x0, PLD_CardCageNumber = 0x0, PLD_Reference = 0x0, PLD_Rotation = 0x0, PLD_Order = 0x0, PLD_VerticalOffset = 0x0, PLD_HorizontalOffset = 0x0) ) // _PLD: Physical Location of Device } Scope (\_SB.PCI0.XHCI.RHUB.HS03) { Name (_DDN, "Bluetooth") // _DDN: DOS Device Name Name (_UPC, Package (0x04) // _UPC: USB Port Capabilities { 0xFF, 0xFF, Zero, Zero }) Name (_PLD, ToPLD ( PLD_Revision = 0x2, PLD_IgnoreColor = 0x1, PLD_Red = 0x0, PLD_Green = 0x0, PLD_Blue = 0x0, PLD_Width = 0x0, PLD_Height = 0x0, PLD_UserVisible = 0x0, PLD_Dock = 0x0, PLD_Lid = 0x0, PLD_Panel = "UNKNOWN", PLD_VerticalPosition = "CENTER", PLD_HorizontalPosition = "CENTER", PLD_Shape = "UNKNOWN", PLD_GroupOrientation = 0x0, PLD_GroupToken = 0x0, PLD_GroupPosition = 0x0, PLD_Bay = 0x0, PLD_Ejectable = 0x0, PLD_EjectRequired = 0x0, PLD_CabinetNumber = 0x0, PLD_CardCageNumber = 0x0, PLD_Reference = 0x0, PLD_Rotation = 0x0, PLD_Order = 0x0, PLD_VerticalOffset = 0x0, PLD_HorizontalOffset = 0x0) ) // _PLD: Physical Location of Device Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings { GpioIo (Exclusive, PullDefault, 0x0000, 0x0000, IoRestrictionOutputOnly, "\\_SB.PCI0.GPIO", 0x00, ResourceConsumer, , ) { // Pin list 0x0062 } }) Name (_DSD, Package (0x02) // _DSD: Device-Specific Data { ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301") /* Device Properties for _DSD */, Package (0x01) { Package (0x02) { "reset-gpio", Package (0x04) { \_SB.PCI0.XHCI.RHUB.HS03, Zero, Zero, One } } } }) } Scope (\_SB.PCI0.XHCI.RHUB.HS05) { Name (_DDN, "USB Type C Port 2") // _DDN: DOS Device Name Name (_UPC, Package (0x04) // _UPC: USB Port Capabilities { 0xFF, 0x09, Zero, Zero }) Name (_PLD, ToPLD ( PLD_Revision = 0x2, PLD_IgnoreColor = 0x1, PLD_Red = 0x0, PLD_Green = 0x0, PLD_Blue = 0x0, PLD_Width = 0x0, PLD_Height = 0x0, PLD_UserVisible = 0x1, PLD_Dock = 0x0, PLD_Lid = 0x0, PLD_Panel = "UNKNOWN", PLD_VerticalPosition = "CENTER", PLD_HorizontalPosition = "CENTER", PLD_Shape = "OVAL", PLD_GroupOrientation = 0x0, PLD_GroupToken = 0x0, PLD_GroupPosition = 0x0, PLD_Bay = 0x0, PLD_Ejectable = 0x0, PLD_EjectRequired = 0x0, PLD_CabinetNumber = 0x0, PLD_CardCageNumber = 0x0, PLD_Reference = 0x0, PLD_Rotation = 0x0, PLD_Order = 0x0, PLD_VerticalOffset = 0x0, PLD_HorizontalOffset = 0x0) ) // _PLD: Physical Location of Device } Scope (\_SB.PCI0.XHCI.RHUB.HS07) { Name (_DDN, "POGO") // _DDN: DOS Device Name Name (_UPC, Package (0x04) // _UPC: USB Port Capabilities { 0xFF, 0xFF, Zero, Zero }) Name (_PLD, ToPLD ( PLD_Revision = 0x2, PLD_IgnoreColor = 0x1, PLD_Red = 0x0, PLD_Green = 0x0, PLD_Blue = 0x0, PLD_Width = 0x0, PLD_Height = 0x0, PLD_UserVisible = 0x0, PLD_Dock = 0x0, PLD_Lid = 0x0, PLD_Panel = "UNKNOWN", PLD_VerticalPosition = "CENTER", PLD_HorizontalPosition = "CENTER", PLD_Shape = "UNKNOWN", PLD_GroupOrientation = 0x0, PLD_GroupToken = 0x0, PLD_GroupPosition = 0x0, PLD_Bay = 0x0, PLD_Ejectable = 0x0, PLD_EjectRequired = 0x0, PLD_CabinetNumber = 0x0, PLD_CardCageNumber = 0x0, PLD_Reference = 0x0, PLD_Rotation = 0x0, PLD_Order = 0x0, PLD_VerticalOffset = 0x0, PLD_HorizontalOffset = 0x0) ) // _PLD: Physical Location of Device } BUG=b:119275094 TEST=build and flash to nocturne, log into nocturne and 'cat /sys/firmware/acpi/tables/SSDT > /tmp/ssdt.dml', copy that ssdt.dsml to /tmp/ssdt.dml on host machine, 'iasl -d /tmp/ssdt.dml', then verify that "reset gpio" shows up in the HS03 node's _DSD package in the table. Change-Id: I65d9b580fd69fd0a2c84f14b78a8e8b5e9217b16 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/29622 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Rajat Jain <rajatja@google.com>
2018-11-22mb/google/poppy/variants/nami: Split FP MCU Wake and IRQ GPIOSShelley Chen
We are seeing problems (interrupt storm) with using the same gpio for FP MCU wake and irq signals. Reverting back to using separate gpios for wake and irq until we resolve the issue. BUG=b:119447525, b:115706071 BRANCH=Nami TEST=Run powerd_dbus_suspend from kernel and make sure see DUT drop into S0ix in the EC console. Also, unlock from lock screen with fingerprint. Change-Id: Id7987f28526256808b8ed49e66f66298f7cdbcee Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/29665 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Vincent Wang <vwang@google.com>
2018-11-21ACPI: Fix DSDT's revision fieldElyes HAOUAS
DSDT revision is =1 for ACPI v1 and =2 for greater ACPI version. This will cause the AML interpreter to use 32-bit integers and math if the version is 1, and 64-bit if the version is >=2. Current spec version is 2 for ACPI 6.2-a. Change-Id: I77372882d5c77b7ed52dcdd88028403df6f6fa7f Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/29626 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-17mb/google/poppy/variants/nami: Invert FP MCU wake signalShelley Chen
GPP_D6 needs to be inverted to enter S0ix because FPMCU_INT_L is active low. Keeps device awake otherwise. BUG=b:119447525, b:115706071 BRANCH=Nami TEST=Run powerd_dbus_suspend from kernel and make sure see DUT drop into S0ix in the EC console. Change-Id: Iad5df124e2439bbdc078d6a33f8d0510d25ecf6f Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/29650 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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