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2019-01-16buildsystem: Promote rules.h to default includeKyösti Mälkki
Does not fix 3rdparty/, *.S or *.ld or yet. Change-Id: I66b48013dd89540b35ab219d2b64bc13f5f19cda Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/17656 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-01-15mb/google/atlas: Enable camera module NVMChen, JasonX Z
Enable at24 EEPROM by adding ASL of nvm BUG=b:122583978 BRANCH=master TEST=Build and run for basic camera functions Change-Id: Ifc2060c2ceb7d1a8ef490f36f484deb425a37c95 Signed-off-by: Chen, JasonX Z <jasonx.z.chen@intel.com> Reviewed-on: https://review.coreboot.org/c/30795 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
2019-01-14/src/mb/google/poppy/variants/atlas: Revise SPK resetGaggery Tsai
This patch revises the pad reset config of speaker reset GPIO pin from RSMRST to PLTRST. Audio engineer suggested to reset the amps with warm reset. BUG=b:122441567 BRANCH=None TEST=warm & cold reset & suspend_stress_test -c 10 and ensure the speakers are working well. Change-Id: I87c554b186b068da93e1662a97afaf01dddae0ef Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com> Reviewed-on: https://review.coreboot.org/c/30866 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2019-01-11soc/mainboard: Update mainboard UART KconfigLijian Zhao
After f5ca922 (Untangle CBFS microcode updates) got merged, all mainboard using intel apollolake, cannonlake, coffeelake, glk, kabylake, skylake, icelake and whiskeylake get affected. Using INTEL_LPSS_UART_FOR_CONSOLE instead of UART_DEBUG and set default console for each platform. BUG=N/A TEST=Build and test on Sarien platform, by default we can still get console from cbmem, and enable CONSOLE_SERIAL can get logs from UART port 2. Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Change-Id: I550a00144cff21420537bb161c64e7a132c5d2de Reviewed-on: https://review.coreboot.org/c/30853 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2019-01-07mb/google/poppy/variant/rammus: enable USB acpimarxwang
Main objective for this change is to export the bluetooth reset gpio to the kernel for use in an rf-kill operation. To do so, we enable USB acpi and define all of the USB2 devices, which includes bluetooth's reset gpio information. BUG=b:119899987 TEST=build and flash to rammus, log into rammus and 'cat /sys/firmware/acpi/tables/SSDT > /tmp/ssdt.dml', copy that ssdt.dsml to /tmp/ssdt.dml on host machine, 'iasl -d /tmp/ssdt.dml', then verify that "reset gpio" shows up in the HS03 node's _DSD package in the table. Signed-off-by: marxwang <marx.wang@intel.com> Change-Id: Ieadb3609c7634a20e96c7c4dfb96f5e3f23e468b Reviewed-on: https://review.coreboot.org/c/30607 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Zhuohao Lee <zhuohao@google.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2019-01-06device: Use pcidev_path_on_root()Kyösti Mälkki
Change-Id: I2e28b9f4ecaf258bff8a062b5a54cb3d8e2bb9b0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/30400 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-01-03mb/google/poppy/variants/nami: Add sku_ids for PantheonFrank Wu
Sync'ing the sku_ids list in the master sku sheet for Pantheon. BUG=b:121207221 BRANCH=firmware-nami-10775.B TEST=emerge-nami coreboot chromeos-bootimage Change-Id: Ic03c3a6fe238f2692ce15c45016115087380c0ca Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/30412 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2019-01-03src/mainboard: Use smm-$(CONFIG_HAVE_SMI_HANDLER)Elyes HAOUAS
Use smm-$(CONFIG_HAVE_SMI_HANDLER) instead of smm-y Change-Id: I0f91bc3e6c8ab31d837ab89af62d700b35c1e01b Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/30485 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-12-28mb/google/poppy/variant/nami: add the vbt setting for bard skuRen Kuo
Modify the vbios's eDP signal setting from level0(0dB) to level1 (3.5dB) for bard Add VBT blobs and include it in cbfs BUG=b:119448457 TEST=Test & measure eDP signal Change-Id: I0b854a6adad43844282aed61d26e798727b5cb62 Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/30375 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-28mainboard/google/poppy/variants/rammus: Fixed touchscreen function failedKane Chenffd
According to issue tracker b:119238959 #4 & #6. Hardware modify design to make GPP_E3 to be a switch of touchscreen I2C CLK and SDA. Control GPP_E3 to make touchscreen I2C CLK and SDA keep low during power on initialization to avoid data transfer during this time. After touchscreen IC initial complete, control GPP_E3 to high to make touchscreen I2C CLK and SDA work normally. Depending on touchscreen IC specification, device take 105ms for power on initialization. Change delay time from 120ms to 105ms. BUG=b:119238959 BRANCH=firmware-rammus-11275.B TEST=emerge-rammus coreboot chromeos-ec chromeos-bootimage Flash FW to DUT, run S5 stress test and verify the result Signed-off-by: YanRu Chen <kane_chen@pegatron.corp-partner.google.com> Change-Id: I86452c1445243c499aeaf931dba286db169c5628 Reviewed-on: https://review.coreboot.org/c/30180 Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-21mb/google/poppy/variants/atlas: Remove duplicate entry of dptf_enableSumeet Pawnikar
Remove duplicate entry of dptf_enable. BRANCH=None BUG=None TEST=None Change-Id: I3ddd6a702180624d31c5c58c71acdce8f627c925 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/30338 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-12-21mb/google/poppy/variants/nami: Add micron_dimm_MT40A512M16TB-062EJ SPDFrank Wu
Add SPD file for micron_dimm_MT40A512M16TB-062EJ (ram id: 12) BUG=b:121217853 BRANCH=firmware-nami-10775.B TEST=emerge-nami coreboot chromeos-bootimage Change-Id: I45e6a7a183556fb085f5442cd6bb429d79ef4235 Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/30327 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-12-21mb/google/poppy/variants/nami: Add micron_dimm_MT40A256M16LY-075F SPDIvy Jian
Add SPD file for sdp micron_dimm_MT40A256M16LY-075F (ram id: 11) BUG=b:120884302 BRANCH=firmware-nami-10775.B TEST=emerge-nami coreboot chromeos-bootimage Change-Id: Icf731bfefd550e9b94b6404bc870d4d76451deb1 Signed-off-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/30183 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-12-20Revert "mb/google/poppy/variants/nocturne: Add DMIC properties to ACPI DSD"Jenny TC
This reverts commit 999b916015ea0558e3821bdb51501b43a60b5ed6. The DMIC doesn't have an ACPI id. The patch which enables ACPI device with id DMIC may create conflict in the feature. Also the ACPI id "DMIC" doesn't comply with ACPI naming conventions. The issue for which the patch was introduced, is already addressed in kernel DMIC driver and the patches are upstreamed in to the Linux kernel. Change-Id: I42cb076700dcb5906599471bebfcd5b265b17644 Signed-off-by: Jenny TC <jenny.tc@intel.com> Reviewed-on: https://review.coreboot.org/c/30151 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2018-12-19mb/google/variant/nocturne: set CONFIG_NO_FADT_8042Nick Vaccaro
Set CONFIG_NO_FADT_8042 to avoid probing for the 8042 controller. This speeds up boot on nocturne by 1.3 seconds: Before change: [2.162266] EXT4-fs (mmcblk0p3): mounting ext2 file system using the ext4 subsystem After change: [0.867735] EXT4-fs (mmcblk0p3): mounting ext2 file system using the ext4 subsystem BUG=b:120960844 BRANCH=none TEST=build, flash, and boot nocturne; check dmesg to verify that boot is faster and that you don't see the following log in dmesg: [0.671501] i8042: Probing ports directly. Change-Id: I62a16e6de5e74fa17970d9967f6d1628497ec1d3 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/30283 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-18mb/google/poppy/variants/nami: Add sku_ids for SyndraAmanda Huang
Sync'ing the sku_ids list in the master sku sheet. BUG=b:112876867 Change-Id: I658e8dc67679b5b528ab267861a1151f50e42414 Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/30265 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-12-17mb/google/poppy/variants/nami: perform PL2 setting for bard/ekkoRen Kuo
According to bard/ekko cpu types, PL2 need to set the values 1. KBL_U PL2 is 25w. 2. KBL_R PL2 is 29w. BUG=b:120874861 TEST=power on and check the DUT can boot up well Change-Id: I5f9d672c4244c363a7cfb362653663a065259fc0 Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/30178 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-12-11mb/google/poppy/variants/nami: Modify SPD for hynix memory partRen Kuo
correct memory part name form hynix_dimm_H5ANAG6NCMR-VKC to hynix_dimm_H5AN4G6NAFR-UHC BUG=b:113983573 BRANCH=Nami TEST=emerge-nami coreboot chromeos-bootimage Change-Id: I0c33343eb1269919fba324333897805da1d1ff9b Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/30076 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2018-12-06rammus: ELAN touchpad I2C special timing requirementkane_chen
According to issue tracker b:119899090. https://partnerissuetracker.corp.google.com/issues/119899090 We modify rammus devicetree.cb .i2c[1] configuration to meet ELAN touchpad I2C special timing requirement. BUG=b:119899090 BRANCH=firmware-rammus-11275.B TEST=emerge-rammus coreboot chromeos-ec chromeos-bootimage Flash FW to DUT, and check touchpad I2C characteristics meet requirement Signed-off-by: YanRu chen <kane_chen@pegatron.corp-partner.google.com> Change-Id: Ifeb08c2530e6a7674f23f7d48cefa16cfc59cb13 Reviewed-on: https://review.coreboot.org/c/29922 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-04mb/google/poppy/variant/nocturne: adjust RcompTarget to fix DRAM corruptionNick Vaccaro
BUG=b:111812662 TEST=flash to nocturne, boot nocturne, run "memtester 1g" and verify it passes. Change-Id: Iefc3957f915a39a47ad6018459e65b70d1b34091 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/29361 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2018-12-04mb/google/poppy/variants/nami: update bard/ekko sku idsRen Kuo
update the new sku ids of bard/ekko BUG=b:120257865 BRANCH=Nami TEST=emerge-nami coreboot chromeos-bootimage write the new sku id in cbi and verify the fw to check it can get the correct settings by the sku id Change-Id: I3579d3d8042a270d8ea8e2f7b5612ff8e2cdfa7b Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/30031 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-03mb/google/poppy/variant/nocturne: increase touch panel power-on delayNick Vaccaro
The WACOM 5C01 touch panel power-up delay of 10mS is too aggressive and causes "failed to change power setting" errors in the kernel, so this change increases the power-up delay to 20mS which allows enough time for the WACOM device's i2c controller to wake up. BUG=b:120090384 BRANCH=none TEST=flash and boot nocturne, log into kernel, execute the following command and make sure the string is not found : dmesg | grep "failed to change power setting" Change-Id: I1db0b3f5ce666b79d8ada2939ec865233ce52a56 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/29988 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-12-03mb/poppy/variant/nami: Move FPMCU_INT_L gpios to B groupShelley Chen
We discovered that the gpios previously used for FPMCU_INT_L were in two different groups with two different voltages (C group was at 3.3V and D group was at 1.8V). Moving both to B group which is at 3.3V. BUG=b:119447525 BRANCH=Nami TEST=unlock OS with fingerprint register fingerprint run powerd_dbus_suspend and see if it goes int s0ix Change-Id: I2332b0eb7a2f74e8178b95a23c8ac2091027a071 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/29872 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-11-30cpu/intel/common: Use a common acpi/cpu.asl fileArthur Heymans
Change-Id: Ifa5a3a22771ff2e0efa14fb765603fd5e0440d59 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/29894 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: David Guckian
2018-11-27mb/google/poppy/variants/nami: Enable g2touch touchscreen deviceCrystal Lin
This change adds ACPI properties for GTCH7503 device. BUG=b:119169362 BRANCH=firmware-nami-10775.B TEST=Verify touchscreen works with this change Change-Id: I26e16b7e118121b3dd9a88c76d04898b97753df0 Signed-off-by: Crystal Lin <crystal_lin@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/29768 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-23mb: Set coreboot as DSDT's manufacturer model IDElyes HAOUAS
Field 'OEMID' & "OEM Table ID" are related to DSDT table not to mainboard. So use macro to set them respectvely to "COREv4" and "COREBOOT". Change-Id: I060e07a730e721df4a86128ee89bfe168c69f31e Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/29790 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: David Guckian
2018-11-22mb/google/poppy/variant/nocturne: enable USB acpiNick Vaccaro
Main objective for this change is to export the bluetooth reset gpio to the kernel for use in an rf-kill operation. To do so, we enable USB acpi and define all of the USB2 devices, which includes bluetooth's reset gpio information. This change produces the following nodes in the SSDT : Scope (\_SB.PCI0.XHCI.RHUB.HS01) { Name (_DDN, "USB Type C Port 1") // _DDN: DOS Device Name Name (_UPC, Package (0x04) // _UPC: USB Port Capabilities { 0xFF, 0x09, Zero, Zero }) Name (_PLD, ToPLD ( PLD_Revision = 0x2, PLD_IgnoreColor = 0x1, PLD_Red = 0x0, PLD_Green = 0x0, PLD_Blue = 0x0, PLD_Width = 0x0, PLD_Height = 0x0, PLD_UserVisible = 0x1, PLD_Dock = 0x0, PLD_Lid = 0x0, PLD_Panel = "UNKNOWN", PLD_VerticalPosition = "CENTER", PLD_HorizontalPosition = "CENTER", PLD_Shape = "OVAL", PLD_GroupOrientation = 0x0, PLD_GroupToken = 0x0, PLD_GroupPosition = 0x0, PLD_Bay = 0x0, PLD_Ejectable = 0x0, PLD_EjectRequired = 0x0, PLD_CabinetNumber = 0x0, PLD_CardCageNumber = 0x0, PLD_Reference = 0x0, PLD_Rotation = 0x0, PLD_Order = 0x0, PLD_VerticalOffset = 0x0, PLD_HorizontalOffset = 0x0) ) // _PLD: Physical Location of Device } Scope (\_SB.PCI0.XHCI.RHUB.HS03) { Name (_DDN, "Bluetooth") // _DDN: DOS Device Name Name (_UPC, Package (0x04) // _UPC: USB Port Capabilities { 0xFF, 0xFF, Zero, Zero }) Name (_PLD, ToPLD ( PLD_Revision = 0x2, PLD_IgnoreColor = 0x1, PLD_Red = 0x0, PLD_Green = 0x0, PLD_Blue = 0x0, PLD_Width = 0x0, PLD_Height = 0x0, PLD_UserVisible = 0x0, PLD_Dock = 0x0, PLD_Lid = 0x0, PLD_Panel = "UNKNOWN", PLD_VerticalPosition = "CENTER", PLD_HorizontalPosition = "CENTER", PLD_Shape = "UNKNOWN", PLD_GroupOrientation = 0x0, PLD_GroupToken = 0x0, PLD_GroupPosition = 0x0, PLD_Bay = 0x0, PLD_Ejectable = 0x0, PLD_EjectRequired = 0x0, PLD_CabinetNumber = 0x0, PLD_CardCageNumber = 0x0, PLD_Reference = 0x0, PLD_Rotation = 0x0, PLD_Order = 0x0, PLD_VerticalOffset = 0x0, PLD_HorizontalOffset = 0x0) ) // _PLD: Physical Location of Device Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings { GpioIo (Exclusive, PullDefault, 0x0000, 0x0000, IoRestrictionOutputOnly, "\\_SB.PCI0.GPIO", 0x00, ResourceConsumer, , ) { // Pin list 0x0062 } }) Name (_DSD, Package (0x02) // _DSD: Device-Specific Data { ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301") /* Device Properties for _DSD */, Package (0x01) { Package (0x02) { "reset-gpio", Package (0x04) { \_SB.PCI0.XHCI.RHUB.HS03, Zero, Zero, One } } } }) } Scope (\_SB.PCI0.XHCI.RHUB.HS05) { Name (_DDN, "USB Type C Port 2") // _DDN: DOS Device Name Name (_UPC, Package (0x04) // _UPC: USB Port Capabilities { 0xFF, 0x09, Zero, Zero }) Name (_PLD, ToPLD ( PLD_Revision = 0x2, PLD_IgnoreColor = 0x1, PLD_Red = 0x0, PLD_Green = 0x0, PLD_Blue = 0x0, PLD_Width = 0x0, PLD_Height = 0x0, PLD_UserVisible = 0x1, PLD_Dock = 0x0, PLD_Lid = 0x0, PLD_Panel = "UNKNOWN", PLD_VerticalPosition = "CENTER", PLD_HorizontalPosition = "CENTER", PLD_Shape = "OVAL", PLD_GroupOrientation = 0x0, PLD_GroupToken = 0x0, PLD_GroupPosition = 0x0, PLD_Bay = 0x0, PLD_Ejectable = 0x0, PLD_EjectRequired = 0x0, PLD_CabinetNumber = 0x0, PLD_CardCageNumber = 0x0, PLD_Reference = 0x0, PLD_Rotation = 0x0, PLD_Order = 0x0, PLD_VerticalOffset = 0x0, PLD_HorizontalOffset = 0x0) ) // _PLD: Physical Location of Device } Scope (\_SB.PCI0.XHCI.RHUB.HS07) { Name (_DDN, "POGO") // _DDN: DOS Device Name Name (_UPC, Package (0x04) // _UPC: USB Port Capabilities { 0xFF, 0xFF, Zero, Zero }) Name (_PLD, ToPLD ( PLD_Revision = 0x2, PLD_IgnoreColor = 0x1, PLD_Red = 0x0, PLD_Green = 0x0, PLD_Blue = 0x0, PLD_Width = 0x0, PLD_Height = 0x0, PLD_UserVisible = 0x0, PLD_Dock = 0x0, PLD_Lid = 0x0, PLD_Panel = "UNKNOWN", PLD_VerticalPosition = "CENTER", PLD_HorizontalPosition = "CENTER", PLD_Shape = "UNKNOWN", PLD_GroupOrientation = 0x0, PLD_GroupToken = 0x0, PLD_GroupPosition = 0x0, PLD_Bay = 0x0, PLD_Ejectable = 0x0, PLD_EjectRequired = 0x0, PLD_CabinetNumber = 0x0, PLD_CardCageNumber = 0x0, PLD_Reference = 0x0, PLD_Rotation = 0x0, PLD_Order = 0x0, PLD_VerticalOffset = 0x0, PLD_HorizontalOffset = 0x0) ) // _PLD: Physical Location of Device } BUG=b:119275094 TEST=build and flash to nocturne, log into nocturne and 'cat /sys/firmware/acpi/tables/SSDT > /tmp/ssdt.dml', copy that ssdt.dsml to /tmp/ssdt.dml on host machine, 'iasl -d /tmp/ssdt.dml', then verify that "reset gpio" shows up in the HS03 node's _DSD package in the table. Change-Id: I65d9b580fd69fd0a2c84f14b78a8e8b5e9217b16 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/29622 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Rajat Jain <rajatja@google.com>
2018-11-22mb/google/poppy/variants/nami: Split FP MCU Wake and IRQ GPIOSShelley Chen
We are seeing problems (interrupt storm) with using the same gpio for FP MCU wake and irq signals. Reverting back to using separate gpios for wake and irq until we resolve the issue. BUG=b:119447525, b:115706071 BRANCH=Nami TEST=Run powerd_dbus_suspend from kernel and make sure see DUT drop into S0ix in the EC console. Also, unlock from lock screen with fingerprint. Change-Id: Id7987f28526256808b8ed49e66f66298f7cdbcee Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/29665 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Vincent Wang <vwang@google.com>
2018-11-21ACPI: Fix DSDT's revision fieldElyes HAOUAS
DSDT revision is =1 for ACPI v1 and =2 for greater ACPI version. This will cause the AML interpreter to use 32-bit integers and math if the version is 1, and 64-bit if the version is >=2. Current spec version is 2 for ACPI 6.2-a. Change-Id: I77372882d5c77b7ed52dcdd88028403df6f6fa7f Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/29626 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-17mb/google/poppy/variants/nami: Invert FP MCU wake signalShelley Chen
GPP_D6 needs to be inverted to enter S0ix because FPMCU_INT_L is active low. Keeps device awake otherwise. BUG=b:119447525, b:115706071 BRANCH=Nami TEST=Run powerd_dbus_suspend from kernel and make sure see DUT drop into S0ix in the EC console. Change-Id: Iad5df124e2439bbdc078d6a33f8d0510d25ecf6f Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/29650 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-16mb/google/poppy/variant/atlas: config GPP_F10 to use PLTRSTNick Vaccaro
GPIO's that use GPI_APIC setting with DEEP causes an IRQ storm after S3 resume. GPIOs that fire IRQs via IOAPIC need to get their logic reset over PLTRST to prevent IRQ storm after S3 resume and hence configuring GPP_F10 (HP_IRQ_GPIO) to use PLTRST. BUG=none TEST=none Change-Id: Idc6c42cb4dc6e8eb368d605c83f584f4c69077dc Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/29540 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: caveh jalali <caveh@chromium.org> Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-16mb/google/poppy/variant/atlas: I2C: run trackpad at 1MHzCaveh Jalali
With this change, coreboot thinks we're running at 1MHz: DW I2C bus 2 at 0xd1133000 (1000 KHz) Elan eKT3644 IC Specification (trackpad) requires: Low Time larger than 500ns (61 * 8.3ns = 506ns). High Time larger than 260ns (32 * 8.3ns = 265ns), Data Hold_time larger than 0ns. Start Condition Hold time larger than 250ns. Rise/Fall time of less than 120ns. HCNT controls both High Time and Start Condition Hold time. LCNT controls Low Time. SDA_HOLD controls Data Hold Time. P2 Atlas "Rise time" is 90ns and "Fall time" is 32ns and tuned using resistors on the board and must be considered when adjusting any of the parameters since these times are all measured at 30 or 70% of base and peak voltages (0v/1.8v). The eKT3644 requirements are met with LCNT=69, HCNT=33, SDA_HOLD=20 which yields the SCL at around 950KHz - suboptimal but compliant. Lower LCNT or HCNT results in "lost arbitration" errors or not complying with eKT3644 requirements. Verified by gaggery.tsai@intel.corp-partner.google.com. Scope shots posted here: https://b.corp.google.com/issues/78601949#comment177 BUG=b:78601949 BRANCH=none TEST=Farzam provided test points on track pad for SCL/SDA/GND. Waveforms measured with oscilloscope and screen shots attached to bug (comment #177, #155, #100). Operate trackpad/touchscreen Review dmesg (kernel) output for correct speed, parameters, and no errors (e.g. "lost arbitration" or "host controller timeout") Change-Id: Iaf42ba7b8818b7cd9c8dcc657823dac705659d38 Signed-off-by: Caveh Jalali <caveh@chromium.org> Signed-off-by: Grant Grundler <grundler@chromium.org> Tested-by: gaggery.tsai@intel.corp-partner.google.com Tested-by: grundler@chromium.org Reviewed-on: https://review.coreboot.org/29553 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Caveh Jalali <caveh@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Gaggery Tsai <gaggery.tsai@intel.com>
2018-11-16mb/google/poppy/variants/nautilus: Control GPP_D0 in 2nd SKU onlySeunghwan Kim
GPP_D0 is NC in 1st SKU board design, so we should control GPP_D0 for only 2nd SKU. BUG=none BRANCH=poppy TEST=emerge-nautilus coreboot Change-Id: Ifd85693c9155ed960f0c794d4b83fe8863b77134 Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com> Reviewed-on: https://review.coreboot.org/29631 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-11-16mb/google/poppy/variant/nocturne: Configure GPP_E1 for WLAN_WAKE_LNick Vaccaro
The GPP_E1 gpio was incorrectly being defined as a no-connect. Configure GPP_E1 for the WLAN_WAKE_L signal as per the schematic. BUG=b:119508897 TEST=Build and flash nocturne, boot nocturne and 1) Verify nocturne can successfully suspend/resume from S3 and S0ix. 2) Verify wake from wlan wakes device from S3 and S0ix. To do so, a) as root, execute "iw phy phy0 wowlan enable disconnect" on DUT b) connect DUT to mobile hotspot c) sleep device via "powerd_dbus_suspend" d) turn off hotspot, verify DUT wakes from S0ix e) enable hotspot again f) connect DUT to hotspot g) sleep DUT via "sudo echo mem > /sys/power/state" h) turn off hotspot, verify DUT wakes from S3 Change-Id: I4efb4f6d601e172ae4807901e3bd4c9954319f80 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/29630 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-11-15ec/google/chromeec/acpi: Rename EC_ENABLE_TABLET_EVENT configKarthikeyan Ramasubramanian
Rename EC_ENABLE_TABLET_EVENT config as EC_ENABLE_MULTIPLE_DPTF_PROFILES since it aligns with the use-case. BUG=b:118149364 BRANCH=None TEST=Ensured that the expected DPTF table are loaded in different modes (base attached/detached and clamshell/360-flipped) on Soraka and Nautilus. Change-Id: If147f1c79ceaaed00e17ec80ec6c912a8f7a8c2e Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/29261 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2018-11-15src/mainboard/google: Remove defining EC_ENABLE_TABLET_EVENT configKarthikeyan Ramasubramanian
Remove defining EC_ENABLE_TABLET_EVENT configuration from the boards where it is not required. BUG=b:118149364 BRANCH=None TEST=Build Change-Id: Iee70192916ac6c53bb27b7f73f3ad6d069afd030 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/29637 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-11-08mb/google/poppy/variant/nocturne: configure SAR irqs to use PLTRSTNick Vaccaro
GPIO's that use GPI_APIC setting with DEEP causes an IRQ storm after S3 resume. GPIOs that fire IRQs via IOAPIC need to get their logic reset over PLTRST to prevent IRQ storm after S3 resume and hence configuring GPP_D9 and GPP_D10 to use PLTRST. BUG=b:119202293 TEST=none Change-Id: I98d71100f28fb9bae05db3fb7d9afcb3f81beb43 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/29538 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-11-08mb/google/poppy/variant/nocturne: use PLTRST for GPP_C11Nick Vaccaro
GPP_C11 (FPMCU_INT_L) was set to DEEP, causing problems with S3. Changed GPP_C11 configuration to use PLTRST instead. BUG=b:114196791 TEST=Build, flash, boot nocturne, log in to kernel and execute the following two commands and verify it passes : echo 0 > /var/lib/power_manager/suspend_to_idle && restart powerd sudo suspend_stress_test -c 2 Change-Id: I008532fce963c51a435378001440ac72b5ebfffc Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/29429 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-11-08mb/google/poppy/variants/nami: add the hynix memory partsRen Kuo
add the memory parts as ram id 10: hynix_dimm_H5ANAG6NAFR-UHC BUG=b:113983573 BRANCH=Nami TEST=emerge-nami coreboot chromeos-bootimage Change-Id: I137259b88f39779768a58959a2dcc565645eee6d Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/29524 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-11-05mb/google/poppy/variants/nami: Enable FP MCUShelley Chen
Some variants of nami will have a fingerprint MCU. BUG=b:118503113 BRANCH=Nami TEST=None (build and boot, but no hw yet) Change-Id: I446dc09cdf7f84a801723cb403d2de80e0997c65 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/29297 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-11-05mb/google/poppy/variant/nocturne: add Nanya memory optionNick Vaccaro
Add option for Nanya NT6CL256T32CM-H1 part. Add comments to indicate total memory size for convenience. BUG=b:118624505 BRANCH=master TEST=none Change-Id: I82200e7b3d0a13295cb38f53ab576697ff8d302b Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/29341 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-11-02mb/google/poppy/variants/nami: Enable radium touchscreen supportRen Kuo
Enable the radium touchscreen support BUG=b:117960394 BRANCH=master TEST= 1. emerge-nami coreboot chromeos-bootimage 2. boot up on ekko DUT to check touchscreen device by evtest /dev/input/event3: Raydium Touchscreen Change-Id: I16167d5d3ce6eac9d64832b52bb1945999a63a90 Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/29365 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-31mb/google/poppy/variants/nami: Perform PL2 setting for syndraJohn Su
According to syndra thermal table, PL2 need to check cpu id. Set up syndra PL2 value. 1. KBL_U PL2 is 25w. 2. KBL_R PL2 is 29w. Refer to b:116836990#comment10. BUG=b:116836990 TEST=The thermal team verify OK Change-Id: I766a886121a089683565608252b4c176c70e88a3 Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/29269 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Shelley Chen <shchen@google.com>
2018-10-29mb/google/poppy/variants/nami: Add field to identify single channel DDRShelley Chen
Variants of Nami need to accommodate single channel DDR. Will use GPP_D10 on nami for identification. GPP_D10 will return 1 when device is using single channel DDR and 0 when using dual channel DDR. BUG=b:117194353 BRANCH=None TEST=dmidecode | grep Channel and make sure that the correct number of channels gets returned. Change-Id: If86ab2c5404c4e818ce496ea935227ab5e51730a Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/29233 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-24mb/google/poppy/var/nocturne: Use CRFP as device name for FP deviceFurquan Shaikh
This change uses CRFP ACPI name for FP device since user space utilities expect this name for triggering different actions. BUG=b:112974410 BRANCH=nocturne Change-Id: I63309227c916b43917e529c223cf738fc3baa209 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/29231 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-24mainboard/google/poppy/variants/rammus: Enable touchscreenkane_chen
On rammus, set GPIO GPP_C22 to 1 for touchscreen power on. And add touchscreen device "PNP0C50" to I2C0. According to touchscreen spec, device power on initialization takes 105 ms, so set "generic.enable_delay_ms" to 120. We found there is i2c error log pop up when we set delay time to be 110ms or 105ms. If we set delay time to be 120ms. System will not pop up i2c error log. BUG=b:115944726 BRANCH=master TEST=emerge-rammus coreboot chromeos-ec chromeos-bootimage Flash FW to DUT, and make sure touchscreen works. Change-Id: Ibce552d04991e85c99ae3a0a92455fc747d9fced Signed-off-by: YanRu Chen <kane_chen@pegatron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/28598 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Zhuohao Lee <zhuohao@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-10-23mb/google/poppy: add the smi_events backZhuohao Lee
Before entering the OS, the AP relies on the smi handler to shutdown the system when the lid closes. Without the smi_events setting, the AP will not receive the smi handler. As a result, the AP won't shutdown and will always keep in S0. This problem is caused by the https://review.coreboot.org/c/coreboot/+/28983 and this patch adds the smi_events back to support the smi handler for the lid close. BRANCH=master BUG=b:115572596 TEST=test_that -b ${BOARD} ${IP} firmware_ECLidShutdown Change-Id: Id82311a8ccd109f9c26516f59a45bdf34da98529 Signed-off-by: Zhuohao Lee <zhuohao@chromium.org> Reviewed-on: https://review.coreboot.org/29191 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2018-10-22mb/google/poppy/var/nocturne: Change IMX319 sensor link freqLijian Zhao
Change link frequency of IMX319 from 360Mhz to 482.4 Mhz to match the changes from kernel driver. IMX319 has two PLLs and it can be configured either single or dual. Previous driver implemente dual PLL mode, however image sensor vendor prefer single PLL mode and calculate the pixel rate became easier. So the kernel driver changed to use single pll, coreboot change will match that. Bug=b:116082248 Change-Id: Iac9a72253e0529bf2c0785fb701b7bc251bcbab5 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/28736 Reviewed-by: Tomasz Figa <tfiga@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Chiranjeevi Rapolu <chiranjeevi.rapolu@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-17mb/google/poppy/variants/nocturne: Disable pull-down of GPP_E9/E10Roy Mingi Park
While these pins were set to a pull-down 20KOhm, NPCX EC consumes ~2.1mW higher power. Becasue there was leakage current on both GPIO67 and GPIO70 from NPCX EC. With the external pull-up 10KOhm for USB_OC0#/USB2_OC1#, this wasn't enough to prevent leakage current. BUG=b:117139495 TEST=Check nxpc EC power to see power improvement Change-Id: I685d876461c263f07ca4c8f8046635cb7087279c Signed-off-by: Roy Mingi Park <roy.mingi.park@intel.com> Reviewed-on: https://review.coreboot.org/29007 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-10-17mb/google/poppy/variants/nocturne: Tune DPTF settings for CPUSumeet R Pawnikar
Update CPU passive temperature threshold value from 70C to 80C, to avoid early throttling for spiky workloads. Also, change CPU throttling interval from 1 sec to 5 sec for CPU temperature. BUG=b:116400298 BRANCH=None TEST=Manual performance testing on nocturne. Change-Id: Ic5031a4aa16f750237565f4e4928e78834b1d686 Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/29044 Reviewed-by: Puthikorn Voravootivat <puthik@chromium.org> Reviewed-by: Todd Broch <tbroch@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-15mb/google/poppy/variants/nami: Disable rear camera/DMIC for SyndraAmanda Huang
Since there are two cameras on Nami and only one camera on Syndra. We need to disable rear camera/DMIC on all Syndra sku. BUG=b:112876867 Change-Id: I92fb43ec84387c268ffdb6d0d34a5e5b13bcf50a Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/29022 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-10-15vc/google/chromeos/ec: remove EC hibernate in cr50 update pathAaron Durbin
More platforms are not able to hibernate under certain circumstances, such as when AC is plugged. This original path was conservatively put in to prevent potential damage when cr50-update-caused asynchronous resets occur. Julius' compelling argument that async resets from recovery mode requests should have enough coverage of the design over the course of project development. Remove the hibernate path and assume all is well going forward. Change-Id: I37121e75ff4e6abcb41d8534a1eccf0788ce2ea2 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/29076 Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-11mb/google/poppy/var/nocturne: Provide override for ec eventinfoFurquan Shaikh
This change implements the callback to provide google_chromeec_event_info structure in nocturne variant and sets MKBP SCI based on board id. BUG=b:112366846,b:112112483,b:112111610 Change-Id: Ifcc10aefc8f450214bd64dfffaf8854ada43f323 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/28984 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Enrico Granata <egranata@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-10-11mb/google/poppy: Allow variants to provide event info at runtimeFurquan Shaikh
This change adds a variant callback to read google_chromeec_event_info from variant at runtime to allow override of any events based on factors like board id. This callback is used in ramstage and smm to get google_chromeec_event_info structure for performing various actions like setting masks and logging wake events from EC. BUG=b:112366846,b:112112483,b:112111610 Change-Id: If89e904c92372530a0f555952f87702f068e0b03 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/28983 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Enrico Granata <egranata@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-10-10mb/google/poppy/variants/nami: Add samsung_dimm_K4AAG165WB-MCRC SPDChris Zhou
Add SPD file for sdp samsung_dimm_K4AAG165WB-MCRC (ram id: 9) BUG=b:112679174 TEST=emerge-nami coreboot chromeos-bootimage Change-Id: Iac1e3ca4b009cc9be94608cd342f535fa581a5eb Signed-off-by: Chris Zhou <chris_zhou@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/28974 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-08Move compiler.h to commonlibNico Huber
Its spreading copies got out of sync. And as it is not a standard header but used in commonlib code, it belongs into commonlib. While we are at it, always include it via GCC's `-include` switch. Some Windows and BSD quirk handling went into the util copies. We always guard from redefinitions now to prevent further issues. Change-Id: I850414e6db1d799dce71ff2dc044e6a000ad2552 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/28927 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-10-08mb/google/poppy/variant/nocturne: correct wifi wake registerNick Vaccaro
Wifi wake register is incorrectly set in devicetree. Set wifi wake to its correct wake source, GPE0_DW2_01. BUG=b:117330593 TEST='emerge-nocturne coreboot chromeos-bootimage', flash nocture, connect wifi to a hotspot, suspend device, echo freeze > /sys/power/state, and then shutdown the hotspot and verify device wakes. Change-Id: Iafa865ca79d33541d7f47b69d2fb209e7f9c98af Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/28938 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-08mb/google/poppy/variant/nocturne: Disable WAKE# signalNick Vaccaro
The WAKE# signal has moved to LAN_WAKE, so WAKE# is now floating and must be disabled. This change disables WAKE#. BUG=b:117284700 TEST=none Change-Id: I1c25e4ba28cd2b8807cd155d47c29c0d3ee9e8a5 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/28926 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-10-06mb/google/poppy/variants/nocturne: Add DMIC properties to ACPI DSDFurquan Shaikh
This change uses the generic device driver to provide DMIC properties in ACPI table to the OS driver. BUG=b:112888584 Change-Id: I239f571bc29f02793f017a4713b5af03b23cfa3e Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/28797 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: HARSHAPRIYA N <harshapriya.n@intel.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-05mb/google/poppy/variants/nautilus: Change SlowSlewRate settings for LTE skuSeunghwan Kim
Nautilus-LTE sku shows abnormal reset symptom at high temperature chamber test, but the root cause is unclear. Experimentally, setting SlowSlewRate IA/GT/SA to 1/2 improves this abnormal reset issue, so we would apply it until find root cause of this issue. BUG=b:117130599 BRANCH=poppy TEST=Built and passed on reliability test with modified coreboot Change-Id: I7fa0041989113097e3b283dbcf4ca2a73629fe54 Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com> Reviewed-on: https://review.coreboot.org/28785 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-05atlas: control touchscreen power using ACPICaveh Jalali
This adds the ACPI controls for power sequencing the touchscreen. The initial setting is to keep the touchscreen powered off and in reset. When linux is ready to talk to the touchscreen, it powers it on and releases reset via ACPI. BUG=b:110286344 TEST=verified touchscreen is functional in chromeos Change-Id: I58c42a8f09342cfe54f82ef0e6cd8ea72a5140dc Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://review.coreboot.org/28869 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-04mb/google/poppy/variant/nocturne: update GPIO configurationNick Vaccaro
GPP_C19 is not being set as the code is incorrectly setting GPP_C16 instead, causing SAR sensor not to work, so this change sets GPP_C19 to NF1. GPP_E3 is not being initialized in the code. Initialize GPP_E3 to a no connect as documented in the board schematic. BUG=b:117124878 TEST: 'emerge-coreboot chromeos-bootimage', flash nocturne and verify that i2c transactions work for the left SAR sensor. Change-Id: I9e972dbe4214cdd15d80d63dfa058e7755f7ecbb Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/28867 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-04mb/google/poppy/variant/nocturne: increase touchscreen reset delayNick Vaccaro
Increase the reset delay for the touchscreen to 10 ms. BUG=b:116857433 TEST='emerge-nocturne coreboot chromeos-bootimage', flash and boot nocturne to kernel, log in and execute the following two commands: echo "i2c-WCOM50C1:00" > /sys/bus/i2c/drivers/i2c_hid/unbind echo "i2c-WCOM50C1:00" > /sys/bus/i2c/drivers/i2c_hid/bind and verify the bind command does not echo back a "-bash: echo: write error: No such device" error. Change-Id: I102b57ea5a10d22bee6d4f7c6f114b380a5d586b Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/28803 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Caveh Jalali <caveh@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-04mb/google/poppy/variants/rammus: Shorten oem_table_id to RAMMUSmarxwang
This patch modifies "oem_table_id" from "RAMMUSMAX" to "RAMMUS" so that the audio topology file can be loaded properly by the operating system. BUG=b:112945714 BRANCH=master TEST=There is no error message like "failed to load topology firmware" in kernel v4.4 log. Change-Id: I66a38ea38791dd3d9606a05b7b696236c350237f Signed-off-by: Marx Wang <marx.wang@intel.com> Reviewed-on: https://review.coreboot.org/28870 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-10-04mb/google/nocturne: Define GPP_D17 as EC_SYNC_IRQDuncan Laurie
Use GPIO GPP_D17 pin as the EC sync interrupt and provide this value to the embedded controller to be exported to the OS. This interface was tested on a reworked Nocturne board with modified EC and a modified kernel driver to ensure that the interrupt asserts as expected and can be used by the kernel driver. Change-Id: Ie2b33692367b5d9ecc2b128180d8cfe4f6b347b1 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/28759 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-09-28mainboard/google/poppy/variants/rammus: Modify VR settingstatham_chu
We refer to Intel Doc#594883. The recommended Ac/Dc loadline values are as below: # VR Settings Configuration for 4 Domains #+----------------+-------+-------+-------+-------+ #| Domain/Setting | SA | IA | GTUS | GTS | #+----------------+-------+-------+-------+-------+ #| Psi1Threshold | 20A | 20A | 20A | 20A | #| Psi2Threshold | 2A | 2A | 2A | 2A | #| Psi3Threshold | 1A | 1A | 1A | 1A | #| Psi3Enable | 1 | 1 | 1 | 1 | #| Psi4Enable | 1 | 1 | 1 | 1 | #| ImonSlope | 0 | 0 | 0 | 0 | #| ImonOffset | 0 | 0 | 0 | 0 | #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | #| AcLoadline | 14.4 | 4.2 | 5.7 | 4.47 | #| DcLoadline | 14.0 | 4.17 | 4.2 | 4.3 | #+----------------+-------+-------+-------+-------+ BUG=b:112167318 BRANCH=master TEST=emerge-rammus coreboot chromeos-ec chromeos-bootimage Flash FW to DUT, and make sure system boots up. Change-Id: I2d83d835ec841ac4cc811a0a69f74d203d5ea173 Signed-off-by: statham_chu <statham_chu@pegatron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/28695 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-09-26mb/google/poppy/variants/nocturne: Update PowerLimit1 maximum valueSumeet Pawnikar
Increase power limit1 maximum value from 5W to 7W. This value as per recent measurement on closed system which shows better performance results. BUG=None TEST=Build and tested on Nocturne system. Performance tests show better results. Change-Id: I7485b1d2afde46ec28d548c13be35a43e7572918 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/28686 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Puthikorn Voravootivat <puthik@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-09-26mb/google/poppy/variants/nocturne: Add tdp_pl1_override valueSumeet Pawnikar
Add tdp_pl1_override value as 7W. BUG=None BRANCH=None TEST=Build coreboot for Nocturne board Change-Id: I16d3894da68bc3be6eff526062f9a88ef2df60c7 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/28708 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Puthikorn Voravootivat <puthik@chromium.org>
2018-09-26mb/google/poppy/variants/nocturne: Update DPTF settingsPuthikorn Voravootivat
The previous does not work well enough when testing with high ambient temperature. Update DPTF settings to make it work better. List of tweaks: 1. Raise DRAM Critical temperature from 48C to 55C Note that there are mechanisms in EC that complement this because of DPTF limitation that we can't have multiple passive temperatures. 2. Lower response time for DRAM temp sensor from 60s to 5s. 3. Increase throttle priority to the charger when DRAM hit passive temperature from 100 to 200. BUG=b:112550414 BRANCH=None TEST=Manually tested by thermal team. Change-Id: Idf7efa76b2c6085cf97aa9f65c6ce066e8cff99a Signed-off-by: Puthikorn Voravootivat <puthik@chromium.org> Reviewed-on: https://review.coreboot.org/28738 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-26Revert "mb/google/poppy/variants/nautilus: Set grip sensor threshold"Seunghwan Kim
This reverts commit aef592d9b66aa18d83b0a211ead26013ff1f7d98. Reason for revert: Use values from driver instead of hardcoding in firmware (b:113303916) Change-Id: I02d21803f38da227f1d85b00cb6b5274d81dbbb4 Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com> Reviewed-on: https://review.coreboot.org/28690 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Enrico Granata <egranata@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-21mb/google/poppy/variants/rammus: Disable command TriState for rammusmarxwang
This patch sets the MRC UPD "CmdTriStateDis" to disable TriState for the rammus boards. Rammus is LPDDR3 design without RTT for CMD/CTRL. BUG=none TEST=Run memtester app and also webgl fishtank on the LPDDR3 kabylake boards and also check the margin data is proper in FSP. Change-Id: Iee115f49ba5b36dc5b0425e9da02b58cd19b2236 Signed-off-by: Marx Wang <marx.wang@intel.com> Reviewed-on: https://review.coreboot.org/28568 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-21mb/google/poppy/variant/nocturne: set DMIC1 to NCNick Vaccaro
Change GPP_D17 and GPP_D18 to no connects as DMIC was moved to DMIC0. BUG=b:113744731,b:111106010 TEST=none Change-Id: I8ef42627e542182707c81389af9da33a114bc184 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/28689 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-20mb/google/poppy/variants/nocturne: Update DPTF settingsPuthikorn Voravootivat
Update DPTF settings based on recommendation from thermal team. BUG=b:112550414 BRANCH=None TEST=Manually tested by thermal team. Change-Id: I26f09392a3293ce4b3481f2be341a667d606bc10 Signed-off-by: Puthikorn Voravootivat <puthik@chromium.org> Reviewed-on: https://review.coreboot.org/28666 Reviewed-by: Todd Broch <tbroch@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-16mb/google/poppy/variants/rammus: fix S0ix entering issueZhuohao Lee
As we don't use the MIPI camera on Rammus, disable SA Imaging Unit and CIO2 devices to avoid the system failed to enter S0ix. BUG=b:114502527 BRANCH=master TEST=On DUT, echo freeze > /sys/power/state 1. check the S0ix status on EC console 2. check the value of /sys/kernel/debug/pmc_core/slp_s0_residency_usec Change-Id: I91629732db01ee534f0ddb67a2b358d725ef810e Signed-off-by: Zhuohao Lee <zhuohao@chromium.org> Reviewed-on: https://review.coreboot.org/28543 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-09-16mb/google/poppy: Set UPD CmdTriStateDis for AtlasCaveh Jalali
This patch sets the MRC UPD CmdTriStateDis for the atlas boards. Atlas is a LPDDR3 design without RTT for CMD/CTRL. The original change for nocturne is I0f593761dcbd121e7e758421af178931b9d78295 mb/google/poppy: Set UPD CmdTriStateDis for Nocturne BUG=b:111812662 Change-Id: I45b6dd22412c689c8db64f4650e9fa9e87dec2ec Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://review.coreboot.org/28540 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2018-09-12mainboards: Add SMMSTORE region in chromeos configsPatrick Georgi
Only for those that are x86 and also have a RW_LEGACY region. The assumption is that all devices touched have 64k block sizes when choosing size and alignment of the region. Change-Id: I12addb137604f003d1296f34f555dae219330b18 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/28532 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-09-12rammus: add SPD mapping for rammus and shyvana supportkane_chen
Add MICRO 4G and 8G SPD file. BUG=none BRANCH=master TEST=emerge-rammus coreboot chromeos-ec chromeos-bootimage Flash FW to DUT, and make sure system boots up. Change-Id: I7cb5b7f2bcdc6fbe0cbc640cad4af014f1a0edd6 Signed-off-by: YanRu Chen <kane_chen@pegatron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/28484 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-10mb/google/poppy/variants/nami: Add SPD for two memory partsRen Kuo
add two memory parts and ram id: hynix_dimm_H5ANAG6NCMR-VKC micron_dimm_MT40A1G16KNR-075E BUG=b:113983573 BRANCH=Nami TEST=emerge-nami coreboot chromeos-bootimage Change-Id: Ia052f16b6c1e64ee6458fbdeea56a482a728c35a Signed-off-by: Ren Kuo <Ren.Kuo@quantatw.com> Reviewed-on: https://review.coreboot.org/28536 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-10mainboard/google/poppy/variants/rammus: Enable DA7219marxwang
On rammus, headset uses DA7219 so that we need to enable it. BUG=b:112945714 BRANCH=master TEST=emerge-rammus coreboot chromeos-bootimage Flash FW and check in kernel to see if DA7219 is up. Change-Id: I92dd412374d007aab264661e698fbbbbcf1eae45 Signed-off-by: marxwang <marx.wang@intel.com> Reviewed-on: https://review.coreboot.org/28537 Reviewed-by: Zhuohao Lee <zhuohao@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-10mb/google/poppy: Set UPD CmdTriStateDis for NocturneShaunak Saha
This patch sets the MRC UPD CmdTriStateDis for the nocturne boards.Nocturne is LPDDR3 design without RTT for CMD/CTRL. BUG=b:111812662 TEST=Run memtester app and also webgl fishtank on the LPDDR3 kabylake boards and also check the margin data is proper in FSP. Change-Id: I0f593761dcbd121e7e758421af178931b9d78295 Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/28379 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-07mb/google/poppy/variants/atlas: enable NVMeCaveh Jalali
This adds support for a x2 NVMe device on PCIe bus PCIe lines 5+6 and clock#4. BUG=b:113369699 TEST=booted on atlas Change-Id: I08e7c4d65662ddbb7d936915c896eb1fcb240ba8 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://review.coreboot.org/28535 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-09-06mainboard/google/poppy/variants/rammus: Enable GSPI clock for bus 0.kane_chen
On rammus, system halt was observed because of gspi clk value being set to 0. Log info from serial coreboot: FMAP: area RW_NVRAM found @ 9fa000 (24576 bytes) SF: Detected FAST_SPI Hardware Sequencer with sector size 0x1000, total 0x1000000 VBNV: Restore from flash failed ASSERTION ERROR: file 'src/soc/intel/common/block/gspi/gspi.c', line 443 gspi.c 442 443 assert(gspi_clk_mhz != 0); 444 assert(ref_clk_mhz != 0); 445 return (DIV_ROUND_UP(ref_clk_mhz, gspi_clk_mhz) - 1) & SSCR0_SCR_MASK; BUG=none BRANCH=master TEST=emerge-rammus coreboot chromeos-ec chromeos-bootimage Flash FW to DUT, and make sure system boots up. Change-Id: Ibe3937902901b2cdc1a196415c08fabb0f3155f2 Signed-off-by: YanRu Chen <kane_chen@pegatron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/28405 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-06mb/google/poppy/variants/nocturne: Enable DMIC CLK0/DATA0Sathyanarayana Nujella
DMIC's are now connected to DMIC_CLK0/DMIC_DATA0. So, enable the pins accordingly. BUG=b:113744731,b:111106010 BRANCH=none TEST='emerge-nocturne coreboot chromeos-bootimage' builds the image Change-Id: I48cace3c6099a2853fcb377c695a5e325094baf6 Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com> Signed-off-by: Harsha Priya <harshapriya.n@intel.com> Reviewed-on: https://review.coreboot.org/28433 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-09-06mb/google/poppy/variants/nautilus: Bump VCC_SA voltage offset 75mVSeunghwan Kim
Nautilus-Wifi with m3 AP got a halt issue during CTS test. Nautilus-Wifi was FCS with Celeron AP first and also its PCB/BOM was validated only with Celeron. Since Celeron deos not support turbo boost mode, its steady power demend and lower CPU frequency may not reflect the potential noise hidden inside the board. Bumping VCC_SA voltage offset 75mV confirmed works to mitigate the potential noise coupling to VCC_GT/SA, and we verified this change makes this issue go away on Nautilus-Wifi board. Nautilus-LTE doesn't show this issue, since it has 10L PCB, will have better grounding and less noise/ripple than 8L PCB. BUG=b:111417632 BRANCH=poppy TEST=Verified CTS test pass without an issue. Change-Id: Id13fcc36a5b6ed42620c66f57a7303f30bff1a50 Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com> Reviewed-on: https://review.coreboot.org/28439 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-09-04mb/google/poppy/variants/rammus: add sku info into smbios tableZhuohao Lee
This patch adds the mainboard.c in order to support the sku id in smbios table where the sku id is queried from the eeprom via EC. BUG=b:113714761 BRANCH=master TEST=check the result of 'dmidecode' Change-Id: I3413784cca1ac10a2468d84f2d06c0e1d701fdcb Signed-off-by: Zhuohao Lee <zhuohao@chromium.org> Reviewed-on: https://review.coreboot.org/28426 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-09-02mb/google/poppy/Kconfig: Fix missing device node /dev/tpm0 for H1Zhuohao Lee
This patch adds the DRIVERS_SPI_ACPI to enable the tpm device node. Without DRIVERS_SPI_ACPI, the kernel will popped out the below error: cr50-update[592]: Starting cr50 update cr50_get_name[595]: updater is /usr/sbin/gsctool -s cr50-update[609]: exit status: 3 cr50-update[613]: output: Could not open TPM: No such file or directory cr50_get_name[615]: board_id: '' board_flags: '0x', extension: 'prod' cr50-update[617]: hashing /opt/google/cr50/firmware/cr50.bin.prod cr50-update[678]: current state 3 in /var/cache/cr50.a3055efbc9.state cr50-update[682]: not running cr50-result[782]: Not running normal image. Skip setting Board ID trunksd[795]: TPM: Error opening tpm0 file descriptor at /dev/tpm0: No such file or directory BUG=none BRANCH=master TEST=/dev/tpm0 is created Change-Id: I35287c6c54299c2677c41fc830675570b9d45a94 Signed-off-by: Zhuohao Lee <zhuohao@chromium.org> Reviewed-on: https://review.coreboot.org/28400 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-08-30mb/google/poppy/variants/nautilus: Set grip sensor thresholdSeunghwan Kim
Set threshold parameter for grip sensor STH9321 .ProxCtrl6: 75 .ProxCtrl7: 99 BUG=b:113303916 BRANCH=poppy TEST=Built and verified parameter passed to driver Change-Id: I8a410a23b5e3831fc8e90118b810fc2409a026eb Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com> Reviewed-on: https://review.coreboot.org/28381 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Enrico Granata <egranata@chromium.org>
2018-08-27mb/google/poppy/variants/atlas: Update DPTF parametersTodd Broch
Reduce the CPU passive threshold sample rate from 5 seconds to 1 second so DPTF will react faster to rapid temperature increases. Signed-off-by: Todd Broch <tbroch@chromium.org> BUG=b:113101335 BRANCH=atlas TEST=manual performance/power testing on nocturne. No longer see messages like below in syslog, 'CPU0: Package temperature above threshold' Change-Id: I2dc9d157b54500bae29e123978bb8ad6e05ef619 Reviewed-on: https://review.coreboot.org/28325 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-27mb/google/poppy/variants/nocturne: Update DPTF parametersTodd Broch
Reduce the CPU passive threshold sample rate from 5 seconds to 1 second so DPTF will react faster to rapid temperature increases. Signed-off-by: Todd Broch <tbroch@chromium.org> BUG=b:67459049 BRANCH=nocturne TEST=manual performance/power testing on nocturne. No longer see messages like below in syslog, 'CPU3: Package temperature above threshold' Change-Id: Ic20c718fd3a496db7c7192feec4f230d924cc458 Reviewed-on: https://review.coreboot.org/28324 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-23mb/google/poppy/variants/nocturne: enable "Base Attached Switch" deviceDmitry Torokhov
This enables CBAS device on Nocturne to allow hid-google-whisker driver in kernel properly detect device configuration. Change-Id: I5905a2de208e94062f2768a9b7d22147f85c7f38 Signed-off-by: Dmitry Torokhov <dtor@chromium.org> Reviewed-on: https://review.coreboot.org/28262 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-20atlas: enable keyboard backlight supportCaveh Jalali
This adds support for controlling the keyboard backlight over ACPI. BUG=b:112619894 BRANCH=none TEST=verified keyboard backlight can be adjusted using keyboard shortcuts Change-Id: I25713f341e8b5a4e50903ac109bfa717f20969d8 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://review.coreboot.org/28205 Reviewed-by: Caveh Jalali <caveh@google.com> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-20mb/google/poppy/variants/nocturne: enable eistMatt Delco
Enable Enhanced Intel SpeedStep (EIST) on nocturne. Change-Id: Ie9b832f5bc3a5ef300783bd9bcd7cf5d186b98fa Signed-off-by: Matt Delco <delco@chromium.org> Reviewed-on: https://review.coreboot.org/28103 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-08-20nocturne: Enable debouncing of SX9310 CLOSE / FAR IRQsEnrico Granata
This is meant to solve an issue where the proximity sensor may fluctuate between CLOSE / FAR in rapid succession upon the user removing their hand from the unit, before settling on the correct output. Using the hardware debouncing filter solves this issue and removes the spurious fluctuations. BRANCH=None BUG=None TEST=manual on Nocturne, observing events come in Change-Id: I78cc4852d42fcda6209fedce1ce91236b5814571 Signed-off-by: Enrico Granata <egranata@chromium.org> Reviewed-on: https://review.coreboot.org/28112 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-17Nami: Disable powering off EC on cr50 updateDaisuke Nojiri
Nami doesn't support wakeup from hibernation by CR50. This causes the device to remain turned off after CR50 update. This patch disables turning off EC on cr50 update. CR50 resets the whole system. So, EC reset is not required. Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> BUG=b:112604277 BRANCH=none TEST=gsctool -a -u /media/removable/cr50.bin && reboot Verify EC reboots. AP prints 'Waiting for CR50 reset to pick up update' then reboots. Change-Id: I06f5eb6100e8af6ffec45d4de2b40eff44f89709 Reviewed-on: https://review.coreboot.org/28113 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-15mb/google/poppy/variants/nocturne: remove dup'ed dptf_enableMatt Delco
This file contains two instances of "dptf_enable" = "1". This change removes the 2nd instance (it doesn't have an explicit comment like the 1st instance). The dptf devices still seem to be present even with this change, as expected. Change-Id: I890006644be9176ebaf555cc121c816e12f2b596 Signed-off-by: Matt Delco <delco@chromium.org> Reviewed-on: https://review.coreboot.org/28076 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-08-15mb/google/poppy/variants/nocturne: sx9310 to 400kbMatt Delco
The spec of the sx9310 says the I2C interface can handle standard (100kb/s) and fast mode (400kb/s). The current setting is using fast plus (1000kb/s) so this change is reducing the speed to fast mode. I've been using the sensors with this change for a few weeks now, though I also don't recall seeing an issue prior to this change. Change-Id: I337fc02c52565d6ec4d7bac1b3564f65238962dc Signed-off-by: Matt Delco <delco@chromium.org> Reviewed-on: https://review.coreboot.org/28075 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-08-15Revert "mb/google/poppy/variants/atlas: enable camera power and release reset"Caveh Jalali
This reverts commit 1fdb76945a9d06bbff37dee9da69e13a86c933f4. Camera power is now handled by ACPI rules - no need to force the GPIOs on by default. BUG=b:80106316,b:111141128 Change-Id: Ifefec320884989f106a4b09c956d3a3279a1491a Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://review.coreboot.org/28072 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Ping-chung Chen <ping-chung.chen@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-15mb/google/atlas: Add DISPLAY_DCR_EN GPIO pinCaveh Jalali
This defines new GPIO pin for controlling the display panel CABC function. The default value is high (enabled). BUG=b:112154569 Change-Id: I29083ab18e37f929a55b450b143463c67fe0abea Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://review.coreboot.org/28070 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-15mb/google/atlas: Update DPTF sensor namesCaveh Jalali
This updates the DPTF sensor names to reflect the sensor locations on the board. BUG=b:75454415 TEST=verified new strings show up in /sys/devices/LNXSYSTM:00/LNXSYBUS:00/INT3400:00/*/description Change-Id: Ibffe6cb361de212ca03e75deaa8c454546d267a5 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://review.coreboot.org/28069 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-14mb/google/poppy/variants/nocturne: Update PL1/PL2 for AMLRoy Mingi Park
This patch updates Power Limit (PL) for AML. - PL1 as 5W TDP as POR - PL2 as 18W TDP as POR BUG=None BRANCH=None TEST=Build coreboot for Nocturne board and check default PL1/PL2 TDP. cat /sys/class/powercap/intel-rapl/intel-rapl\:0/constraint_0_power 5000000 (5W TDP) cat /sys/class/powercap/intel-rapl/intel-rapl\:0/constraint_1_power 18000000 (18W TDP) Change-Id: Icb02a8a7c5fcd5e6aee45f14eba540a6b3ed3d67 Signed-off-by: Roy Mingi Park <roy.mingi.park@intel.com> Reviewed-on: https://review.coreboot.org/27427 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>