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This patch ensures skylake soc is using common thermal code
from intel common block.
TEST=Build and boot soraka
Change-Id: I0812daa3536051918ccac973fde8d7f4f949609d
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34648
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add hynix_dimm_H9CCNNNCLGALAR-NVD for new onboard memory support.
BUG=b:130337306
BRANCH=firmware-rammus-11275.B
TEST=emerge-rammus coreboot chromeos-ec chromeos-bootimage
Flash FW to DUT, and make sure system boots up.
Signed-off-by: YanRu Chen <kane_chen@pegatron.corp-partner.google.com>
Change-Id: Ibd02953d0c6ac62fa4d7751fd8b103b74433aa73
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32674
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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The InternalGfx option in devicetree.cb is not used to enable iGPU.
The patch removes this option from chip.h and mb/*/devicetree.cb
files for all boards with skl/kbl processor.
Change-Id: I41ecca3fdfb1d4b20ee634a13263ff481dcf440e
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32171
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Add micron_dimm_MT52L256M32D1PF-107 for new onboard memory support.
BUG=none
BRANCH=firmware-rammus-11275.B
TEST=emerge-rammus coreboot chromeos-ec chromeos-bootimage
Flash FW to DUT, and make sure system boots up.
Signed-off-by: YanRu Chen <kane_chen@pegatron.corp-partner.google.com>
Change-Id: Iaec4147a64313dcd461affb492805c0453e8703d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32046
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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We were used to set the same values in the system and board tables.
We'll keep the mainboard values as defaults for the system tables,
so nothing changes unless somebody overrides the system table hooks.
Change-Id: I3c9c95a1307529c3137647a161a698a4c3daa0ae
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/29477
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
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We had two ways to configure the serial IRQ mode. One time in the
devicetree for FSP and one time through Kconfig for coreboot. We'll
use `enum serirq_mode` from soc/intel/common/ as a devicetree option
instead. As the default is `quiet mode` here and that is the most
common mode, this saves us a lot of lines.
In four cases kblrvp8, 11 and librem 13v2, 15v3, we had conflicting
settings in devicetree and Kconfig. We'll maintain the `continuous`
selection, although it might be that coreboot overrode this earlier
on the kblrvps.
Note: A lot of Google boards have serial IRQ enabled, while the pin
seems to be unconnected?
Change-Id: I79f0cd302e335d8dcf8bf6bc32f3d40ca6713e5c
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/31596
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Use the common VMX implementation, and set IA32_FEATURE_CONTROL
lock bit per Kconfig *after* SGX is configured (as SGX also sets
bits on the IA32_FEATURE_CONTROL register).
As it is now correctly based on a Kconfig, the `VmxEnable` devicetree
setting vanishes.
Test: build/boot google/[chell,fizz], observe Virtualization enabled
under Windows 10 when VMX enabled and lock bit set.
Change-Id: Iea598cf74ba542a650433719f29cb5c9df700c0f
Signed-off-by: Nico Huber <nico.h@gmx.de>
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/29682
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This change enables mode change as a wake source for S3 and S0ix.
Change-Id: I2e7f9997776b1e024ea417eb69e6c2ffa8c62580
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/31296
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Main objective for this change is to export the bluetooth reset
gpio to the kernel for use in an rf-kill operation.
To do so, we enable USB acpi and define all of the USB2 devices,
which includes bluetooth's reset gpio information.
BUG=b:119899987
TEST=build and flash to rammus, log into rammus and
'cat /sys/firmware/acpi/tables/SSDT > /tmp/ssdt.dml', copy
that ssdt.dsml to /tmp/ssdt.dml on host machine,
'iasl -d /tmp/ssdt.dml', then verify that "reset gpio"
shows up in the HS03 node's _DSD package in the table.
Signed-off-by: marxwang <marx.wang@intel.com>
Change-Id: Ieadb3609c7634a20e96c7c4dfb96f5e3f23e468b
Reviewed-on: https://review.coreboot.org/c/30607
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
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According to issue tracker b:119238959 #4 & #6.
Hardware modify design to make GPP_E3 to be a switch of touchscreen
I2C CLK and SDA.
Control GPP_E3 to make touchscreen I2C CLK and SDA keep low during
power on initialization to avoid data transfer during this time.
After touchscreen IC initial complete, control GPP_E3 to high to
make touchscreen I2C CLK and SDA work normally.
Depending on touchscreen IC specification, device take 105ms for
power on initialization.
Change delay time from 120ms to 105ms.
BUG=b:119238959
BRANCH=firmware-rammus-11275.B
TEST=emerge-rammus coreboot chromeos-ec chromeos-bootimage
Flash FW to DUT, run S5 stress test and verify the result
Signed-off-by: YanRu Chen <kane_chen@pegatron.corp-partner.google.com>
Change-Id: I86452c1445243c499aeaf931dba286db169c5628
Reviewed-on: https://review.coreboot.org/c/30180
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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According to issue tracker b:119899090.
https://partnerissuetracker.corp.google.com/issues/119899090
We modify rammus devicetree.cb .i2c[1] configuration to meet ELAN touchpad I2C special timing requirement.
BUG=b:119899090
BRANCH=firmware-rammus-11275.B
TEST=emerge-rammus coreboot chromeos-ec chromeos-bootimage
Flash FW to DUT, and check touchpad I2C characteristics meet requirement
Signed-off-by: YanRu chen <kane_chen@pegatron.corp-partner.google.com>
Change-Id: Ifeb08c2530e6a7674f23f7d48cefa16cfc59cb13
Reviewed-on: https://review.coreboot.org/c/29922
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Remove defining EC_ENABLE_TABLET_EVENT configuration from the boards where
it is not required.
BUG=b:118149364
BRANCH=None
TEST=Build
Change-Id: Iee70192916ac6c53bb27b7f73f3ad6d069afd030
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/29637
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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On rammus, set GPIO GPP_C22 to 1 for touchscreen power on.
And add touchscreen device "PNP0C50" to I2C0.
According to touchscreen spec, device power on initialization takes
105 ms, so set "generic.enable_delay_ms" to 120.
We found there is i2c error log pop up when we set delay
time to be 110ms or 105ms. If we set delay time to be
120ms. System will not pop up i2c error log.
BUG=b:115944726
BRANCH=master
TEST=emerge-rammus coreboot chromeos-ec chromeos-bootimage
Flash FW to DUT, and make sure touchscreen works.
Change-Id: Ibce552d04991e85c99ae3a0a92455fc747d9fced
Signed-off-by: YanRu Chen <kane_chen@pegatron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/28598
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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This patch modifies "oem_table_id" from "RAMMUSMAX" to "RAMMUS"
so that the audio topology file can be loaded properly by the
operating system.
BUG=b:112945714
BRANCH=master
TEST=There is no error message like "failed to load topology firmware" in
kernel v4.4 log.
Change-Id: I66a38ea38791dd3d9606a05b7b696236c350237f
Signed-off-by: Marx Wang <marx.wang@intel.com>
Reviewed-on: https://review.coreboot.org/28870
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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We refer to Intel Doc#594883.
The recommended Ac/Dc loadline values are as below:
# VR Settings Configuration for 4 Domains
#+----------------+-------+-------+-------+-------+
#| Domain/Setting | SA | IA | GTUS | GTS |
#+----------------+-------+-------+-------+-------+
#| Psi1Threshold | 20A | 20A | 20A | 20A |
#| Psi2Threshold | 2A | 2A | 2A | 2A |
#| Psi3Threshold | 1A | 1A | 1A | 1A |
#| Psi3Enable | 1 | 1 | 1 | 1 |
#| Psi4Enable | 1 | 1 | 1 | 1 |
#| ImonSlope | 0 | 0 | 0 | 0 |
#| ImonOffset | 0 | 0 | 0 | 0 |
#| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V |
#| AcLoadline | 14.4 | 4.2 | 5.7 | 4.47 |
#| DcLoadline | 14.0 | 4.17 | 4.2 | 4.3 |
#+----------------+-------+-------+-------+-------+
BUG=b:112167318
BRANCH=master
TEST=emerge-rammus coreboot chromeos-ec chromeos-bootimage
Flash FW to DUT, and make sure system boots up.
Change-Id: I2d83d835ec841ac4cc811a0a69f74d203d5ea173
Signed-off-by: statham_chu <statham_chu@pegatron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/28695
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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This patch sets the MRC UPD "CmdTriStateDis" to disable TriState for
the rammus boards. Rammus is LPDDR3 design without RTT for CMD/CTRL.
BUG=none
TEST=Run memtester app and also webgl fishtank on the LPDDR3 kabylake
boards and also check the margin data is proper in FSP.
Change-Id: Iee115f49ba5b36dc5b0425e9da02b58cd19b2236
Signed-off-by: Marx Wang <marx.wang@intel.com>
Reviewed-on: https://review.coreboot.org/28568
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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As we don't use the MIPI camera on Rammus, disable SA Imaging Unit and
CIO2 devices to avoid the system failed to enter S0ix.
BUG=b:114502527
BRANCH=master
TEST=On DUT, echo freeze > /sys/power/state
1. check the S0ix status on EC console
2. check the value of /sys/kernel/debug/pmc_core/slp_s0_residency_usec
Change-Id: I91629732db01ee534f0ddb67a2b358d725ef810e
Signed-off-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-on: https://review.coreboot.org/28543
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Add MICRO 4G and 8G SPD file.
BUG=none
BRANCH=master
TEST=emerge-rammus coreboot chromeos-ec chromeos-bootimage
Flash FW to DUT, and make sure system boots up.
Change-Id: I7cb5b7f2bcdc6fbe0cbc640cad4af014f1a0edd6
Signed-off-by: YanRu Chen <kane_chen@pegatron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/28484
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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On rammus, headset uses DA7219 so that we need to enable it.
BUG=b:112945714
BRANCH=master
TEST=emerge-rammus coreboot chromeos-bootimage
Flash FW and check in kernel to see if DA7219 is up.
Change-Id: I92dd412374d007aab264661e698fbbbbcf1eae45
Signed-off-by: marxwang <marx.wang@intel.com>
Reviewed-on: https://review.coreboot.org/28537
Reviewed-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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On rammus, system halt was observed because of gspi clk value being set to 0.
Log info from serial coreboot:
FMAP: area RW_NVRAM found @ 9fa000 (24576 bytes)
SF: Detected FAST_SPI Hardware Sequencer with sector size 0x1000, total 0x1000000
VBNV: Restore from flash failed
ASSERTION ERROR: file 'src/soc/intel/common/block/gspi/gspi.c', line 443
gspi.c
442
443 assert(gspi_clk_mhz != 0);
444 assert(ref_clk_mhz != 0);
445 return (DIV_ROUND_UP(ref_clk_mhz, gspi_clk_mhz) - 1) & SSCR0_SCR_MASK;
BUG=none
BRANCH=master
TEST=emerge-rammus coreboot chromeos-ec chromeos-bootimage
Flash FW to DUT, and make sure system boots up.
Change-Id: Ibe3937902901b2cdc1a196415c08fabb0f3155f2
Signed-off-by: YanRu Chen <kane_chen@pegatron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/28405
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch adds the mainboard.c in order to support the sku id in smbios
table where the sku id is queried from the eeprom via EC.
BUG=b:113714761
BRANCH=master
TEST=check the result of 'dmidecode'
Change-Id: I3413784cca1ac10a2468d84f2d06c0e1d701fdcb
Signed-off-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-on: https://review.coreboot.org/28426
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Use the default value for Iccmax which is specified in vr_config.c.
The AcLoadline and DcLoadline keep the poppy value. Besides, the
USB 2.0 ports located on the mainboard are set to USB2_PORT_SHORT
and the others on the daughterboard are set to USB2_PORT_LONG.
Those setting need to be fine tuned later.
BUG=b:111579386
BRANCH=Master
TEST=Build pass
Change-Id: Icabfac04c94b3d480872c243d811509e274ef122
Signed-off-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-on: https://review.coreboot.org/27808
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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The gpio setting is based on the proto board schematics
BUG=b:111579386
BRANCH=Master
TEST=Build pass
Change-Id: I20fc081d372b8686f6128a7e85276f9c6798b199
Signed-off-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-on: https://review.coreboot.org/27807
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Add memory configuration based on the proto board schematics
BUG=b:111579386
BRANCH=Master
TEST=Build pass
Change-Id: I45efdc7893b5bcbca0de6e932e1452cc1a2ff028
Signed-off-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-on: https://review.coreboot.org/27806
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Rammus uses DA7219 Headset, Maxim MAX98927 Smart Amps and 4 channel dmic
BUG=b:111579386
BRANCH=Master
TEST=Build pass
Change-Id: If21a3870ee4b000a776d2f3e025fb43ef2fe48c7
Signed-off-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-on: https://review.coreboot.org/27805
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Move the build board directory from poppy to rammus.
BUG=b:111579386
BRANCH=Master
TEST=Build pass
Change-Id: I3a9fc2bbfe7261661f0c5c073baff0ff1434d09f
Signed-off-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-on: https://review.coreboot.org/27804
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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